211 lines
5.3 KiB
C
211 lines
5.3 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_types.h"
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#include "cmsis.h"
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#include "hal_analogif.h"
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#include "hal_location.h"
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#include "hal_spi.h"
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#define ANA_REG_CHIP_ID 0x00
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#define ANA_CHIP_ID_SHIFT (4)
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#define ANA_CHIP_ID_MASK (0xFFF << ANA_CHIP_ID_SHIFT)
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#define ANA_CHIP_ID(n) BITFIELD_VAL(ANA_CHIP_ID, n)
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#define ANA_VAL_CHIP_ID 0x18E
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// ISPI_ARBITRATOR_ENABLE should be defined when:
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// 1) BT and MCU will access RF register at the same time; or
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// 2) BT can access PMU/ANA, and BT will access RF register at the same time
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// when MCU is accessing PMU/ANA register
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#ifdef ISPI_ARBITRATOR_ENABLE
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// Min padding OSC cycles needed: BT=0 MCU=6
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// When OSC=26M and SPI=6.5M, min padding SPI cycles is BT=0 MCU=2
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#define PADDING_CYCLES 2
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#else
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#define PADDING_CYCLES 0
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#endif
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#define ANA_READ_CMD(r) (((1 << 24) | (((r) & 0xFF) << 16)) << PADDING_CYCLES)
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#define ANA_WRITE_CMD(r, v) (((((r) & 0xFF) << 16) | ((v) & 0xFFFF)) << PADDING_CYCLES)
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#define ANA_READ_VAL(v) (((v) >> PADDING_CYCLES) & 0xFFFF)
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#define ANA_PAGE_1 0xA010
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#define ANA_PAGE_0 0xA000
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static const BOOT_RODATA_SRAM_LOC uint8_t page_reg[3] = {
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0x00, 0x60, 0x80,
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};
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static const BOOT_RODATA_FLASH_LOC struct HAL_SPI_CFG_T spi_cfg = {
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.clk_delay_half = false,
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.clk_polarity = false,
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.slave = false,
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.dma_rx = false,
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.dma_tx = false,
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.rx_sep_line = false,
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.cs = 0,
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.rate = 6500000,
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.tx_bits = 25 + PADDING_CYCLES,
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.rx_bits = 25 + PADDING_CYCLES,
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.rx_frame_bits = 0,
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};
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static bool BOOT_BSS_LOC analogif_inited = false;
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static int BOOT_TEXT_SRAM_LOC hal_analogif_rawread(unsigned short reg, unsigned short *val)
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{
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int ret;
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unsigned int data;
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unsigned int cmd;
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data = 0;
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cmd = ANA_READ_CMD(reg);
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ret = hal_ispi_recv(&cmd, &data, 4);
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if (ret) {
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return ret;
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}
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*val = ANA_READ_VAL(data);
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return 0;
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}
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static int BOOT_TEXT_SRAM_LOC hal_analogif_rawwrite(unsigned short reg, unsigned short val)
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{
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int ret;
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unsigned int cmd;
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cmd = ANA_WRITE_CMD(reg, val);
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ret = hal_ispi_send(&cmd, 4);
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if (ret) {
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return ret;
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}
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return 0;
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}
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int BOOT_TEXT_SRAM_LOC hal_analogif_reg_read(unsigned short reg, unsigned short *val)
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{
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uint32_t lock;
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uint32_t idx;
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int ret;
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#if defined(USE_CYBERON)
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extern int cyb_efuse_check_status(void);
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if (cyb_efuse_check_status()) {
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if (reg == 0x5e) {
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*val = 49185;
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return 0;
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}
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if (reg == 0x00) {
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*val = 0x20e0;
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return 0;
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}
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}
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#endif
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if (reg < 0x100) {
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lock = int_lock();
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ret = hal_analogif_rawread(reg, val);
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int_unlock(lock);
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return ret;
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} else if (reg >= 0x100 && reg <= 0x15F) {
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idx = 0;
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} else if (reg >= 0x160 && reg <= 0x17F) {
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idx = 1;
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} else if (reg >= 0x180 && reg <= 0x1FF) {
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idx = 2;
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} else {
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return -1;
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}
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reg &= 0xFF;
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lock = int_lock();
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hal_analogif_rawwrite(page_reg[idx], ANA_PAGE_1);
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ret = hal_analogif_rawread(reg, val);
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hal_analogif_rawwrite(page_reg[idx], ANA_PAGE_0);
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int_unlock(lock);
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return ret;
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}
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int BOOT_TEXT_SRAM_LOC hal_analogif_reg_write(unsigned short reg, unsigned short val)
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{
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uint32_t lock;
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uint32_t idx;
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int ret;
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if (reg < 0x100) {
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lock = int_lock();
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ret = hal_analogif_rawwrite(reg, val);
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int_unlock(lock);
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return ret;
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} else if (reg >= 0x100 && reg <= 0x15F) {
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idx = 0;
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} else if (reg >= 0x160 && reg <= 0x17F) {
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idx = 1;
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} else if (reg >= 0x180 && reg <= 0x1FF) {
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idx = 2;
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} else {
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return -1;
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}
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reg &= 0xFF;
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lock = int_lock();
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hal_analogif_rawwrite(page_reg[idx], ANA_PAGE_1);
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ret = hal_analogif_rawwrite(reg, val);
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hal_analogif_rawwrite(page_reg[idx], ANA_PAGE_0);
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int_unlock(lock);
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return ret;
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}
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int BOOT_TEXT_FLASH_LOC hal_analogif_open(void)
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{
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int ret;
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unsigned short chip_id;
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const struct HAL_SPI_CFG_T *cfg_ptr;
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struct HAL_SPI_CFG_T cfg;
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if (analogif_inited) {
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// Restore the nominal rate
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cfg_ptr = &spi_cfg;
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} else {
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analogif_inited = true;
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// Crystal freq is unknown yet. Let SPI run on half of the nominal rate
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cfg = spi_cfg;
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cfg.rate /= 2;
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cfg_ptr = &cfg;
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}
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ret = hal_ispi_open(cfg_ptr);
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if (ret) {
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return ret;
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}
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ret = hal_analogif_rawread(ANA_REG_CHIP_ID, &chip_id);
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if (ret) {
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return ret;
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}
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if (GET_BITFIELD(chip_id, ANA_CHIP_ID) != ANA_VAL_CHIP_ID) {
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return -1;
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}
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return 0;
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}
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