277 lines
8.3 KiB
C
277 lines
8.3 KiB
C
/*----------------------------------------------------------------------------
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* RL-ARM - RTX
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*----------------------------------------------------------------------------
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* Name: RT_HAL_CM.H
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* Purpose: Hardware Abstraction Layer for Cortex-M definitions
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* Rev.: V4.60
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*----------------------------------------------------------------------------
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*
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* Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*---------------------------------------------------------------------------*/
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/* Definitions */
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#define INITIAL_xPSR 0x01000000
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#define DEMCR_TRCENA 0x01000000
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#define ITM_ITMENA 0x00000001
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#define MAGIC_WORD 0xE25A2EA5
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#if defined (__CC_ARM) /* ARM Compiler */
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#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
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#define __USE_EXCLUSIVE_ACCESS
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#else
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#undef __USE_EXCLUSIVE_ACCESS
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#endif
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#elif defined (__GNUC__) /* GNU Compiler */
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#undef __USE_EXCLUSIVE_ACCESS
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#if defined (__CORTEX_M0)
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#define __TARGET_ARCH_6S_M 1
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#else
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#define __TARGET_ARCH_6S_M 0
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#endif
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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#define __TARGET_FPU_VFP 1
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#else
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#define __TARGET_FPU_VFP 0
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#endif
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#define __inline inline
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#define __weak __attribute__((weak))
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#ifndef __CMSIS_GENERIC
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__attribute__((always_inline)) static inline void __enable_irq(void)
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{
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__asm volatile ("cpsie i");
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}
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__attribute__((always_inline)) static inline U32 __disable_irq(void)
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{
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U32 result;
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__asm volatile ("mrs %0, primask" : "=r" (result));
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__asm volatile ("cpsid i");
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return(result & 1);
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}
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#endif
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__attribute__(( always_inline)) static inline U8 __clz(U32 value)
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{
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U8 result;
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__asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
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return(result);
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}
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#elif defined (__ICCARM__) /* IAR Compiler */
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#undef __USE_EXCLUSIVE_ACCESS
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#if (__CORE__ == __ARM6M__)
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#define __TARGET_ARCH_6S_M 1
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#else
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#define __TARGET_ARCH_6S_M 0
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#endif
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#if defined __ARMVFP__
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#define __TARGET_FPU_VFP 1
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#else
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#define __TARGET_FPU_VFP 0
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#endif
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#define __inline inline
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#ifndef __CMSIS_GENERIC
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static inline void __enable_irq(void)
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{
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__asm volatile ("cpsie i");
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}
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static inline U32 __disable_irq(void)
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{
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U32 result;
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__asm volatile ("mrs %0, primask" : "=r" (result));
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__asm volatile ("cpsid i");
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return(result & 1);
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}
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#endif
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static inline U8 __clz(U32 value)
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{
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U8 result;
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__asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
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return(result);
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}
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#endif
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/* NVIC registers */
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#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
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#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
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#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
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#define NVIC_ISER ((volatile U32 *)0xE000E100)
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#define NVIC_ICER ((volatile U32 *)0xE000E180)
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#if (__TARGET_ARCH_6S_M)
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#define NVIC_IP ((volatile U32 *)0xE000E400)
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#else
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#define NVIC_IP ((volatile U8 *)0xE000E400)
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#endif
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#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
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#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
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#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
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#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
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#define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
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#define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
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#define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
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#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
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#define OS_LOCK() NVIC_ST_CTRL = 0x0005
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#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
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#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
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#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
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#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
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#if (__TARGET_ARCH_6S_M)
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#define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
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NVIC_ISER[n>>5] = 1 << (n & 0x1F)
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#else
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#define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
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NVIC_ISER[n>>5] = 1 << (n & 0x1F)
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#endif
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#define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
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#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
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/* Core Debug registers */
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#define DEMCR (*((volatile U32 *)0xE000EDFC))
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/* ITM registers */
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#define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
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#define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
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#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
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#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
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#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
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#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
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/* Variables */
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extern BIT dbg_msg;
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/* Functions */
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#ifdef __USE_EXCLUSIVE_ACCESS
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#define rt_inc(p) while(__strex((__ldrex(p)+1),p))
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#define rt_dec(p) while(__strex((__ldrex(p)-1),p))
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#else
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#define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
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#define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
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#endif
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__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
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U32 cnt,c2;
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#ifdef __USE_EXCLUSIVE_ACCESS
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do {
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if ((cnt = __ldrex(count)) == size) {
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__clrex();
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return (cnt); }
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} while (__strex(cnt+1, count));
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do {
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c2 = (cnt = __ldrex(first)) + 1;
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if (c2 == size) c2 = 0;
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} while (__strex(c2, first));
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#else
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__disable_irq();
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if ((cnt = *count) < size) {
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*count = cnt+1;
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c2 = (cnt = *first) + 1;
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if (c2 == size) c2 = 0;
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*first = c2;
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}
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__enable_irq ();
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#endif
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return (cnt);
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}
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__inline static void rt_systick_init (void) {
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NVIC_ST_RELOAD = os_trv;
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NVIC_ST_CURRENT = 0;
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NVIC_ST_CTRL = 0x0007;
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NVIC_SYS_PRI3 |= 0xFF000000;
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}
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__inline static void rt_svc_init (void) {
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#if !(__TARGET_ARCH_6S_M)
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int sh,prigroup;
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#endif
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NVIC_SYS_PRI3 |= 0x00FF0000;
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#if (__TARGET_ARCH_6S_M)
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NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
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#else
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sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
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prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
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if (prigroup >= sh) {
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sh = prigroup + 1;
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}
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NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
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#endif
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}
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extern void rt_set_PSP (U32 stack);
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extern U32 rt_get_PSP (void);
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extern void os_set_env (void);
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extern void *_alloc_box (void *box_mem);
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extern int _free_box (void *box_mem, void *box);
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extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
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extern void rt_ret_val (P_TCB p_TCB, U32 v0);
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extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
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extern void dbg_init (void);
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extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
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extern void dbg_task_switch (U32 task_id);
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#ifdef DBG_MSG
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#define DBG_INIT() dbg_init()
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#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
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#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
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dbg_task_switch(task_id)
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#else
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#define DBG_INIT()
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#define DBG_TASK_NOTIFY(p_tcb,create)
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#define DBG_TASK_SWITCH(task_id)
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#endif
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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