602 lines
15 KiB
C
602 lines
15 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_types.h"
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#include "plat_addr_map.h"
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#include "cmsis.h"
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#include "hal_cache.h"
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#include "hal_location.h"
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#if (CHIP_CACHE_VER < 2)
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#include "hal_norflash.h"
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#endif
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#include "hal_timer.h"
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#define HAL_CACHE_YES 1
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#define HAL_CACHE_NO 0
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/* cache controller */
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#if 0
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#elif defined(CHIP_BEST1000)
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#define CACHE_SIZE 0x1000
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#define CACHE_LINE_SIZE 0x10
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#elif defined(CHIP_BEST2000) || defined(CHIP_BEST3001)
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#define CACHE_SIZE 0x2000
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#define CACHE_LINE_SIZE 0x10
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#elif defined(CHIP_BEST2001)
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#define CACHE_SIZE 0x4000
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#define CACHE_LINE_SIZE 0x20
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#else
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#define CACHE_SIZE 0x2000
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#define CACHE_LINE_SIZE 0x20
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#endif
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#define CACHE_ASSOCIATIVITY_WAY_NUM 4
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/* reg value */
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#define CACHE_ENABLE_REG_OFFSET 0x00
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#define CACHE_INI_CMD_REG_OFFSET 0x04
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#define WRITEBUFFER_ENABLE_REG_OFFSET 0x08
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#define WRITEBUFFER_FLUSH_REG_OFFSET 0x0C
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#define LOCK_UNCACHEABLE_REG_OFFSET 0x10
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#define INVALIDATE_ADDRESS_REG_OFFSET 0x14
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#define INVALIDATE_SET_CMD_REG_OFFSET 0x18
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// Since best2300
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#define MONITOR_ENABLE_REG_OFFSET 0x1C
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#define MONITOR_CNT_READ_HIT0_REG_OFFSET 0x20
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#define MONITOR_CNT_READ_HIT1_REG_OFFSET 0x24
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#define MONITOR_CNT_READ_MISS0_REG_OFFSET 0x28
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#define MONITOR_CNT_READ_MISS1_REG_OFFSET 0x2C
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// Since best2300p
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#define STATUS_REG_OFFSET 0x30
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// Since best2300p
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#define SYNC_CMD_REG_OFFSET 0x34
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#define CACHE_EN (1 << 0)
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// Since best2300
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#define WRAP_EN (1 << 1)
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#define WRITEBUFFER_EN (1 << 0)
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// Since best2300
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#define WRITE_BACK_EN (1 << 1)
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#define LOCK_UNCACHEABLE (1 << 0)
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// Since best2300
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#define MONITOR_EN (1 << 0)
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#define CNT_READ_HIT_31_0_SHIFT (0)
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#define CNT_READ_HIT_31_0_MASK (0xFFFFFFFF << CNT_READ_HIT_31_0_SHIFT)
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#define CNT_READ_HIT_31_0(n) BITFIELD_VAL(CNT_READ_HIT_31_0, n)
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#define CNT_READ_HIT_39_32_SHIFT (0)
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#define CNT_READ_HIT_39_32_MASK (0xFF << CNT_READ_HIT_39_32_SHIFT)
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#define CNT_READ_HIT_39_32(n) BITFIELD_VAL(CNT_READ_HIT_39_32, n)
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// Since best2300p
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#define STATUS_FETCHING (1 << 0)
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/* read write */
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#define cacheip_write32(v,b,a) \
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(*((volatile uint32_t *)(b+a)) = v)
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#define cacheip_read32(b,a) \
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(*((volatile uint32_t *)(b+a)))
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__STATIC_FORCEINLINE void cacheip_enable_cache(uint32_t reg_base, uint32_t v)
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{
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uint32_t val;
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if (v) {
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val = CACHE_EN;
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} else {
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val = 0;
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}
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cacheip_write32(val, reg_base, CACHE_ENABLE_REG_OFFSET);
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}
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__STATIC_FORCEINLINE void cacheip_enable_wrap(uint32_t reg_base, uint32_t v)
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{
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uint32_t val;
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val = cacheip_read32(reg_base, CACHE_ENABLE_REG_OFFSET);
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if (v) {
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val |= WRAP_EN;
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} else {
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val &= ~WRAP_EN;
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}
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cacheip_write32(val, reg_base, CACHE_ENABLE_REG_OFFSET);
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}
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__STATIC_FORCEINLINE POSSIBLY_UNUSED int cacheip_wrap_enabled(uint32_t reg_base)
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{
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uint32_t val;
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val = cacheip_read32(reg_base, CACHE_ENABLE_REG_OFFSET);
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return !!(val & WRAP_EN);
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}
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__STATIC_FORCEINLINE void cacheip_init_cache(uint32_t reg_base)
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{
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cacheip_write32(1, reg_base, CACHE_INI_CMD_REG_OFFSET);
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}
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__STATIC_FORCEINLINE void cacheip_enable_writebuffer(uint32_t reg_base, uint32_t v)
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{
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// PSRAM controller V2 has an embedded write buffer and the cache write buffer can be ignored
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#if defined(CHIP_HAS_PSRAM) && defined(PSRAM_ENABLE) && defined(CHIP_PSRAM_CTRL_VER) && (CHIP_PSRAM_CTRL_VER == 1)
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uint32_t val;
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val = cacheip_read32(reg_base, WRITEBUFFER_ENABLE_REG_OFFSET);
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if (v) {
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val |= WRITEBUFFER_EN;
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} else {
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val &= ~WRITEBUFFER_EN;
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}
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cacheip_write32(val, reg_base, WRITEBUFFER_ENABLE_REG_OFFSET);
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#endif
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}
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__STATIC_FORCEINLINE void cacheip_enable_writeback(uint32_t reg_base, uint32_t v)
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{
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// Cache implements write back feature since PSRAM controller V2
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#if !defined(CHIP_BEST2001)
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#if (defined(CHIP_HAS_PSRAM) && defined(PSRAM_ENABLE) && defined(CHIP_PSRAM_CTRL_VER) && (CHIP_PSRAM_CTRL_VER >= 2)) || (defined(CHIP_HAS_PSRAMUHS) && defined(PSRAMUHS_ENABLE))
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uint32_t val;
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val = cacheip_read32(reg_base, WRITEBUFFER_ENABLE_REG_OFFSET);
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if (v) {
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val |= WRITE_BACK_EN;
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} else {
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val &= ~WRITE_BACK_EN;
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}
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cacheip_write32(val, reg_base, WRITEBUFFER_ENABLE_REG_OFFSET);
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#endif
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#endif
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}
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__STATIC_FORCEINLINE void cacheip_flush_writebuffer(uint32_t reg_base)
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{
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cacheip_write32(1, reg_base, WRITEBUFFER_FLUSH_REG_OFFSET);
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}
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__STATIC_FORCEINLINE void cacheip_set_invalidate_address(uint32_t reg_base, uint32_t v)
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{
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cacheip_write32(v, reg_base, INVALIDATE_ADDRESS_REG_OFFSET);
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}
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__STATIC_FORCEINLINE void cacheip_trigger_invalidate(uint32_t reg_base)
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{
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cacheip_write32(1, reg_base, INVALIDATE_SET_CMD_REG_OFFSET);
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}
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__STATIC_FORCEINLINE void cacheip_trigger_sync(uint32_t reg_base)
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{
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cacheip_write32(1, reg_base, SYNC_CMD_REG_OFFSET);
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}
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/* cache controller end */
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/* hal api */
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__STATIC_FORCEINLINE uint32_t _cache_get_reg_base(enum HAL_CACHE_ID_T id)
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{
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uint32_t base;
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if (id == HAL_CACHE_ID_I_CACHE) {
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base = ICACHE_CTRL_BASE;
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} else if (id == HAL_CACHE_ID_D_CACHE) {
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#ifdef DCACHE_CTRL_BASE
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base = DCACHE_CTRL_BASE;
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#else
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base = 0;
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#endif
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} else {
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base = 0;
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}
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return base;
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}
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uint8_t BOOT_TEXT_FLASH_LOC hal_cache_enable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_init_cache(reg_base);
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cacheip_enable_cache(reg_base, HAL_CACHE_YES);
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return 0;
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}
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uint8_t SRAM_TEXT_LOC hal_cache_disable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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#if !(defined(ROM_BUILD) || defined(PROGRAMMER))
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#if (CHIP_CACHE_VER >= 2)
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uint32_t val;
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do {
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val = cacheip_read32(reg_base, STATUS_REG_OFFSET);
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} while (val & STATUS_FETCHING);
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#else
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uint32_t time;
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time = hal_sys_timer_get();
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while (hal_norflash_busy() && (hal_sys_timer_get() - time) < MS_TO_TICKS(2));
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// Delay for at least 8 cycles till the cache becomes idle
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for (int delay = 0; delay < 8; delay++) {
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asm volatile("nop");
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}
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#endif
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#endif
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cacheip_enable_cache(reg_base, HAL_CACHE_NO);
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return 0;
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}
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uint8_t BOOT_TEXT_FLASH_LOC hal_cache_writebuffer_enable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_enable_writebuffer(reg_base, HAL_CACHE_YES);
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return 0;
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}
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uint8_t hal_cache_writebuffer_disable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_enable_writebuffer(reg_base, HAL_CACHE_NO);
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return 0;
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}
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uint8_t hal_cache_writebuffer_flush(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_flush_writebuffer(reg_base);
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return 0;
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}
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uint8_t BOOT_TEXT_FLASH_LOC hal_cache_writeback_enable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_enable_writeback(reg_base, HAL_CACHE_YES);
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return 0;
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}
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uint8_t hal_cache_writeback_disable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_enable_writeback(reg_base, HAL_CACHE_NO);
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return 0;
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}
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// Wrap is enabled during flash init
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uint8_t BOOT_TEXT_SRAM_LOC hal_cache_wrap_enable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_enable_wrap(reg_base, HAL_CACHE_YES);
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return 0;
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}
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uint8_t hal_cache_wrap_disable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_enable_wrap(reg_base, HAL_CACHE_NO);
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return 0;
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}
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// Flash timing calibration might need to invalidate cache
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uint8_t BOOT_TEXT_SRAM_LOC hal_cache_invalidate(enum HAL_CACHE_ID_T id, uint32_t start_address, uint32_t len)
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{
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uint32_t reg_base;
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uint32_t end_address;
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uint32_t lock;
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#ifndef DCACHE_CTRL_BASE
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if (id == HAL_CACHE_ID_D_CACHE) {
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id = HAL_CACHE_ID_I_CACHE;
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}
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#endif
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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lock = int_lock_global();
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#if defined(CHIP_BEST2300) || defined(CHIP_BEST1400)
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uint32_t time;
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time = hal_sys_timer_get();
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while (hal_norflash_busy() && (hal_sys_timer_get() - time) < MS_TO_TICKS(2));
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// Delay for at least 8 cycles till the cache becomes idle
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for (int delay = 0; delay < 8; delay++) {
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asm volatile("nop");
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}
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#endif
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if (len >= CACHE_SIZE / 2) {
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cacheip_init_cache(reg_base);
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cacheip_init_cache(reg_base);
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} else {
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end_address = start_address + len;
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start_address &= (~(CACHE_LINE_SIZE-1));
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while (start_address < end_address) {
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cacheip_set_invalidate_address(reg_base, start_address);
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cacheip_trigger_invalidate(reg_base);
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cacheip_trigger_invalidate(reg_base);
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start_address += CACHE_LINE_SIZE;
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}
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}
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int_unlock_global(lock);
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return 0;
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}
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uint8_t hal_cache_invalidate_all(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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//warning BEST1501 may change this reg offset to 0x38
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cacheip_write32(1, reg_base, CACHE_INI_CMD_REG_OFFSET);
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cacheip_write32(1, reg_base, CACHE_INI_CMD_REG_OFFSET);
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return 0;
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}
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uint8_t hal_cache_sync(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cache_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_trigger_sync(reg_base);
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return 0;
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}
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#ifdef CHIP_HAS_CP
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__STATIC_FORCEINLINE uint32_t _cachecp_get_reg_base(enum HAL_CACHE_ID_T id)
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{
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uint32_t base;
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if (id == HAL_CACHE_ID_I_CACHE) {
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base = ICACHECP_CTRL_BASE;
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} else if (id == HAL_CACHE_ID_D_CACHE) {
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#ifdef DCACHECP_CTRL_BASE
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base = DCACHECP_CTRL_BASE;
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#else
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base = 0;
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#endif
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} else {
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base = 0;
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}
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return base;
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}
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uint8_t hal_cachecp_enable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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uint32_t main_cache_reg_base;
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enum HAL_CMU_MOD_ID_T mod;
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reg_base = _cachecp_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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if (id == HAL_CACHE_ID_D_CACHE) {
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mod = HAL_CMU_H_DCACHECP;
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} else {
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mod = HAL_CMU_H_ICACHECP;
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}
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hal_cmu_clock_enable(mod);
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hal_cmu_reset_clear(mod);
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cacheip_init_cache(reg_base);
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cacheip_enable_cache(reg_base, HAL_CACHE_YES);
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// Init wrap option
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main_cache_reg_base = _cache_get_reg_base(id);
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if (main_cache_reg_base == 0) {
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return 0;
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}
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cacheip_enable_wrap(reg_base, cacheip_wrap_enabled(main_cache_reg_base));
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return 0;
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}
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uint8_t CP_TEXT_SRAM_LOC hal_cachecp_disable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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enum HAL_CMU_MOD_ID_T mod;
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reg_base = _cachecp_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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#if !(defined(ROM_BUILD) || defined(PROGRAMMER))
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uint32_t val;
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do {
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val = cacheip_read32(reg_base, STATUS_REG_OFFSET);
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} while (val & STATUS_FETCHING);
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#endif
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cacheip_enable_cache(reg_base, HAL_CACHE_NO);
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if (id == HAL_CACHE_ID_D_CACHE) {
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mod = HAL_CMU_H_DCACHECP;
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} else {
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mod = HAL_CMU_H_ICACHECP;
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}
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hal_cmu_reset_set(mod);
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hal_cmu_clock_disable(mod);
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return 0;
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}
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uint8_t hal_cachecp_writebuffer_enable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cachecp_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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}
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cacheip_enable_writebuffer(reg_base, HAL_CACHE_YES);
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return 0;
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}
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uint8_t hal_cachecp_writebuffer_disable(enum HAL_CACHE_ID_T id)
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{
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uint32_t reg_base = 0;
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reg_base = _cachecp_get_reg_base(id);
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if (reg_base == 0) {
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return 0;
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|
}
|
|
|
|
cacheip_enable_writebuffer(reg_base, HAL_CACHE_NO);
|
|
|
|
return 0;
|
|
}
|
|
uint8_t hal_cachecp_writebuffer_flush(enum HAL_CACHE_ID_T id)
|
|
{
|
|
uint32_t reg_base = 0;
|
|
|
|
reg_base = _cachecp_get_reg_base(id);
|
|
if (reg_base == 0) {
|
|
return 0;
|
|
}
|
|
|
|
cacheip_flush_writebuffer(reg_base);
|
|
|
|
return 0;
|
|
}
|
|
uint8_t hal_cachecp_writeback_enable(enum HAL_CACHE_ID_T id)
|
|
{
|
|
uint32_t reg_base = 0;
|
|
|
|
reg_base = _cachecp_get_reg_base(id);
|
|
if (reg_base == 0) {
|
|
return 0;
|
|
}
|
|
|
|
cacheip_enable_writeback(reg_base, HAL_CACHE_YES);
|
|
|
|
return 0;
|
|
}
|
|
uint8_t hal_cachecp_writeback_disable(enum HAL_CACHE_ID_T id)
|
|
{
|
|
uint32_t reg_base = 0;
|
|
|
|
reg_base = _cachecp_get_reg_base(id);
|
|
if (reg_base == 0) {
|
|
return 0;
|
|
}
|
|
|
|
cacheip_enable_writeback(reg_base, HAL_CACHE_NO);
|
|
|
|
return 0;
|
|
}
|
|
uint8_t CP_TEXT_SRAM_LOC hal_cachecp_invalidate(enum HAL_CACHE_ID_T id, uint32_t start_address, uint32_t len)
|
|
{
|
|
uint32_t reg_base;
|
|
uint32_t end_address;
|
|
|
|
#ifndef DCACHECP_CTRL_BASE
|
|
if (id == HAL_CACHE_ID_D_CACHE) {
|
|
id = HAL_CACHE_ID_I_CACHE;
|
|
}
|
|
#endif
|
|
|
|
reg_base = _cachecp_get_reg_base(id);
|
|
if (reg_base == 0) {
|
|
return 0;
|
|
}
|
|
|
|
if (len >= CACHE_SIZE / 2) {
|
|
cacheip_init_cache(reg_base);
|
|
cacheip_init_cache(reg_base);
|
|
} else {
|
|
end_address = start_address + len;
|
|
start_address &= (~(CACHE_LINE_SIZE-1));
|
|
while (start_address < end_address) {
|
|
cacheip_set_invalidate_address(reg_base, start_address);
|
|
cacheip_trigger_invalidate(reg_base);
|
|
cacheip_trigger_invalidate(reg_base);
|
|
start_address += CACHE_LINE_SIZE;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
uint8_t hal_cachecp_sync(enum HAL_CACHE_ID_T id)
|
|
{
|
|
uint32_t reg_base = 0;
|
|
|
|
reg_base = _cachecp_get_reg_base(id);
|
|
if (reg_base == 0) {
|
|
return 0;
|
|
}
|
|
|
|
cacheip_trigger_sync(reg_base);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|