124 lines
4.2 KiB
C
124 lines
4.2 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_addr_map.h"
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#include "cmsis.h"
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#include "hal_timer.h"
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#include "hal_location.h"
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#include "hal_psc.h"
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#include CHIP_SPECIFIC_HDR(reg_psc)
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#define PSC_WRITE_ENABLE 0xCAFE0000
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static struct AONPSC_T * const psc = (struct AONPSC_T *)AON_PSC_BASE;
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void BOOT_TEXT_FLASH_LOC hal_psc_init(void)
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{
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// Setup wakeup mask
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psc->REG_080 = 0xFFFFFFFF;
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psc->REG_084 = 0xFFFFFFFF;
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}
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void SRAM_TEXT_LOC hal_psc_core_auto_power_down(void)
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{
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psc->REG_018 = PSC_WRITE_ENABLE | 0;
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psc->REG_000 = PSC_WRITE_ENABLE | PSC_AON_MCU_PG_AUTO_EN;
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psc->REG_010 = PSC_WRITE_ENABLE | PSC_AON_MCU_POWERDN_START;
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}
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void SRAM_TEXT_LOC hal_psc_mcu_auto_power_up(void)
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{
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psc->REG_014 = PSC_WRITE_ENABLE | PSC_AON_MCU_POWERUP_START;
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}
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void BOOT_TEXT_FLASH_LOC hal_psc_codec_enable(void)
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{
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psc->REG_078 = PSC_WRITE_ENABLE |
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PSC_AON_CODEC_PSW_EN_DR |
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PSC_AON_CODEC_RESETN_ASSERT_DR | PSC_AON_CODEC_RESETN_ASSERT_REG |
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PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
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PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
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hal_sys_timer_delay(MS_TO_TICKS(1));
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psc->REG_078 = PSC_WRITE_ENABLE |
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PSC_AON_CODEC_PSW_EN_DR |
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PSC_AON_CODEC_RESETN_ASSERT_DR |
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PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
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PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
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psc->REG_078 = PSC_WRITE_ENABLE |
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PSC_AON_CODEC_PSW_EN_DR |
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PSC_AON_CODEC_RESETN_ASSERT_DR |
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PSC_AON_CODEC_ISO_EN_DR |
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PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
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psc->REG_078 = PSC_WRITE_ENABLE |
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PSC_AON_CODEC_PSW_EN_DR |
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PSC_AON_CODEC_RESETN_ASSERT_DR |
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PSC_AON_CODEC_ISO_EN_DR |
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PSC_AON_CODEC_CLK_STOP_DR;
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}
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void BOOT_TEXT_FLASH_LOC hal_psc_codec_disable(void)
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{
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psc->REG_078 = PSC_WRITE_ENABLE |
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PSC_AON_CODEC_PSW_EN_DR | PSC_AON_CODEC_PSW_EN_REG |
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PSC_AON_CODEC_RESETN_ASSERT_DR | PSC_AON_CODEC_RESETN_ASSERT_REG |
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PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
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PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
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}
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void BOOT_TEXT_FLASH_LOC hal_psc_bt_enable(void)
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{
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psc->REG_038 = PSC_WRITE_ENABLE |
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PSC_AON_BT_PSW_EN_DR |
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PSC_AON_BT_RESETN_ASSERT_DR | PSC_AON_BT_RESETN_ASSERT_REG |
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PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
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PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
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hal_sys_timer_delay(MS_TO_TICKS(1));
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psc->REG_038 = PSC_WRITE_ENABLE |
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PSC_AON_BT_PSW_EN_DR |
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PSC_AON_BT_RESETN_ASSERT_DR |
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PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
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PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
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psc->REG_038 = PSC_WRITE_ENABLE |
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PSC_AON_BT_PSW_EN_DR |
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PSC_AON_BT_RESETN_ASSERT_DR |
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PSC_AON_BT_ISO_EN_DR |
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PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
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psc->REG_038 = PSC_WRITE_ENABLE |
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PSC_AON_BT_PSW_EN_DR |
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PSC_AON_BT_RESETN_ASSERT_DR |
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PSC_AON_BT_ISO_EN_DR |
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PSC_AON_BT_CLK_STOP_DR;
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#ifdef JTAG_BT
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psc->REG_064 |= PSC_AON_CODEC_RESERVED(1 << 3);
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psc->REG_064 &= ~PSC_AON_CODEC_RESERVED(1 << 2);
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#endif
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}
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void BOOT_TEXT_FLASH_LOC hal_psc_bt_disable(void)
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{
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#ifdef JTAG_BT
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psc->REG_064 &= ~PSC_AON_CODEC_RESERVED(1 << 3);
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psc->REG_064 |= PSC_AON_CODEC_RESERVED(1 << 2);
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#endif
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psc->REG_038 = PSC_WRITE_ENABLE |
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PSC_AON_BT_PSW_EN_DR | PSC_AON_BT_PSW_EN_REG |
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PSC_AON_BT_RESETN_ASSERT_DR | PSC_AON_BT_RESETN_ASSERT_REG |
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PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
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PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
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}
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