266 lines
8.7 KiB
C
266 lines
8.7 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __HAL_CMU_BEST2300P_H__
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#define __HAL_CMU_BEST2300P_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HAL_CMU_VALID_CRYSTAL_FREQ { 26000000, 24000000, 40000000, 48000000, }
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enum HAL_CMU_MOD_ID_T {
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// HCLK/HRST
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HAL_CMU_MOD_H_MCU, // 0
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HAL_CMU_MOD_H_ROM0, // 1
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HAL_CMU_MOD_H_ROM1, // 2
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HAL_CMU_MOD_H_ROM2, // 3
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HAL_CMU_MOD_H_RAM0, // 4
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HAL_CMU_MOD_H_RAM1, // 5
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HAL_CMU_MOD_H_RAM2, // 6
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HAL_CMU_MOD_H_RAMRET, // 7
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HAL_CMU_MOD_H_AHB0, // 8
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HAL_CMU_MOD_H_AHB1, // 9
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HAL_CMU_MOD_H_AH2H_BT, // 10
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HAL_CMU_MOD_H_ADMA, // 11
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HAL_CMU_MOD_H_GDMA, // 12
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HAL_CMU_MOD_H_CACHE, // 13
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HAL_CMU_MOD_H_FLASH, // 14
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HAL_CMU_MOD_H_SDMMC, // 15
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HAL_CMU_MOD_H_USBC, // 16
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HAL_CMU_MOD_H_CODEC, // 17
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HAL_CMU_MOD_H_FFT, // 18
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HAL_CMU_MOD_H_I2C_SLAVE, // 19
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HAL_CMU_MOD_H_USBH, // 20
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HAL_CMU_MOD_H_SENSOR_ENG, // 21
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HAL_CMU_MOD_H_BT_DUMP, // 22
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HAL_CMU_MOD_H_CP, // 23
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HAL_CMU_MOD_H_RAM3, // 24
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HAL_CMU_MOD_H_RAM4, // 25
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HAL_CMU_MOD_H_RAM5, // 26
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HAL_CMU_MOD_H_RAM6, // 27
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HAL_CMU_MOD_H_SEC_ENG, // 28
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HAL_CMU_MOD_H_ICACHE0, // 29
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HAL_CMU_MOD_H_ICACHE1, // 30
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// PCLK/PRST
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HAL_CMU_MOD_P_CMU, // 31
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HAL_CMU_MOD_P_WDT, // 32
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HAL_CMU_MOD_P_TIMER0, // 33
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HAL_CMU_MOD_P_TIMER1, // 34
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HAL_CMU_MOD_P_TIMER2, // 35
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HAL_CMU_MOD_P_I2C0, // 36
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HAL_CMU_MOD_P_I2C1, // 37
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HAL_CMU_MOD_P_SPI, // 38
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HAL_CMU_MOD_P_SLCD, // 39
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HAL_CMU_MOD_P_SPI_ITN, // 40
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HAL_CMU_MOD_P_SPI_PHY, // 41
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HAL_CMU_MOD_P_UART0, // 42
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HAL_CMU_MOD_P_UART1, // 43
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HAL_CMU_MOD_P_UART2, // 44
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HAL_CMU_MOD_P_PCM, // 45
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HAL_CMU_MOD_P_I2S0, // 46
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HAL_CMU_MOD_P_SPDIF0, // 47
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HAL_CMU_MOD_P_I2S1, // 48
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HAL_CMU_MOD_P_SEC_ENG, // 49
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// OCLK/ORST
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HAL_CMU_MOD_O_SLEEP, // 50
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HAL_CMU_MOD_O_FLASH, // 51
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HAL_CMU_MOD_O_USB, // 52
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HAL_CMU_MOD_O_SDMMC, // 53
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HAL_CMU_MOD_O_WDT, // 54
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HAL_CMU_MOD_O_TIMER0, // 55
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HAL_CMU_MOD_O_TIMER1, // 56
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HAL_CMU_MOD_O_TIMER2, // 57
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HAL_CMU_MOD_O_I2C0, // 58
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HAL_CMU_MOD_O_I2C1, // 59
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HAL_CMU_MOD_O_SPI, // 60
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HAL_CMU_MOD_O_SLCD, // 61
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HAL_CMU_MOD_O_SPI_ITN, // 62
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HAL_CMU_MOD_O_SPI_PHY, // 63
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HAL_CMU_MOD_O_UART0, // 64
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HAL_CMU_MOD_O_UART1, // 65
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HAL_CMU_MOD_O_UART2, // 66
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HAL_CMU_MOD_O_I2S0, // 67
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HAL_CMU_MOD_O_SPDIF0, // 68
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HAL_CMU_MOD_O_PCM, // 69
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HAL_CMU_MOD_O_USB32K, // 70
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HAL_CMU_MOD_O_I2S1, // 71
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// AON ACLK/ARST
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HAL_CMU_AON_A_CMU, // 72
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HAL_CMU_AON_A_GPIO, // 73
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HAL_CMU_AON_A_GPIO_INT, // 74
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HAL_CMU_AON_A_WDT, // 75
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HAL_CMU_AON_A_PWM, // 76
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HAL_CMU_AON_A_TIMER, // 77
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HAL_CMU_AON_A_PSC, // 78
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HAL_CMU_AON_A_IOMUX, // 79
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HAL_CMU_AON_A_APBC, // 80
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HAL_CMU_AON_A_H2H_MCU, // 81
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// AON OCLK/ORST
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HAL_CMU_AON_O_WDT, // 82
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HAL_CMU_AON_O_TIMER, // 83
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HAL_CMU_AON_O_GPIO, // 84
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HAL_CMU_AON_O_PWM0, // 85
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HAL_CMU_AON_O_PWM1, // 86
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HAL_CMU_AON_O_PWM2, // 87
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HAL_CMU_AON_O_PWM3, // 88
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HAL_CMU_AON_O_IOMUX, // 89
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HAL_CMU_AON_O_SLP32K, // 90
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HAL_CMU_AON_O_SLP26M, // 91
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HAL_CMU_AON_RESERVED0, // 92
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HAL_CMU_AON_RESERVED1, // 93
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HAL_CMU_AON_RESERVED2, // 94
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HAL_CMU_AON_RESERVED3, // 95
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// AON SUBSYS
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HAL_CMU_AON_MCU, // 96
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HAL_CMU_AON_CODEC, // 97
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HAL_CMU_AON_RESERVED4, // 98
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HAL_CMU_AON_BT, // 99
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HAL_CMU_AON_MCUCPU, // 100
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HAL_CMU_AON_RESERVED5, // 101
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HAL_CMU_AON_BTCPU, // 102
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HAL_CMU_AON_GLOBAL, // 103
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HAL_CMU_MOD_QTY,
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HAL_CMU_MOD_GLOBAL = HAL_CMU_AON_GLOBAL,
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HAL_CMU_MOD_BT = HAL_CMU_AON_BT,
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HAL_CMU_MOD_BTCPU = HAL_CMU_AON_BTCPU,
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HAL_CMU_MOD_P_PWM = HAL_CMU_AON_A_PWM,
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HAL_CMU_MOD_O_PWM0 = HAL_CMU_AON_O_PWM0,
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HAL_CMU_MOD_O_PWM1 = HAL_CMU_AON_O_PWM1,
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HAL_CMU_MOD_O_PWM2 = HAL_CMU_AON_O_PWM2,
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HAL_CMU_MOD_O_PWM3 = HAL_CMU_AON_O_PWM3,
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HAL_CMU_H_ICACHECP = HAL_CMU_MOD_H_ICACHE0,
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HAL_CMU_H_DCACHECP = HAL_CMU_MOD_QTY,
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// TO BE REMOVED
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HAL_CMU_MOD_P_CODEC = HAL_CMU_MOD_QTY,
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HAL_CMU_MOD_O_CODEC_DA = HAL_CMU_MOD_QTY,
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HAL_CMU_MOD_O_CODEC_AD = HAL_CMU_MOD_QTY,
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};
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enum HAL_CMU_CLOCK_OUT_ID_T {
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HAL_CMU_CLOCK_OUT_AON_32K = 0x00,
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HAL_CMU_CLOCK_OUT_AON_26M = 0x01,
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HAL_CMU_CLOCK_OUT_AON_52M = 0x02,
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HAL_CMU_CLOCK_OUT_AON_DIG_52M = 0x03,
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HAL_CMU_CLOCK_OUT_AON_DIG_104M = 0x04,
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HAL_CMU_CLOCK_OUT_AON_PER = 0x05,
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HAL_CMU_CLOCK_OUT_AON_USB = 0x06,
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HAL_CMU_CLOCK_OUT_AON_DCDC = 0x07,
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HAL_CMU_CLOCK_OUT_AON_CHCLK = 0x08,
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HAL_CMU_CLOCK_OUT_AON_SPDIF0 = 0x09,
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HAL_CMU_CLOCK_OUT_AON_MCU = 0x0A,
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HAL_CMU_CLOCK_OUT_AON_FLASH = 0x0B,
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HAL_CMU_CLOCK_OUT_AON_SYS = 0x0C,
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HAL_CMU_CLOCK_OUT_BT_32K = 0x40,
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HAL_CMU_CLOCK_OUT_BT_SYS = 0x41,
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HAL_CMU_CLOCK_OUT_BT_52M = 0x42,
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HAL_CMU_CLOCK_OUT_BT_26MI = 0x43,
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HAL_CMU_CLOCK_OUT_BT_13M = 0x44,
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HAL_CMU_CLOCK_OUT_BT_12M = 0x45,
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HAL_CMU_CLOCK_OUT_BT_ADC = 0x46,
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HAL_CMU_CLOCK_OUT_BT_ADC2 = 0x47,
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HAL_CMU_CLOCK_OUT_BT_24M = 0x48,
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HAL_CMU_CLOCK_OUT_BT_26M = 0x49,
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HAL_CMU_CLOCK_OUT_MCU_32K = 0x60,
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HAL_CMU_CLOCK_OUT_MCU_SYS = 0x61,
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HAL_CMU_CLOCK_OUT_MCU_FLASH = 0x62,
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HAL_CMU_CLOCK_OUT_MCU_USB = 0x63,
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HAL_CMU_CLOCK_OUT_MCU_PCLK = 0x64,
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HAL_CMU_CLOCK_OUT_MCU_I2S = 0x65,
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HAL_CMU_CLOCK_OUT_MCU_PCM = 0x66,
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HAL_CMU_CLOCK_OUT_MCU_SPDIF0 = 0x67,
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HAL_CMU_CLOCK_OUT_MCU_SDMMC = 0x68,
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HAL_CMU_CLOCK_OUT_MCU_SPI2 = 0x69,
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HAL_CMU_CLOCK_OUT_MCU_SPI0 = 0x6A,
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HAL_CMU_CLOCK_OUT_MCU_SPI1 = 0x6B,
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HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA = 0x80,
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HAL_CMU_CLOCK_OUT_CODEC_CODEC = 0x81,
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HAL_CMU_CLOCK_OUT_CODEC_IIR = 0x82,
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HAL_CMU_CLOCK_OUT_CODEC_RS = 0x83,
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HAL_CMU_CLOCK_OUT_CODEC_HCLK = 0x84,
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};
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enum HAL_CMU_I2S_MCLK_ID_T {
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HAL_CMU_I2S_MCLK_PLLCODEC = 0x00,
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HAL_CMU_I2S_MCLK_CODEC = 0x01,
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HAL_CMU_I2S_MCLK_PLLIIR = 0x02,
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HAL_CMU_I2S_MCLK_PLLRS = 0x03,
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HAL_CMU_I2S_MCLK_PLLSPDIF0 = 0x04,
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HAL_CMU_I2S_MCLK_PLLPCM = 0x05,
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HAL_CMU_I2S_MCLK_PER = 0x06,
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HAL_CMU_I2S_MCLK_CLK_OUT = 0x07,
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};
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enum HAL_I2S_ID_T {
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HAL_I2S_ID_0 = 0,
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HAL_I2S_ID_1,
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HAL_I2S_ID_QTY,
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};
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#define HAL_I2S_ID_T HAL_I2S_ID_T
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enum HAL_CMU_ANC_CLK_USER_T {
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HAL_CMU_ANC_CLK_USER_ANC,
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HAL_CMU_ANC_CLK_USER_QTY
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};
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enum HAL_CMU_LOW_SYS_FREQ_T {
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HAL_CMU_LOW_SYS_FREQ_NONE,
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HAL_CMU_LOW_SYS_FREQ_13M,
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HAL_CMU_LOW_SYS_FREQ_6P5M,
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HAL_CMU_LOW_SYS_FREQ_4P33M,
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HAL_CMU_LOW_SYS_FREQ_3P25M,
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};
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void hal_cmu_low_sys_clock_set(enum HAL_CMU_LOW_SYS_FREQ_T freq);
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int hal_cmu_fast_timer_offline(void);
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void hal_cmu_anc_enable(enum HAL_CMU_ANC_CLK_USER_T user);
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void hal_cmu_anc_disable(enum HAL_CMU_ANC_CLK_USER_T user);
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int hal_cmu_anc_get_status(enum HAL_CMU_ANC_CLK_USER_T user);
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void hal_cmu_codec_vad_clock_enable(uint32_t enabled);
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uint32_t hal_cmu_get_aon_chip_id(void);
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uint32_t hal_cmu_get_aon_revision_id(void);
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void hal_cmu_cp_enable(uint32_t sp, uint32_t entry);
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void hal_cmu_cp_disable(void);
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uint32_t hal_cmu_cp_get_entry_addr(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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