142 lines
5.9 KiB
C
142 lines
5.9 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_BTPCMIP_H_
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#define __REG_BTPCMIP_H_
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#include "plat_types.h"
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#define BTPCMIP_FIFO_DEPTH 8
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/* btpcmip register */
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/* enable register */
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#define BTPCMIP_ENABLE_REG_REG_OFFSET 0x0
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#define BTPCMIP_ENABLE_REG_BTPCM_ENABLE_SHIFT (0)
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#define BTPCMIP_ENABLE_REG_BTPCM_ENABLE_MASK ((0x1)<<BTPCMIP_ENABLE_REG_BTPCM_ENABLE_SHIFT)
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/* recv fifo flush register */
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#define BTPCMIP_RX_FIFO_FLUSH_REG_OFFSET 0x4
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#define BTPCMIP_RX_FIFO_FLUSH_SHIFT (0)
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#define BTPCMIP_RX_FIFO_FLUSH_MASK ((0x1)<<BTPCMIP_RX_FIFO_FLUSH_SHIFT)
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/* send fifo flush register */
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#define BTPCMIP_TX_FIFO_FLUSH_REG_OFFSET 0x8
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#define BTPCMIP_TX_FIFO_FLUSH_SHIFT (0)
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#define BTPCMIP_TX_FIFO_FLUSH_MASK ((0x1)<<BTPCMIP_TX_FIFO_FLUSH_SHIFT)
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/* send buffer register */
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#define BTPCMIP_TX_BUFF_REG_OFFSET 0xc
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/* recv buffer register */
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#define BTPCMIP_RX_BUFF_REG_OFFSET 0xc
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/* config register */
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#define BTPCMIP_CR_REG_OFFSET 0x10
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#define BTPCMIP_CR_MASK2_SHIFT (21)
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#define BTPCMIP_CR_MASK2_MASK ((0x1)<<BTPCMIP_CR_MASK2_SHIFT)
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#define BTPCMIP_CR_SYNCSHORT_SHIFT (20)
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#define BTPCMIP_CR_SYNCSHORT_MASK ((0x1)<<BTPCMIP_CR_SYNCSHORT_SHIFT)
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#define BTPCMIP_CR_MASK1_SHIFT (19)
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#define BTPCMIP_CR_MASK1_MASK ((0x1)<<BTPCMIP_CR_MASK1_SHIFT)
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#define BTPCMIP_CR_LENTH_SHIFT (16)
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#define BTPCMIP_CR_LENTH_MASK ((0x7)<<BTPCMIP_CR_LENTH_SHIFT)
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// Since 1302
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#define BTPCMIP_CR_PCM_CLK_OPEN_EN_SHIFT (15)
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#define BTPCMIP_CR_PCM_CLK_OPEN_EN_MASK ((0x1)<<BTPCMIP_CR_PCM_CLK_OPEN_EN_SHIFT)
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// -- End of since 1302
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#define BTPCMIP_CR_SLOTSEL_SHIFT (0)
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#define BTPCMIP_CR_SLOTSEL_MASK ((0x7)<<BTPCMIP_CR_SLOTSEL_SHIFT)
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/* rx config register */
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#define BTPCMIP_RCR0_REG_OFFSET 0x14
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#define BTPCMIP_RCR0_SIGNEXTIN_SHIFT (4)
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#define BTPCMIP_RCR0_SIGNEXTIN_MASK ((0x1)<<BTPCMIP_RCR0_SIGNEXTIN_SHIFT)
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#define BTPCMIP_RCR0_MSBIN_SHIFT (3)
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#define BTPCMIP_RCR0_MSBIN_MASK ((0x1)<<BTPCMIP_RCR0_MSBIN_SHIFT)
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#define BTPCMIP_RCR0_SIGNIN_SHIFT (2)
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#define BTPCMIP_RCR0_SIGNIN_MASK ((0x1)<<BTPCMIP_RCR0_SIGNIN_SHIFT)
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#define BTPCMIP_RCR0_2SIN_SHIFT (1)
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#define BTPCMIP_RCR0_2SIN_MASK ((0x1)<<BTPCMIP_RCR0_2SIN_SHIFT)
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#define BTPCMIP_RCR0_1SIN_SHIFT (0)
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#define BTPCMIP_RCR0_1SIN_MASK ((0x1)<<BTPCMIP_RCR0_1SIN_SHIFT)
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/* tx config register */
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#define BTPCMIP_TCR0_REG_OFFSET 0x18
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#define BTPCMIP_TCR0_SIGNEXTO_SHIFT (4)
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#define BTPCMIP_TCR0_SIGNEXTO_MASK ((0x1)<<BTPCMIP_TCR0_SIGNEXTO_SHIFT)
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#define BTPCMIP_TCR0_MSBO_SHIFT (3)
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#define BTPCMIP_TCR0_MSBO_MASK ((0x1)<<BTPCMIP_TCR0_MSBO_SHIFT)
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#define BTPCMIP_TCR0_SIGNO_SHIFT (2)
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#define BTPCMIP_TCR0_SIGNO_MASK ((0x1)<<BTPCMIP_TCR0_SIGNO_SHIFT)
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#define BTPCMIP_TCR0_2SO_SHIFT (1)
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#define BTPCMIP_TCR0_2SO_MASK ((0x1)<<BTPCMIP_TCR0_2SO_SHIFT)
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#define BTPCMIP_TCR0_1SO_SHIFT (0)
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#define BTPCMIP_TCR0_1SO_MASK ((0x1)<<BTPCMIP_TCR0_1SO_SHIFT)
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/* int status register */
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#define BTPCMIP_INT_STATUS_REG_OFFSET 0x1c
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#define BTPCMIP_INT_STATUS_TX_FIFO_OVER_SHIFT (5)
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#define BTPCMIP_INT_STATUS_TX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_STATUS_TX_FIFO_OVER_SHIFT)
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#define BTPCMIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT (4)
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#define BTPCMIP_INT_STATUS_TX_FIFO_EMPTY_MASK ((0x1)<<BTPCMIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT)
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#define BTPCMIP_INT_STATUS_RX_FIFO_OVER_SHIFT (1)
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#define BTPCMIP_INT_STATUS_RX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_STATUS_RX_FIFO_OVER_SHIFT)
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#define BTPCMIP_INT_STATUS_RX_FIFO_DA_SHIFT (0)
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#define BTPCMIP_INT_STATUS_RX_FIFO_DA_MASK ((0x1)<<BTPCMIP_INT_STATUS_RX_FIFO_DA_SHIFT)
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/* int mask register */
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#define BTPCMIP_INT_MASK_REG_OFFSET 0x20
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#define BTPCMIP_INT_MASK_TX_FIFO_OVER_SHIFT (5)
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#define BTPCMIP_INT_MASK_TX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_MASK_TX_FIFO_OVER_SHIFT)
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#define BTPCMIP_INT_MASK_TX_FIFO_EMPTY_SHIFT (4)
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#define BTPCMIP_INT_MASK_TX_FIFO_EMPTY_MASK ((0x1)<<BTPCMIP_INT_MASK_TX_FIFO_EMPTY_SHIFT)
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#define BTPCMIP_INT_MASK_RX_FIFO_OVER_SHIFT (1)
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#define BTPCMIP_INT_MASK_RX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_MASK_RX_FIFO_OVER_SHIFT)
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#define BTPCMIP_INT_MASK_RX_FIFO_DA_SHIFT (0)
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#define BTPCMIP_INT_MASK_RX_FIFO_DA_MASK ((0x1)<<BTPCMIP_INT_MASK_RX_FIFO_DA_SHIFT)
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#define BTPCMIP_INT_MASK_ALL \
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(BTPCMIP_INT_MASK_TX_FIFO_OVER_MASK|BTPCMIP_INT_MASK_TX_FIFO_EMPTY_MASK|BTPCMIP_INT_MASK_RX_FIFO_OVER_MASK|BTPCMIP_INT_MASK_RX_FIFO_DA_MASK)
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#define BTPCMIP_INT_UNMASK_ALL 0
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/* clr recv over flow register */
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#define BTPCMIP_CLR_RX_OVER_FLOW_REG_OFFSET 0x24
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#define BTPCMIP_CLR_RX_OVER_FLOW_CLR_SHIFT (0)
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#define BTPCMIP_CLR_RX_OVER_FLOW_CLR_MASK ((0x1)<<BTPCMIP_CLR_RX_OVER_FLOW_CLR_SHIFT)
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/* clr send over flow register */
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#define BTPCMIP_CLR_TX_OVER_FLOW_REG_OFFSET 0x28
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#define BTPCMIP_CLR_TX_OVER_FLOW_CLR_SHIFT (0)
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#define BTPCMIP_CLR_TX_OVER_FLOW_CLR_MASK ((0x1)<<BTPCMIP_CLR_TX_OVER_FLOW_CLR_SHIFT)
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/* recv fifo config register */
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#define BTPCMIP_RX_FIFO_CFG_REG_OFFSET 0x2c
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#define BTPCMIP_RX_FIFO_CFG_LEVEL_SHIFT (0)
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#define BTPCMIP_RX_FIFO_CFG_LEVEL_MASK ((0xf)<<BTPCMIP_RX_FIFO_CFG_LEVEL_SHIFT)
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/* send fifo config register */
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#define BTPCMIP_TX_FIFO_CFG_REG_OFFSET 0x30
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#define BTPCMIP_TX_FIFO_CFG_LEVEL_SHIFT (0)
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#define BTPCMIP_TX_FIFO_CFG_LEVEL_MASK ((0xf)<<BTPCMIP_TX_FIFO_CFG_LEVEL_SHIFT)
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/* dma ctrl register */
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#define BTPCMIP_DMA_CTRL_REG_OFFSET 0x34
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#define BTPCMIP_DMA_CTRL_TX_ENABLE_SHIFT (1)
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#define BTPCMIP_DMA_CTRL_TX_ENABLE_MASK ((0x1)<<BTPCMIP_DMA_CTRL_TX_ENABLE_SHIFT)
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#define BTPCMIP_DMA_CTRL_RX_ENABLE_SHIFT (0)
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#define BTPCMIP_DMA_CTRL_RX_ENABLE_MASK ((0x1)<<BTPCMIP_DMA_CTRL_RX_ENABLE_SHIFT)
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/* btpcmip register end */
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#endif /* __REG_BTPCMIP_H_ */
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