243 lines
6.5 KiB
C
243 lines
6.5 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_types.h"
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#include "plat_addr_map.h"
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#include "cmsis.h"
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#include "cmsis_nvic.h"
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#include "hal_timer.h"
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#include "hal_trace.h"
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#include "hal_uart.h"
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#include "hal_wdt.h"
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#if defined(CHIP_BEST3001) || defined(CHIP_BEST3003) || defined(CHIP_BEST3005) || defined(CHIP_BEST1400) || defined(CHIP_BEST1402)
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#define CLOCK_SYNC_WORKAROUND
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#endif
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#define SLOW_TIMER_VAL_DELTA 1
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#define FAST_TIMER_VAL_DELTA 20
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/* wdt controller */
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/* reg address */
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/* default timeout in seconds */
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#define DEFAULT_TIMEOUT 60
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#define WDT_RATE CONFIG_SYSTICK_HZ
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/* watchdog register offsets and masks */
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#define WDTLOAD_REG_OFFSET 0x000
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#define WDTLOAD_LOAD_MIN 0x00000001
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#define WDTLOAD_LOAD_MAX 0xFFFFFFFF
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#define WDTVALUE_REG_OFFSET 0x004
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#define WDTCONTROL_REG_OFFSET 0x008
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#define WDTCONTROL_REG_INT_ENABLE (1 << 0)
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#define WDTCONTROL_REG_RESET_ENABLE (1 << 1)
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#define WDTINTCLR_REG_OFFSET 0x00C
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#define WDTRIS_REG_OFFSET 0x010
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#define WDTRIS_REG_INT_MASK (1 << 0)
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#define WDTMIS_REG_OFFSET 0x014
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#define WDTMIS_REG_INT_MASK (1 << 0)
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#define WDTLOCK_REG_OFFSET 0xC00
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#define WDTLOCK_REG_UNLOCK 0x1ACCE551
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#define WDTLOCK_REG_LOCK 0x00000001
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/* read write */
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#define wdtip_write32(v,b,a) \
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(*((volatile unsigned int *)(b+a)) = v)
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#define wdtip_read32(b,a) \
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(*((volatile unsigned int *)(b+a)))
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#if 1
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typedef void (*HAL_WDT_IRQ_HANDLER)(void);
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struct HAL_WDT_CTX {
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unsigned int load_val;
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};
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struct HAL_WDT_CTX hal_wdt_ctx[HAL_WDT_ID_NUM];
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static void _wdt1_irq_handler(void);
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HAL_WDT_IRQ_HANDLER hal_wdt_irq_handler[HAL_WDT_ID_NUM] =
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{
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_wdt1_irq_handler,
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};
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HAL_WDT_IRQ_CALLBACK hal_wdt_irq_callback[HAL_WDT_ID_NUM];
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static void _wdt1_irq_handler(void)
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{
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if (hal_wdt_irq_callback[HAL_WDT_ID_0] != 0) {
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hal_wdt_irq_callback[HAL_WDT_ID_0](HAL_WDT_ID_0, HAL_WDT_EVENT_FIRE);
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}
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}
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static unsigned int _wdt_get_base(enum HAL_WDT_ID_T id)
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{
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switch(id) {
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default:
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case HAL_WDT_ID_0:
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return WDT_BASE;
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break;
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}
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return 0;
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}
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static void _wdt_load(enum HAL_WDT_ID_T id)
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{
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unsigned int reg_base = 0;
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struct HAL_WDT_CTX *wdt = &hal_wdt_ctx[id];
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uint32_t lock;
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reg_base = _wdt_get_base(id);
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lock = int_lock();
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wdtip_write32(WDTLOCK_REG_UNLOCK, reg_base, WDTLOCK_REG_OFFSET);
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#ifdef CLOCK_SYNC_WORKAROUND
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uint32_t val;
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do {
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wdtip_write32(wdt->load_val, reg_base, WDTLOAD_REG_OFFSET);
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val = wdtip_read32(reg_base, WDTVALUE_REG_OFFSET);
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} while ((wdt->load_val < val) || (wdt->load_val > val + SLOW_TIMER_VAL_DELTA));
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#else
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wdtip_write32(wdt->load_val, reg_base, WDTLOAD_REG_OFFSET);
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#endif
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wdtip_write32(WDTLOCK_REG_LOCK, reg_base, WDTLOCK_REG_OFFSET);
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int_unlock(lock);
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/* Flush posted writes. */
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wdtip_read32(reg_base, WDTLOCK_REG_OFFSET);
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}
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static void _wdt_config(enum HAL_WDT_ID_T id)
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{
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unsigned int reg_base = 0;
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uint32_t lock;
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reg_base = _wdt_get_base(id);
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lock = int_lock();
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wdtip_write32(WDTLOCK_REG_UNLOCK, reg_base, WDTLOCK_REG_OFFSET);
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wdtip_write32(WDTRIS_REG_INT_MASK, reg_base, WDTINTCLR_REG_OFFSET);
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wdtip_write32(WDTCONTROL_REG_INT_ENABLE | WDTCONTROL_REG_RESET_ENABLE, reg_base, WDTCONTROL_REG_OFFSET);
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wdtip_write32(WDTLOCK_REG_LOCK, reg_base, WDTLOCK_REG_OFFSET);
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int_unlock(lock);
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/* Flush posted writes. */
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wdtip_read32(reg_base, WDTLOCK_REG_OFFSET);
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}
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static int wdt_start;
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/* mandatory operations */
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int hal_wdt_start(enum HAL_WDT_ID_T id)
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{
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_wdt_load(id);
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_wdt_config(id);
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wdt_start = 1;
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return 0;
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}
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int hal_wdt_stop(enum HAL_WDT_ID_T id)
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{
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unsigned int reg_base = 0;
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uint32_t lock;
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reg_base = _wdt_get_base(id);
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lock = int_lock();
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wdtip_write32(WDTLOCK_REG_UNLOCK, reg_base, WDTLOCK_REG_OFFSET);
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wdtip_write32(0, reg_base, WDTCONTROL_REG_OFFSET);
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wdtip_write32(WDTLOCK_REG_LOCK, reg_base, WDTLOCK_REG_OFFSET);
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int_unlock(lock);
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/* Flush posted writes. */
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wdtip_read32(reg_base, WDTLOCK_REG_OFFSET);
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wdt_start = 0;
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return 0;
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}
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/* optional operations */
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int hal_wdt_ping(enum HAL_WDT_ID_T id)
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{
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if (wdt_start) {
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_wdt_load(id);
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}
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return 0;
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}
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int hal_wdt_set_timeout(enum HAL_WDT_ID_T id, unsigned int timeout)
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{
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uint64_t load;
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struct HAL_WDT_CTX *wdt = &hal_wdt_ctx[id];
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/*
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* sp805 runs counter with given value twice, after the end of first
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* counter it gives an interrupt and then starts counter again. If
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* interrupt already occurred then it resets the system. This is why
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* load is half of what should be required.
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*/
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load = WDT_RATE * timeout - 1;
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load = (load > WDTLOAD_LOAD_MAX) ? WDTLOAD_LOAD_MAX: load;
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load = (load < WDTLOAD_LOAD_MIN) ? WDTLOAD_LOAD_MIN: load;
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wdt->load_val = load;
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return 0;
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}
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unsigned int hal_wdt_get_timeleft(enum HAL_WDT_ID_T id)
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{
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uint64_t load;
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unsigned int reg_base = 0;
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struct HAL_WDT_CTX *wdt = &hal_wdt_ctx[id];
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reg_base = _wdt_get_base(id);
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load = wdtip_read32(reg_base, WDTVALUE_REG_OFFSET);
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/*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
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if (!(wdtip_read32(reg_base, WDTRIS_REG_OFFSET) & WDTRIS_REG_INT_MASK))
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load += wdt->load_val + 1;
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return load/WDT_RATE;
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}
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void hal_wdt_set_irq_callback(enum HAL_WDT_ID_T id, HAL_WDT_IRQ_CALLBACK cb)
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{
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switch(id) {
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default:
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case HAL_WDT_ID_0:
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NVIC_SetVector(WDT_IRQn, (uint32_t)hal_wdt_irq_handler[id]);
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NVIC_SetPriority(WDT_IRQn, IRQ_PRIORITY_NORMAL);
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NVIC_ClearPendingIRQ(WDT_IRQn);
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NVIC_EnableIRQ(WDT_IRQn);
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break;
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}
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hal_wdt_irq_callback[id] = cb;
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}
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#endif
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