58 lines
2.4 KiB
C
58 lines
2.4 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_BTCMU_BEST2300P_H__
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#define __REG_BTCMU_BEST2300P_H__
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#include "plat_types.h"
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struct BTCMU_T {
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__IO uint32_t CLK_ENABLE; // 0x00
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__IO uint32_t CLK_DISABLE; // 0x04
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__IO uint32_t CLK_MODE; // 0x08
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__IO uint32_t DIV_TIMER; // 0x0C
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__IO uint32_t RESET_SET; // 0x10
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__IO uint32_t RESET_CLR; // 0x14
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__IO uint32_t DIV_WDT; // 0x18
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__IO uint32_t RESET_PULSE; // 0x1C
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uint32_t RESERVED_020[0x24 / 4]; // 0x20
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__IO uint32_t CLK_OUT; // 0x44
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uint32_t RESERVED_048[2]; // 0x48
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__IO uint32_t ISIRQ_SET; // 0x50
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__IO uint32_t ISIRQ_CLR; // 0x54
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};
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// reg_44
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#define BT_CMU_CAL_TIME(n) (((n) & 0xFF) << 0)
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#define BT_CMU_CAL_TIME_MASK (0xFF << 0)
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#define BT_CMU_CAL_TIME_SHIFT (0)
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#define BT_CMU_SMP_CMU_SEL(n) (((n) & 0xF) << 8)
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#define BT_CMU_SMP_CMU_SEL_MASK (0xF << 8)
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#define BT_CMU_SMP_CMU_SEL_SHIFT (8)
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#define BT_CMU_CFG_CLK_OUT(n) (((n) & 0xF) << 12)
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#define BT_CMU_CFG_CLK_OUT_MASK (0xF << 12)
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#define BT_CMU_CFG_CLK_OUT_SHIFT (12)
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#define BT_CMU_PWR_DELAY(n) (((n) & 0x7F) << 16)
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#define BT_CMU_PWR_DELAY_MASK (0x7F << 16)
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#define BT_CMU_PWR_DELAY_SHIFT (16)
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#define BT_CMU_ROM_PGEN(n) (((n) & 0xF) << 23)
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#define BT_CMU_ROM_PGEN_MASK (0xF << 23)
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#define BT_CMU_ROM_PGEN_SHIFT (23)
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#define BT_CMU_RAM_EMAS (1 << 27)
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#define BT_CMU_RF_EMAS (1 << 28)
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#endif
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