116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __HAL_DMACFG_BEST2300P_H__
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#define __HAL_DMACFG_BEST2300P_H__
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#define AUDMA_PERIPH_NUM 16
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#define GPDMA_PERIPH_NUM 16
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#define AUDMA_CHAN_NUM 8
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#define GPDMA_CHAN_NUM 8
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#define AUDMA_CHAN_START (0)
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#define GPDMA_CHAN_START (0)
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static const uint32_t audma_fifo_addr[AUDMA_PERIPH_NUM] = {
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CODEC_BASE + 0x01C, // CODEC RX
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CODEC_BASE + 0x01C, // CODEC TX
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#ifdef CODEC_DSD
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CODEC_BASE + 0x034, // DSD RX
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CODEC_BASE + 0x034, // DSD TX
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#else
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BTPCM_BASE + 0x1C0, // BTPCM RX
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BTPCM_BASE + 0x1C8, // BTPCM TX
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#endif
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I2S0_BASE + 0x200, // I2S0 RX
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I2S0_BASE + 0x240, // I2S0 TX
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0, // FIR RX
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0, // FIR TX
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SPDIF0_BASE + 0x1C0, // SPDIF0 RX
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SPDIF0_BASE + 0x1C8, // SPDIF0 TX
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CODEC_BASE + 0x03C, // IIR RX
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CODEC_BASE + 0x03C, // IIR TX
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BTDUMP_BASE + 0x34, // BTDUMP
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CODEC_BASE + 0x038, // MC RX
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I2S1_BASE + 0x200, // I2S1 RX
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I2S1_BASE + 0x240, // I2S1 TX
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};
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static const enum HAL_DMA_PERIPH_T audma_fifo_periph[AUDMA_PERIPH_NUM] = {
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HAL_AUDMA_CODEC_RX,
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HAL_AUDMA_CODEC_TX,
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#ifdef CODEC_DSD
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HAL_AUDMA_DSD_RX,
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HAL_AUDMA_DSD_TX,
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#else
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HAL_AUDMA_BTPCM_RX,
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HAL_AUDMA_BTPCM_TX,
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#endif
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HAL_AUDMA_I2S0_RX,
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HAL_AUDMA_I2S0_TX,
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HAL_AUDMA_FIR_RX,
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HAL_AUDMA_FIR_TX,
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HAL_AUDMA_SPDIF0_RX,
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HAL_AUDMA_SPDIF0_TX,
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HAL_AUDMA_IIR_RX,
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HAL_AUDMA_IIR_TX,
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HAL_AUDMA_BTDUMP,
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HAL_AUDMA_MC_RX,
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HAL_AUDMA_I2S1_RX,
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HAL_AUDMA_I2S1_TX,
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};
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static const uint32_t gpdma_fifo_addr[GPDMA_PERIPH_NUM] = {
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FLASH_CTRL_BASE + 0x008, // FLASH CTRL
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SDMMC_BASE + 0x200, // SDMMC
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I2C0_BASE + 0x010, // I2C0 RX
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I2C0_BASE + 0x010, // I2C0 TX
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SPI_BASE + 0x008, // SPI RX
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SPI_BASE + 0x008, // SPI TX
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SPILCD_BASE + 0x008, // SPILCD RX
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SPILCD_BASE + 0x008, // SPILCD TX
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UART0_BASE + 0x000, // UART0 RX
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UART0_BASE + 0x000, // UART0 TX
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UART1_BASE + 0x000, // UART1 RX
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UART1_BASE + 0x000, // UART1 TX
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I2C1_BASE + 0x010, // I2C1 RX
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I2C1_BASE + 0x010, // I2C1 TX
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UART2_BASE + 0x000, // UART2 RX
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UART2_BASE + 0x000, // UART2 TX
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};
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static const enum HAL_DMA_PERIPH_T gpdma_fifo_periph[GPDMA_PERIPH_NUM] = {
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HAL_GPDMA_FLASH_TX,
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HAL_GPDMA_SDMMC,
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HAL_GPDMA_I2C0_RX,
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HAL_GPDMA_I2C0_TX,
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HAL_GPDMA_SPI_RX,
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HAL_GPDMA_SPI_TX,
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HAL_GPDMA_SPILCD_RX,
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HAL_GPDMA_SPILCD_TX,
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HAL_GPDMA_UART0_RX,
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HAL_GPDMA_UART0_TX,
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HAL_GPDMA_UART1_RX,
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HAL_GPDMA_UART1_TX,
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HAL_GPDMA_I2C1_RX,
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HAL_GPDMA_I2C1_TX,
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HAL_GPDMA_UART2_RX,
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HAL_GPDMA_UART2_TX,
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};
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#endif
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