187 lines
8.1 KiB
C
187 lines
8.1 KiB
C
/**************************************************************************//**
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* @file irq_ctrl.h
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* @brief Interrupt Controller API header file
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* @version V1.0.0
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* @date 23. June 2017
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******************************************************************************/
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/*
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* Copyright (c) 2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__clang__)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef IRQ_CTRL_H_
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#define IRQ_CTRL_H_
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#include <stdint.h>
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#ifndef IRQHANDLER_T
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#define IRQHANDLER_T
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/// Interrupt handler data type
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typedef void (*IRQHandler_t) (void);
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#endif
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#ifndef IRQN_ID_T
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#define IRQN_ID_T
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/// Interrupt ID number data type
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typedef int32_t IRQn_ID_t;
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#endif
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/* Interrupt mode bit-masks */
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#define IRQ_MODE_TRIG_Pos (0U)
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#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
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#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
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#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
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#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
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#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
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#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
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#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
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#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
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#define IRQ_MODE_TYPE_Pos (3U)
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#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
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#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
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#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
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#define IRQ_MODE_DOMAIN_Pos (4U)
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#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
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#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
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#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
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#define IRQ_MODE_CPU_Pos (5U)
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#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
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#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
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#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
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#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
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#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
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#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
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#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
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#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
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#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
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#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
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#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
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/* Interrupt priority bit-masks */
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#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
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#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
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/// Initialize interrupt controller.
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/// \return 0 on success, -1 on error.
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int32_t IRQ_Initialize (void);
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/// Register interrupt handler.
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/// \param[in] irqn interrupt ID number
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/// \param[in] handler interrupt handler function address
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/// \return 0 on success, -1 on error.
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int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
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/// Get the registered interrupt handler.
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/// \param[in] irqn interrupt ID number
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/// \return registered interrupt handler function address.
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IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
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/// Enable interrupt.
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/// \param[in] irqn interrupt ID number
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/// \return 0 on success, -1 on error.
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int32_t IRQ_Enable (IRQn_ID_t irqn);
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/// Disable interrupt.
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/// \param[in] irqn interrupt ID number
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/// \return 0 on success, -1 on error.
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int32_t IRQ_Disable (IRQn_ID_t irqn);
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/// Get interrupt enable state.
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/// \param[in] irqn interrupt ID number
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/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
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uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
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/// Configure interrupt request mode.
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/// \param[in] irqn interrupt ID number
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/// \param[in] mode mode configuration
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/// \return 0 on success, -1 on error.
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int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
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/// Get interrupt mode configuration.
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/// \param[in] irqn interrupt ID number
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/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
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uint32_t IRQ_GetMode (IRQn_ID_t irqn);
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/// Get ID number of current interrupt request (IRQ).
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/// \return interrupt ID number.
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IRQn_ID_t IRQ_GetActiveIRQ (void);
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/// Get ID number of current fast interrupt request (FIQ).
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/// \return interrupt ID number.
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IRQn_ID_t IRQ_GetActiveFIQ (void);
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/// Signal end of interrupt processing.
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/// \param[in] irqn interrupt ID number
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/// \return 0 on success, -1 on error.
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int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
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/// Set interrupt pending flag.
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/// \param[in] irqn interrupt ID number
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/// \return 0 on success, -1 on error.
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int32_t IRQ_SetPending (IRQn_ID_t irqn);
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/// Get interrupt pending flag.
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/// \param[in] irqn interrupt ID number
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/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
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uint32_t IRQ_GetPending (IRQn_ID_t irqn);
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/// Clear interrupt pending flag.
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/// \param[in] irqn interrupt ID number
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/// \return 0 on success, -1 on error.
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int32_t IRQ_ClearPending (IRQn_ID_t irqn);
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/// Set interrupt priority value.
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/// \param[in] irqn interrupt ID number
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/// \param[in] priority interrupt priority value
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/// \return 0 on success, -1 on error.
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int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
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/// Get interrupt priority.
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/// \param[in] irqn interrupt ID number
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/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
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uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
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/// Set priority masking threshold.
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/// \param[in] priority priority masking threshold value
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/// \return 0 on success, -1 on error.
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int32_t IRQ_SetPriorityMask (uint32_t priority);
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/// Get priority masking threshold
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/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
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uint32_t IRQ_GetPriorityMask (void);
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/// Set priority grouping field split point
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/// \param[in] bits number of MSB bits included in the group priority field comparison
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/// \return 0 on success, -1 on error.
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int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
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/// Get priority grouping field split point
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/// \return current number of MSB bits included in the group priority field comparison with
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/// optional IRQ_PRIORITY_ERROR bit set.
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uint32_t IRQ_GetPriorityGroupBits (void);
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#endif // IRQ_CTRL_H_
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