137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/******************************************************************************
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* @file system_ARMCA7.c
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* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
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* @version V1.0.1
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* @date 13. February 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "cmsis_nvic.h"
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#include "ca/system_ARMCA.h"
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#include "ca/irq_ctrl.h"
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#include "hal_location.h"
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#include "hal_cmu.h"
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extern uint32_t __sram_text_data_start_load__[];
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extern uint32_t __sram_text_data_end_load__[];
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extern uint32_t __sram_text_data_start__[];
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extern uint32_t __sram_bss_start__[];
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extern uint32_t __sram_bss_end__[];
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extern uint32_t __bss_start__[];
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extern uint32_t __bss_end__[];
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extern uint32_t __sync_flags_start[];
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extern uint32_t __sync_flags_end[];
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extern uint32_t __psramuhs_text_data_start_load__[];
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extern uint32_t __psramuhs_text_data_end_load__[];
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extern uint32_t __psramuhs_text_start[];
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/*----------------------------------------------------------------------------
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System Initialization
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*----------------------------------------------------------------------------*/
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void SystemInit (void)
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{
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uint32_t *dst, *src;
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if (__sram_text_data_start__ != __sram_text_data_start_load__) {
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for (dst = __sram_text_data_start__, src = __sram_text_data_start_load__;
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src < __sram_text_data_end_load__;
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dst++, src++) {
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*dst = *src;
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}
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}
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hal_cmu_dsp_setup();
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/*psramhus_test load region covers sram_bss, and it needs to be copyed first*/
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#if defined(CHIP_HAS_PSRAMUHS) && defined(PSRAMUHS_ENABLE)
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for (dst = __psramuhs_text_start, src = __psramuhs_text_data_start_load__;
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src < __psramuhs_text_data_end_load__;
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dst++, src++) {
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*dst = *src;
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}
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#endif
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for (dst = __sram_bss_start__; dst < __sram_bss_end__; dst++) {
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*dst = 0;
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}
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#ifdef NOSTD
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for (dst = __bss_start__; dst < __bss_end__; dst++) {
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*dst = 0;
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}
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#endif
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for (dst = __sync_flags_start; dst < __sync_flags_end; dst++) {
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*dst = 0;
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}
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/* do not use global variables because this function is called before
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reaching pre-main. RW section may be overwritten afterwards. */
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// Init exception vectors
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GIC_InitVectors();
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// Invalidate entire Unified TLB
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__set_TLBIALL(0);
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// Invalidate entire branch predictor array
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__set_BPIALL(0);
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__DSB();
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__ISB();
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// Invalidate instruction cache and flush branch target cache
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__set_ICIALLU(0);
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__DSB();
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__ISB();
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// Invalidate data cache
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L1C_InvalidateDCacheAll();
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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// Enable FPU
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__FPU_Enable();
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#endif
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// Create Translation Table
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MMU_CreateTranslationTable();
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// Enable MMU
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MMU_Enable();
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// Enable Caches
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L1C_EnableCaches();
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L1C_EnableBTAC();
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#if (__L2C_PRESENT == 1)
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// Enable GIC
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L2C_Enable();
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#endif
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// IRQ Initialize
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IRQ_Initialize();
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}
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uint32_t BOOT_TEXT_SRAM_DEF(get_cpu_id) (void)
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{
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return __get_MPIDR() & 3;
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}
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