584 lines
19 KiB
C
584 lines
19 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_types.h"
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#include "norflash_drv.h"
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#include "hal_norflaship.h"
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#include "hal_timer.h"
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#include "hal_trace.h"
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#include "norflash_cfg.h"
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#include "norflash_gd25lq32c.h"
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static void gd25lq32c_write_status_s0_s15(uint16_t status, uint8_t len)
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{
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norflash_write_reg(GD25LQ32C_CMD_WRITE_STATUS, (uint8_t *)&status, len);
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}
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static int gd25lq32c_write_status(enum DRV_NORFLASH_W_STATUS_T type, uint32_t param)
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{
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uint8_t status_s0_s7;
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uint8_t status_s8_s15;
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uint32_t bp_mask = 0;
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union DRV_NORFLASH_SEC_REG_CFG_T cfg;
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bool has_quad;
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if (type != DRV_NORFLASH_W_STATUS_INIT && type != DRV_NORFLASH_W_STATUS_QE &&
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type != DRV_NORFLASH_W_STATUS_LB && type != DRV_NORFLASH_W_STATUS_BP) {
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return 1;
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}
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has_quad = !!(norflash_get_supported_mode() &
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(HAL_NORFLASH_OP_MODE_QUAD_OUTPUT | HAL_NORFLASH_OP_MODE_QUAD_IO));
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if (type == DRV_NORFLASH_W_STATUS_INIT) {
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gd25lq32c_write_status_s0_s15(param, (has_quad ? 2 : 1));
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return 0;
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}
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status_s0_s7 = norflash_read_status_s0_s7();
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if (type == DRV_NORFLASH_W_STATUS_BP) {
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bp_mask = norflash_get_block_protect_mask();
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status_s0_s7 = (status_s0_s7 & ~bp_mask) | (param & bp_mask);
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}
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if (has_quad) {
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status_s8_s15 = norflash_read_status_s8_s15();
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if (type == DRV_NORFLASH_W_STATUS_QE) {
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if (param) {
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status_s8_s15 |= GD25LQ32C_QE_BIT_MASK;
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} else {
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status_s8_s15 &= ~(GD25LQ32C_QE_BIT_MASK);
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}
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} else if (type == DRV_NORFLASH_W_STATUS_BP) {
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param >>= 8;
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bp_mask >>= 8;
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status_s8_s15 = (status_s8_s15 & ~bp_mask) | (param & bp_mask);
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} else if (type == DRV_NORFLASH_W_STATUS_LB) {
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cfg = norflash_get_security_register_config();
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if (!cfg.s.enabled) {
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return 2;
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}
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if (cfg.s.lb == SEC_REG_LB_S11_S13) {
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if (param >= 3) {
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return 3;
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}
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status_s8_s15 |= (STATUS_S11_LB1_BIT_MASK << param);
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} else if (cfg.s.lb == SEC_REG_LB_S10) {
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status_s8_s15 |= STATUS_S10_LB_BIT_MASK;
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} else {
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return 4;
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}
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}
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gd25lq32c_write_status_s0_s15(status_s0_s7 | (status_s8_s15 << 8), 2);
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} else {
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gd25lq32c_write_status_s0_s15(status_s0_s7, 1);
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}
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return 0;
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}
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// ----------------------
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// GigaDevice
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// ----------------------
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const struct NORFLASH_CFG_T gd25lq64c_cfg = {
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.id = { 0xC8, 0x60, 0x17, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_6_EIGHTH,
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.others = SPEED_RATIO_8_EIGHTH,
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},
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},
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.crm_en_bits = (1 << 5) | (0 << 4),
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.crm_dis_bits = 0,
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.block_protect_mask = 0x407C,
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.sec_reg_cfg = {
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.s = {
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.enabled = true,
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.base = SEC_REG_BASE_0X1000,
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.size = SEC_REG_SIZE_1024,
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.offset = SEC_REG_OFFSET_0X1000,
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.cnt = SEC_REG_CNT_3,
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.pp = SEC_REG_PP_256,
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.lb = SEC_REG_LB_S11_S13,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = GD25LQ64C_TOTAL_SIZE,
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.max_speed = 104 * 1000 * 1000,
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_DUAL_IO |
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HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
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HAL_NORFLASH_OP_MODE_QUAD_IO |
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HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
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HAL_NORFLASH_OP_MODE_READ_WRAP |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_SUSPEND),
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.write_status = gd25lq32c_write_status,
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};
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const struct NORFLASH_CFG_T gd25lq32c_cfg = {
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.id = { 0xC8, 0x60, 0x16, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_5_EIGHTH,
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.others = SPEED_RATIO_8_EIGHTH,
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},
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},
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.crm_en_bits = (1 << 5) | (0 << 4),
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.crm_dis_bits = 0,
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.block_protect_mask = 0x407C,
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.sec_reg_cfg = {
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.s = {
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.enabled = true,
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.base = SEC_REG_BASE_0X1000,
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.size = SEC_REG_SIZE_1024,
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.offset = SEC_REG_OFFSET_0X1000,
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.cnt = SEC_REG_CNT_3,
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.pp = SEC_REG_PP_256,
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.lb = SEC_REG_LB_S11_S13,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = GD25LQ32C_TOTAL_SIZE,
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.max_speed = 120 * 1000 * 1000,
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_DUAL_IO |
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HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
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HAL_NORFLASH_OP_MODE_QUAD_IO |
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HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
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HAL_NORFLASH_OP_MODE_READ_WRAP |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_SUSPEND),
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.write_status = gd25lq32c_write_status,
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};
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const struct NORFLASH_CFG_T gd25lq16c_cfg = {
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.id = { 0xC8, 0x60, 0x15, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_6_EIGHTH,
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.others = SPEED_RATIO_8_EIGHTH,
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},
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},
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.crm_en_bits = (1 << 5) | (0 << 4),
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.crm_dis_bits = 0,
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.block_protect_mask = 0x407C,
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.sec_reg_cfg = {
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.s = {
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.enabled = true,
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.base = SEC_REG_BASE_0X1000,
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.size = SEC_REG_SIZE_512,
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.offset = SEC_REG_OFFSET_0X1000,
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.cnt = SEC_REG_CNT_3,
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.pp = SEC_REG_PP_256,
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.lb = SEC_REG_LB_S11_S13,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = GD25LQ16C_TOTAL_SIZE,
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.max_speed = 104 * 1000 * 1000,
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_DUAL_IO |
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HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
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HAL_NORFLASH_OP_MODE_QUAD_IO |
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HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
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HAL_NORFLASH_OP_MODE_READ_WRAP |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_SUSPEND),
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.write_status = gd25lq32c_write_status,
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};
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const struct NORFLASH_CFG_T gd25lq80c_cfg = {
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.id = { 0xC8, 0x60, 0x14, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_6_EIGHTH,
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.others = SPEED_RATIO_6_EIGHTH,
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},
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},
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.crm_en_bits = (1 << 5) | (0 << 4),
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.crm_dis_bits = 0,
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.block_protect_mask = 0x407C,
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.sec_reg_cfg = {
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.s = {
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.enabled = true,
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.base = SEC_REG_BASE_0X1000,
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.size = SEC_REG_SIZE_512,
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.offset = SEC_REG_OFFSET_0X1000,
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.cnt = SEC_REG_CNT_3,
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.pp = SEC_REG_PP_256,
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.lb = SEC_REG_LB_S11_S13,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = GD25LQ80C_TOTAL_SIZE,
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.max_speed = 104 * 1000 * 1000,
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_DUAL_IO |
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HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
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HAL_NORFLASH_OP_MODE_QUAD_IO |
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HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
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HAL_NORFLASH_OP_MODE_READ_WRAP |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_SUSPEND),
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.write_status = gd25lq32c_write_status,
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};
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const struct NORFLASH_CFG_T gd25q80c_cfg = {
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.id = { 0xC8, 0x40, 0x14, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_5_EIGHTH,
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.others = SPEED_RATIO_5_EIGHTH,
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},
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},
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.crm_en_bits = 0xA0,
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.crm_dis_bits = 0,
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.block_protect_mask = 0x407C,
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.sec_reg_cfg = {
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.s = {
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.enabled = true,
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.base = SEC_REG_BASE_0X0000,
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.size = SEC_REG_SIZE_256,
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.offset = SEC_REG_OFFSET_0X0100,
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.cnt = SEC_REG_CNT_4,
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.pp = SEC_REG_PP_256,
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.lb = SEC_REG_LB_S10,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = GD25Q80C_TOTAL_SIZE,
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#ifdef FLASH_HPM
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.max_speed = 120 * 1000 * 1000,
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#else
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.max_speed = 104 * 1000 * 1000,
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#endif
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_DUAL_IO |
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HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
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HAL_NORFLASH_OP_MODE_QUAD_IO |
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#ifdef FLASH_HPM
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HAL_NORFLASH_OP_MODE_HIGH_PERFORMANCE |
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#endif
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HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
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HAL_NORFLASH_OP_MODE_READ_WRAP |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_SUSPEND),
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.write_status = gd25lq32c_write_status,
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};
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const struct NORFLASH_CFG_T gd25d40c_cfg = {
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.id = { 0xC8, 0x40, 0x13, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_6_EIGHTH,
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.others = SPEED_RATIO_6_EIGHTH,
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},
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},
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.crm_en_bits = 0,
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.crm_dis_bits = 0,
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.block_protect_mask = 0x1C,
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.sec_reg_cfg = {
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.s = {
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.enabled = false,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = GD25D40C_TOTAL_SIZE,
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.max_speed = 80 * 1000 * 1000,
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM),
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.write_status = gd25lq32c_write_status,
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};
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const struct NORFLASH_CFG_T gd25d20c_cfg = {
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.id = { 0xC8, 0x40, 0x12, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_6_EIGHTH,
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.others = SPEED_RATIO_6_EIGHTH,
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},
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},
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.crm_en_bits = 0,
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.crm_dis_bits = 0,
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.block_protect_mask = 0x1C,
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.sec_reg_cfg = {
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.s = {
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.enabled = false,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = GD25D20C_TOTAL_SIZE,
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.max_speed = 80 * 1000 * 1000,
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM),
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.write_status = gd25lq32c_write_status,
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};
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// ----------------------
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// Puya
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// ----------------------
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const struct NORFLASH_CFG_T p25q16l_cfg = {
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.id = { 0x85, 0x60, 0x15, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_3_EIGHTH,
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.others = SPEED_RATIO_8_EIGHTH,
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},
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},
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.crm_en_bits = (1 << 5) | (0 << 4),
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.crm_dis_bits = 0,
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.block_protect_mask = 0x407C,
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.sec_reg_cfg = {
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.s = {
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.enabled = true,
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.base = SEC_REG_BASE_0X1000,
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.size = SEC_REG_SIZE_512,
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.offset = SEC_REG_OFFSET_0X1000,
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.cnt = SEC_REG_CNT_3,
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.pp = SEC_REG_PP_256,
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.lb = SEC_REG_LB_S11_S13,
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},
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},
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.page_size = GD25LQ32C_PAGE_SIZE,
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.sector_size = GD25LQ32C_SECTOR_SIZE,
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.block_size = GD25LQ32C_BLOCK_SIZE,
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.total_size = P25Q16L_TOTAL_SIZE,
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.max_speed = 70 * 1000 * 1000, // P25Q80L=70M, P25Q80H=104M, P25Q80U=70M/104M
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_DUAL_IO |
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HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
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HAL_NORFLASH_OP_MODE_QUAD_IO |
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HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
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HAL_NORFLASH_OP_MODE_READ_WRAP |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_DUAL_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_SUSPEND),
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.write_status = gd25lq32c_write_status,
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};
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const struct NORFLASH_CFG_T p25q80h_cfg = {
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.id = { 0x85, 0x60, 0x14, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_3_EIGHTH,
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.others = SPEED_RATIO_8_EIGHTH,
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},
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},
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.crm_en_bits = (1 << 5) | (0 << 4),
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.crm_dis_bits = 0,
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.block_protect_mask = 0x407C,
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.sec_reg_cfg = {
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.s = {
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.enabled = true,
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.base = SEC_REG_BASE_0X1000,
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.size = SEC_REG_SIZE_512,
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.offset = SEC_REG_OFFSET_0X1000,
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.cnt = SEC_REG_CNT_3,
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.pp = SEC_REG_PP_256,
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.lb = SEC_REG_LB_S11_S13,
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},
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},
|
|
.page_size = GD25LQ32C_PAGE_SIZE,
|
|
.sector_size = GD25LQ32C_SECTOR_SIZE,
|
|
.block_size = GD25LQ32C_BLOCK_SIZE,
|
|
.total_size = P25Q80H_TOTAL_SIZE,
|
|
.max_speed = 70 * 1000 * 1000, // P25Q80L=70M, P25Q80H=104M, P25Q80U=70M/104M
|
|
.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
|
|
HAL_NORFLASH_OP_MODE_FAST_SPI |
|
|
HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_DUAL_IO |
|
|
HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_QUAD_IO |
|
|
HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
|
|
HAL_NORFLASH_OP_MODE_READ_WRAP |
|
|
HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_DUAL_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_SUSPEND),
|
|
.write_status = gd25lq32c_write_status,
|
|
};
|
|
|
|
const struct NORFLASH_CFG_T p25q40h_cfg = {
|
|
.id = { 0x85, 0x60, 0x13, },
|
|
.speed_ratio = {
|
|
.s = {
|
|
.std_read = SPEED_RATIO_3_EIGHTH,
|
|
.others = SPEED_RATIO_8_EIGHTH,
|
|
},
|
|
},
|
|
.crm_en_bits = (1 << 5) | (0 << 4),
|
|
.crm_dis_bits = 0,
|
|
.block_protect_mask = 0x407C,
|
|
.sec_reg_cfg = {
|
|
.s = {
|
|
.enabled = true,
|
|
.base = SEC_REG_BASE_0X1000,
|
|
.size = SEC_REG_SIZE_512,
|
|
.offset = SEC_REG_OFFSET_0X1000,
|
|
.cnt = SEC_REG_CNT_3,
|
|
.pp = SEC_REG_PP_256,
|
|
.lb = SEC_REG_LB_S11_S13,
|
|
},
|
|
},
|
|
.page_size = GD25LQ32C_PAGE_SIZE,
|
|
.sector_size = GD25LQ32C_SECTOR_SIZE,
|
|
.block_size = GD25LQ32C_BLOCK_SIZE,
|
|
.total_size = P25Q40H_TOTAL_SIZE,
|
|
.max_speed = 70 * 1000 * 1000, // P25Q21L=70M, P25Q21H=104M, P25Q21U=70M/104M
|
|
.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
|
|
HAL_NORFLASH_OP_MODE_FAST_SPI |
|
|
HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_DUAL_IO |
|
|
HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_QUAD_IO |
|
|
HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
|
|
HAL_NORFLASH_OP_MODE_READ_WRAP |
|
|
HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_DUAL_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_SUSPEND),
|
|
.write_status = gd25lq32c_write_status,
|
|
};
|
|
|
|
|
|
const struct NORFLASH_CFG_T p25q21h_cfg = {
|
|
.id = { 0x85, 0x40, 0x12, },
|
|
.speed_ratio = {
|
|
.s = {
|
|
.std_read = SPEED_RATIO_3_EIGHTH,
|
|
.others = SPEED_RATIO_8_EIGHTH,
|
|
},
|
|
},
|
|
.crm_en_bits = (1 << 5) | (0 << 4),
|
|
.crm_dis_bits = 0,
|
|
.block_protect_mask = 0x407C,
|
|
.sec_reg_cfg = {
|
|
.s = {
|
|
.enabled = true,
|
|
.base = SEC_REG_BASE_0X1000,
|
|
.size = SEC_REG_SIZE_512,
|
|
.offset = SEC_REG_OFFSET_0X1000,
|
|
.cnt = SEC_REG_CNT_3,
|
|
.pp = SEC_REG_PP_256,
|
|
.lb = SEC_REG_LB_S11_S13,
|
|
},
|
|
},
|
|
.page_size = GD25LQ32C_PAGE_SIZE,
|
|
.sector_size = GD25LQ32C_SECTOR_SIZE,
|
|
.block_size = GD25LQ32C_BLOCK_SIZE,
|
|
.total_size = P25Q21H_TOTAL_SIZE,
|
|
.max_speed = 70 * 1000 * 1000, // P25Q21L=70M, P25Q21H=104M, P25Q21U=70M/104M
|
|
.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
|
|
HAL_NORFLASH_OP_MODE_FAST_SPI |
|
|
HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_DUAL_IO |
|
|
HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_QUAD_IO |
|
|
HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
|
|
HAL_NORFLASH_OP_MODE_READ_WRAP |
|
|
HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_DUAL_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_SUSPEND),
|
|
.write_status = gd25lq32c_write_status,
|
|
};
|
|
|
|
// ----------------------
|
|
// XTS
|
|
// ----------------------
|
|
|
|
const struct NORFLASH_CFG_T xt25q08b_cfg = {
|
|
.id = { 0x0B, 0x60, 0x14, },
|
|
.speed_ratio = {
|
|
.s = {
|
|
.std_read = SPEED_RATIO_7_EIGHTH,
|
|
.others = SPEED_RATIO_7_EIGHTH,
|
|
},
|
|
},
|
|
.crm_en_bits = (1 << 5) | (0 << 4),
|
|
.crm_dis_bits = 0,
|
|
.block_protect_mask = 0x403C,
|
|
.sec_reg_cfg = {
|
|
.s = {
|
|
.enabled = true,
|
|
.base = SEC_REG_BASE_0X0000,
|
|
.size = SEC_REG_SIZE_256,
|
|
.offset = SEC_REG_OFFSET_0X0100,
|
|
.cnt = SEC_REG_CNT_4,
|
|
.pp = SEC_REG_PP_256,
|
|
.lb = SEC_REG_LB_S10,
|
|
},
|
|
},
|
|
.page_size = GD25LQ32C_PAGE_SIZE,
|
|
.sector_size = GD25LQ32C_SECTOR_SIZE,
|
|
.block_size = GD25LQ32C_BLOCK_SIZE,
|
|
.total_size = XT25Q08B_TOTAL_SIZE,
|
|
.max_speed = 96 * 1000 * 1000,
|
|
.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
|
|
HAL_NORFLASH_OP_MODE_FAST_SPI |
|
|
HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_DUAL_IO |
|
|
HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
|
|
HAL_NORFLASH_OP_MODE_QUAD_IO |
|
|
HAL_NORFLASH_OP_MODE_CONTINUOUS_READ |
|
|
HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
|
|
HAL_NORFLASH_OP_MODE_SUSPEND),
|
|
.write_status = gd25lq32c_write_status,
|
|
};
|
|
|