144 lines
3.7 KiB
C
144 lines
3.7 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_types.h"
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#include "norflash_drv.h"
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#include "hal_norflaship.h"
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#include "norflash_en25s80b.h"
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#include "hal_trace.h"
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#include "hal_timer.h"
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static void POSSIBLY_UNUSED en25s80b_en25s80b_reset(void)
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{
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// ip quad mode
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norflaship_quad_mode(1);
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norflaship_busy_wait();
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hal_sys_timer_delay(20);
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// quad reset enable
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norflaship_clear_txfifo();
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norflaship_cmd_addr(EN25S80B_CMD_QUAD_RESET_ENABLE, 0);
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norflaship_busy_wait();
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hal_sys_timer_delay(20);
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// quad reset
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norflaship_clear_txfifo();
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norflaship_cmd_addr(EN25S80B_CMD_QUAD_RESET, 0);
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norflaship_busy_wait();
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hal_sys_timer_delay(20);
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// ip spi mode
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norflaship_quad_mode(0);
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norflaship_hold_pin(0);
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norflaship_wpr_pin(0);
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norflaship_busy_wait();
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hal_sys_timer_delay(20);
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// reset enable
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norflaship_clear_txfifo();
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norflaship_cmd_addr(EN25S80B_CMD_SPI_RESET_ENABLE, 0);
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norflaship_busy_wait();
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hal_sys_timer_delay(20);
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// reset
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norflaship_clear_txfifo();
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norflaship_cmd_addr(EN25S80B_CMD_SPI_RESET, 0);
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norflaship_busy_wait();
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hal_sys_timer_delay(20);
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}
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static void en25s80b_enter_OTP(void)
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{
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norflaship_clear_txfifo();
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norflaship_cmd_addr(EN25S80B_CMD_ENTER_OTP, 0);
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norflash_status_WIP_1_wait(0);
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}
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static void en25s80b_exit_OTP(void)
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{
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norflaship_clear_txfifo();
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norflaship_cmd_addr(EN25S80B_CMD_EXIT_OTP, 0);
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norflash_status_WIP_1_wait(0);
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}
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static void en25s80b_write_status_s0_s7(uint8_t status)
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{
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norflash_write_reg(EN25S80B_CMD_WRITE_STATUS, &status, 1);
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}
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static int en25s80b_write_status(enum DRV_NORFLASH_W_STATUS_T type, uint32_t param)
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{
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uint8_t status;
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if (type == DRV_NORFLASH_W_STATUS_QE) {
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en25s80b_enter_OTP();
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status = norflash_read_status_s0_s7();
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if (param) {
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status |= (EN25S80B_WHDIS_BIT_MASK);
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} else {
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status &= ~(EN25S80B_WHDIS_BIT_MASK);
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}
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en25s80b_write_status_s0_s7(status);
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en25s80b_exit_OTP();
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return 0;
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}
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return 1;
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}
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const struct NORFLASH_CFG_T en25s80b_cfg = {
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.id = { 0x1C, 0x38, 0x14, },
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.speed_ratio = {
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.s = {
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.std_read = SPEED_RATIO_6_EIGHTH,
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.others = SPEED_RATIO_6_EIGHTH,
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},
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},
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.crm_en_bits = 0xA5,
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.crm_dis_bits = 0xAA,
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.sec_reg_cfg = {
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.s = {
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.enabled = false,
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},
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},
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.page_size = EN25S80B_PAGE_SIZE,
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.sector_size = EN25S80B_SECTOR_SIZE,
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.block_size = EN25S80B_BLOCK_SIZE,
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.total_size = EN25S80B_TOTAL_SIZE,
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.max_speed = 104 * 1000 * 1000,
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.mode = (HAL_NORFLASH_OP_MODE_STAND_SPI |
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HAL_NORFLASH_OP_MODE_FAST_SPI |
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HAL_NORFLASH_OP_MODE_DUAL_OUTPUT |
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HAL_NORFLASH_OP_MODE_DUAL_IO |
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HAL_NORFLASH_OP_MODE_QUAD_OUTPUT |
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HAL_NORFLASH_OP_MODE_QUAD_IO |
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HAL_NORFLASH_OP_MODE_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM |
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HAL_NORFLASH_OP_MODE_ERASE_IN_STD),
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.write_status = en25s80b_write_status,
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};
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