240 lines
6.1 KiB
C
240 lines
6.1 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_types.h"
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#include "codec_tlv32aic32.h"
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#include "hal_i2c.h"
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#include "hal_i2s.h"
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#include "hal_uart.h"
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#include "hal_trace.h"
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#include "string.h"
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#define TLV32AIC32_INST HAL_I2S_ID_0
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static struct HAL_I2C_CONFIG_T _codec_i2c_cfg;
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static uint8_t sample_rate_div[] = {
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10, /* index is 0 */
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15,
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20,
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25,
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30,
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35,
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40,
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45,
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50,
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55,
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60,
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};
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/* i2c write */
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static int codec_write(uint8_t reg_addr, uint8_t value)
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{
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uint8_t buf[2];
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buf[0] = reg_addr;
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buf[1] = value;
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return hal_i2c_task_send(HAL_I2C_ID_0, TLV32AIC32_I2C_ADDRESS, buf, 1 + 1, 0, 0);
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}
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/* i2c read */
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#if 0
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static uint8_t codec_read(uint8_t reg_addr)
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{
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uint8_t buf[2];
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buf[0] = reg_addr;
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buf[1] = 0;
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hal_i2c_task_recv(HAL_I2C_ID_0, TLV32AIC32_I2C_ADDRESS, &buf[0], 1, &buf[1], 1, 0, 0);
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return buf[1];
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}
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#endif
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uint32_t tlv32aic32_open(void)
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{
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_codec_i2c_cfg.mode = HAL_I2C_API_MODE_TASK;
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_codec_i2c_cfg.use_dma = 0;
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_codec_i2c_cfg.use_sync = 1;
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_codec_i2c_cfg.speed = 20000;
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_codec_i2c_cfg.as_master = 1;
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hal_i2c_open(HAL_I2C_ID_0, &_codec_i2c_cfg);
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return 0;
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}
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uint32_t tlv32aic32_stream_open(enum AUD_STREAM_T stream)
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{
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hal_i2s_open(TLV32AIC32_INST, stream, HAL_I2S_MODE_MASTER);
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return 0;
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}
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uint32_t tlv32aic32_stream_setup(enum AUD_STREAM_T stream, struct tlv32aic32_config_t *cfg)
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{
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uint32_t param = 0, i = 0;
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/* select page : 0*/
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codec_write(AIC3X_PAGE_SELECT, PAGE0_SELECT);
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/* soft reset : 1 */
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codec_write(AIC3X_RESET, SOFT_RESET);
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/* CLKDIV_IN uses mCLK : 102 , PLLDIV_IN use mCLK */
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codec_write(AIC3X_CLKGEN_CTRL_REG, 0x02);
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/* CODEC_CLK_IN uses CLKDIV : 101, CODEC_CLK_IN use CLKDIV_IN */
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codec_write(101, 0x00);
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/* PLL R value : 11, R is 1 */
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codec_write(AIC3X_OVRF_STATUS_AND_PLLR_REG, 0x1);
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/* PLL J value : 4, J is 8 */
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codec_write(AIC3X_PLL_PROGB_REG, 0x8);
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/* PLL D value : 5,6, D is 1920 */
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codec_write(AIC3X_PLL_PROGC_REG, 0x780>>6);
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codec_write(AIC3X_PLL_PROGD_REG, (0x780&0x3f)<<2);
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/* PLL disable and select Q value : 3, enable pll, Q is 2 */
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codec_write(AIC3X_PLL_PROGA_REG, 0x81);
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/* left and right DAC open : 7, open codec dac path and fref */
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if ((cfg->sample_rate%8000) == 0) {
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/* 48000 */
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codec_write(AIC3X_CODEC_DATAPATH_REG, 0x0a);
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param = 480000/cfg->sample_rate;
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}
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else {
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/* 44100 */
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codec_write(AIC3X_CODEC_DATAPATH_REG, 0x8a);
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param = 441000/cfg->sample_rate;
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}
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for (i = 0; i < sizeof(sample_rate_div); ++i) {
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if (param == sample_rate_div[i])
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break;
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}
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if (i == sizeof(sample_rate_div)) {
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i = 0;
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}
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/* sample_rate divider : 2, default is /1 */
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codec_write(AIC3X_SAMPLE_RATE_SEL_REG, i<<4|i<<4);
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/* ctrl mode : 8, bitclock input, word clock input */
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codec_write(AIC3X_ASD_INTF_CTRLA, 0x20);
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/* Audio Serial Data Interface Control : 9, 16bit i2s mode */
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if (cfg->bits == AUD_BITS_16)
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param = 0;
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else if (cfg->bits == AUD_BITS_20)
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param = 1;
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else if (cfg->bits == AUD_BITS_24)
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param = 2;
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else if (cfg->bits == AUD_BITS_32)
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param = 3;
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else
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param = 0;
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codec_write(AIC3X_ASD_INTF_CTRLB, 0x00 | param<<4);
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/* out ac-coupled : 14, headset control */
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codec_write(AIC3X_HEADSET_DETECT_CTRL_B, 0x08);
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/* left and right DAC power on : 37 */
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//codec_write(DAC_PWR, 0xC0);
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codec_write(DAC_PWR, 0xD0);
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/* out common-mode voltage : 40 */
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codec_write(HPOUT_SC, 0x00);
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/* out path select : 41 */
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codec_write(DAC_LINE_MUX, 0xA1);
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/* left DAC not muted : 43 */
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codec_write(LDAC_VOL, 0x0f);
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/* right DAC not muted : 44 */
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codec_write(RDAC_VOL, 0x0f);
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/* HPLOUT is not muted : 51 */
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codec_write(HPLOUT_CTRL, 0x9F);
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/* HPROUT is not muted : 65 */
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codec_write(HPROUT_CTRL, 0x9F);
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/* out short circuit protection : 38 */
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//codec_write(HPRCOM_CFG, 0x3A);
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codec_write(HPRCOM_CFG, 0x22);
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/* input */
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/* mic bias : 25 */
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codec_write(MICBIAS_CTRL, 0x40);
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/* left adc power : 19 */
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codec_write(LINE1L_2_LADC_CTRL, 0x04);
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/* right adc power : 22 */
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codec_write(LINE1R_2_RADC_CTRL, 0x04);
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/* left adc pga mute : 15 */
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codec_write(LADC_VOL, 0x0);
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/* right adc pga mute : 16 */
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codec_write(RADC_VOL, 0x0);
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/* adc flag : 36 */
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//TRACE(1,"tlv adc flag 0x%x", codec_read(ADC_FLAG));
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/* left adc pga mute : 15 */
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//TRACE(1,"tlv left adc pga 0x%x", codec_read(LADC_VOL));
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/* right adc pga mute : 16 */
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//TRACE(1,"tlv right adc pga 0x%x", codec_read(RADC_VOL));
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/* input end */
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struct HAL_I2S_CONFIG_T i2s_cfg;
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memset(&i2s_cfg, 0, sizeof(i2s_cfg));
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i2s_cfg.use_dma = cfg->use_dma;
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i2s_cfg.chan_sep_buf = cfg->chan_sep_buf;
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i2s_cfg.sync_start = cfg->sync_start;
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i2s_cfg.cycles = cfg->slot_cycles;
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i2s_cfg.bits = cfg->bits;
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i2s_cfg.channel_num = cfg->channel_num;
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i2s_cfg.channel_map = cfg->channel_map;
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i2s_cfg.sample_rate = cfg->sample_rate;
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hal_i2s_setup_stream(TLV32AIC32_INST, stream, &i2s_cfg);
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return 0;
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}
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uint32_t tlv32aic32_stream_start(enum AUD_STREAM_T stream)
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{
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hal_i2s_start_stream(TLV32AIC32_INST, stream);
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return 0;
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}
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uint32_t tlv32aic32_stream_stop(enum AUD_STREAM_T stream)
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{
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hal_i2s_stop_stream(TLV32AIC32_INST, stream);
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return 0;
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}
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uint32_t tlv32aic32_stream_close(enum AUD_STREAM_T stream)
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{
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hal_i2s_close(TLV32AIC32_INST, stream);
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return 0;
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}
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uint32_t tlv32aic32_close(void)
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{
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return 0;
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}
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