210 lines
14 KiB
C
210 lines
14 KiB
C
/******************************************************************************
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* @file ARMCA7.h
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* @brief CMSIS Cortex-A7 Core Peripheral Access Layer Header File
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* @version V1.1.0
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* @date 15. May 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __BEST2001_DSP_H__
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#define __BEST2001_DSP_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __ASSEMBLER__
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/* ------------------------- Interrupt Number Definition ------------------------ */
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/** Device specific Interrupt IDs */
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typedef enum IRQn
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{
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/****** SGI Interrupts Numbers ****************************************/
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SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */
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SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */
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SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */
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SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */
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SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */
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SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */
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SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */
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SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */
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SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */
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SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */
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SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */
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SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */
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SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */
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SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */
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SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */
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SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */
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/****** Cortex-A7 Processor Exceptions Numbers ****************************************/
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SecurePhyTimer_IRQn = 29, /*!< Physical Timer Interrupt */
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/****** Platform Exceptions Numbers ***************************************************/
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WAKEUP_IRQn = 32, /*!< Wakeup Interrupt */
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CODEC_IRQn = 33, /*!< CODEC Interrupt */
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CODEC_TX_PEAK_IRQn = 34, /*!< CODEC TX PEAK Interrupt */
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SDMMC_IRQn = 35, /*!< SDMMC Interrupt */
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BES2001_AUDMA_IRQn = 36, /*!< Audio DMA Interrupt */
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BES2001_GPDMA_IRQn = 37, /*!< General Purpose DMA Interrupt */
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USB_IRQn = 38, /*!< USB Interrupt */
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USB_PHY_IRQn = 39, /*!< USB PHY Interrupt */
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USB_CAL_IRQn = 40, /*!< USB Calibration Interrupt */
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USB_PIN_IRQn = 41, /*!< USB Pin Interrupt */
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SEC_ENG_IRQn = 42, /*!< Security Engine Interrupt */
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SEDMA_IRQn = 43, /*!< SEDMA Interrupt */
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DUMP_IRQn = 44, /*!< DUMP Interrupt */
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MCU_WDT_IRQn = 45, /*!< Watchdog Timer Interrupt */
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MCU_TIMER00_IRQn = 46, /*!< Timer00 Interrupt */
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MCU_TIMER01_IRQn = 47, /*!< Timer01 Interrupt */
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MCU_TIMER10_IRQn = 48, /*!< Timer10 Interrupt */
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MCU_TIMER11_IRQn = 49, /*!< Timer11 Interrupt */
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MCU_TIMER20_IRQn = 50, /*!< Timer20 Interrupt */
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MCU_TIMER21_IRQn = 51, /*!< Timer21 Interrupt */
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I2C0_IRQn = 52, /*!< I2C0 Interrupt */
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I2C1_IRQn = 53, /*!< I2C1 Interrupt */
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SPI0_IRQn = 54, /*!< SPI0 Interrupt */
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SPILCD_IRQn = 55, /*!< SPILCD Interrupt */
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ITNSPI_IRQn = 56, /*!< Internal SPI Interrupt */
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SPIPHY_IRQn = 57, /*!< SPIPHY Interrupt */
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UART0_IRQn = 58, /*!< UART0 Interrupt */
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UART1_IRQn = 59, /*!< UART1 Interrupt */
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UART2_IRQn = 60, /*!< UART2 Interrupt */
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BTPCM_IRQn = 61, /*!< BTPCM Interrupt */
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I2S0_IRQn = 62, /*!< I2S0 Interrupt */
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SPDIF0_IRQn = 63, /*!< SPDIF0 Interrupt */
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TRNG_IRQn = 64, /*!< TRNG Interrupt */
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AON_GPIO_IRQn = 65, /*!< AON GPIO Interrupt */
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AON_GPIOAUX_IRQn = 66, /*!< AON GPIOAUX Interrupt */
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AON_WDT_IRQn = 67, /*!< AON Watchdog Timer Interrupt */
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AON_TIMER00_IRQn = 68, /*!< AON Timer00 Interrupt */
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AON_TIMER01_IRQn = 69, /*!< AON Timer01 Interrupt */
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TRANSQW_LCL_IRQn = 70, /*!< TRANSQ-WIFI Local Interrupt */
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TRANSQW_RMT_IRQn = 71, /*!< TRANSQ-WIFI Peer Remote Interrupt */
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WIFI_IRQn = 72, /*!< DSP to MCU Interrupt */
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ISDONE_IRQn = 73, /*!< Intersys MCU2BT Data Done Interrupt */
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ISDONE1_IRQn = 74, /*!< Intersys MCU2BT Data1 Done Interrupt */
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ISDATA_IRQn = 75, /*!< Intersys BT2MCU Data Indication Interrupt */
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ISDATA1_IRQn = 76, /*!< Intersys BT2MCU Data1 Indication Interrupt */
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BT_IRQn = 77, /*!< BT to MCU Interrupt */
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RESERVED58_IRQn = 78, /*!< Reserved Interrupt */
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RTC_IRQn = 79, /*!< RTC Interrupt */
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GPADC_IRQn = 80, /*!< GPADC Interrupt */
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CHARGER_IRQn = 81, /*!< Charger Interrupt */
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PWRKEY_IRQn = 82, /*!< Power key Interrupt */
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WIFIDUMP_IRQn = 83, /*!< WIFIDUMP Interrupt */
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CHKSUM_IRQn = 84, /*!< Checksum Interrupt */
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CRC_IRQn = 85, /*!< CRC Interrupt */
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AON_SPIDPD_IRQn = 86, /*!< AON SPIDPD Interrupt */
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TRUSTZONE_IRQn = 87, /*!< TrustZone Interrupt */
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TRANSQM_LCL_IRQn = 88, /*!< TRANSQ-MCU Local Interrupt */
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TRANSQM_RMT_IRQn = 89, /*!< TRANSQ-MCU Peer Remote Interrupt */
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MCU_IRQn = 90, /*!< MCU to DSP Interrupt */
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DSP_WDT_IRQn = 91, /*!< Watchdog Timer Interrupt */
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DSP_TIMER00_IRQn = 92, /*!< Timer00 Interrupt */
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DSP_TIMER01_IRQn = 93, /*!< Timer01 Interrupt */
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DSP_TIMER10_IRQn = 94, /*!< Timer10 Interrupt */
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DSP_TIMER11_IRQn = DSP_TIMER10_IRQn, /*!< Timer11 Interrupt */
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XDMA_IRQn = 95, /*!< DSP XDMA Interrupt */
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USER_IRQn_QTY,
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INVALID_IRQn = USER_IRQn_QTY,
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} IRQn_Type;
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#define AUDMA_IRQn BES2001_AUDMA_IRQn //A7 use AUDMA
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#define GPIO_IRQn AON_GPIO_IRQn
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#define GPIOAUX_IRQn AON_GPIOAUX_IRQn
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#define TIMER00_IRQn DSP_TIMER00_IRQn
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#define TIMER01_IRQn DSP_TIMER01_IRQn
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#define WDT_IRQn AON_WDT_IRQn
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#define TRANSQ0_RMT_IRQn TRANSQW_RMT_IRQn//use MCU's transq
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#define TRANSQ0_LCL_IRQn TRANSQW_LCL_IRQn
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#define TRANSQ1_RMT_IRQn TRANSQM_RMT_IRQn
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#define TRANSQ1_LCL_IRQn TRANSQM_LCL_IRQn
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#endif
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#if 0
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/* Peripheral and RAM base address */
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#define VE_A7_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
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#define VE_A7_MP_FLASH_BASE1 (0x0C000000UL) /*!< (FLASH1 ) Base Address */
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#define VE_A7_MP_SRAM_BASE (0x14000000UL) /*!< (SRAM ) Base Address */
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#define VE_A7_MP_PERIPH_BASE_CS2 (0x18000000UL) /*!< (Peripheral ) Base Address */
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#define VE_A7_MP_VRAM_BASE (0x00000000UL + VE_A7_MP_PERIPH_BASE_CS2) /*!< (VRAM ) Base Address */
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#define VE_A7_MP_ETHERNET_BASE (0x02000000UL + VE_A7_MP_PERIPH_BASE_CS2) /*!< (ETHERNET ) Base Address */
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#define VE_A7_MP_USB_BASE (0x03000000UL + VE_A7_MP_PERIPH_BASE_CS2) /*!< (USB ) Base Address */
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#define VE_A7_MP_PERIPH_BASE_CS3 (0x1C000000UL) /*!< (Peripheral ) Base Address */
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#define VE_A7_MP_DAP_BASE (0x00000000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (LOCAL DAP ) Base Address */
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#define VE_A7_MP_SYSTEM_REG_BASE (0x00010000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (SYSTEM REG ) Base Address */
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#define VE_A7_MP_SERIAL_BASE (0x00030000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (SERIAL ) Base Address */
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#define VE_A7_MP_AACI_BASE (0x00040000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (AACI ) Base Address */
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#define VE_A7_MP_MMCI_BASE (0x00050000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (MMCI ) Base Address */
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#define VE_A7_MP_KMI0_BASE (0x00060000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (KMI0 ) Base Address */
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#define VE_A7_MP_UART_BASE (0x00090000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (UART ) Base Address */
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#define VE_A7_MP_WDT_BASE (0x000F0000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (WDT ) Base Address */
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#define VE_A7_MP_TIMER_BASE (0x00110000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (TIMER ) Base Address */
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#define VE_A7_MP_DVI_BASE (0x00160000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (DVI ) Base Address */
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#define VE_A7_MP_RTC_BASE (0x00170000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (RTC ) Base Address */
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#define VE_A7_MP_UART4_BASE (0x001B0000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (UART4 ) Base Address */
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#define VE_A7_MP_CLCD_BASE (0x001F0000UL + VE_A7_MP_PERIPH_BASE_CS3) /*!< (CLCD ) Base Address */
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#define VE_A7_MP_PRIVATE_PERIPH_BASE (0x2C000000UL) /*!< (Peripheral ) Base Address */
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#define VE_A7_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST ) Base Address */
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#define VE_A7_MP_GIC_INTERFACE_BASE (0x00002000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */
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#define VE_A7_MP_PL310_BASE (0x000F0000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310 ) Base Address */
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#define VE_A7_MP_SSRAM_BASE (0x2E000000UL) /*!< (System SRAM) Base Address */
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#define VE_A7_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */
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#define GIC_DISTRIBUTOR_BASE VE_A7_MP_GIC_DISTRIBUTOR_BASE
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#define GIC_INTERFACE_BASE VE_A7_MP_GIC_INTERFACE_BASE
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//The VE-A7 model implements L1 cache as architecturally defined, but does not implement L2 cache.
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//Do not enable the L2 cache if you are running RTX on a VE-A7 model as it may cause a data abort.
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#define L2C_310_BASE VE_A7_MP_PL310_BASE
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#endif
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/* -------- Configuration of the Cortex-A7 Processor and Core Peripherals ------- */
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#define __CA_REV 0x0000U /* Core revision r0p0 */
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#define __CORTEX_A 7U /* Cortex-A7 Core */
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#define __FPU_PRESENT 1U /* FPU present */
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#define __GIC_PRESENT 1U /* GIC present */
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#define __TIM_PRESENT 1U /* TIM present */
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#define __L2C_PRESENT 0U /* L2C present */
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#define __GIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
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#include "ca/core_ca.h"
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#ifndef __ASSEMBLER__
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#include "ca/system_ARMCA.h"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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