370 lines
8.7 KiB
C
370 lines
8.7 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __ARM_ARCH_ISA_ARM
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#include "mpu.h"
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#include "cmsis.h"
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#include "hal_trace.h"
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int mpu_open(void)
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{
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int i;
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if ((MPU->TYPE & MPU_TYPE_DREGION_Msk) == 0) {
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return 1;
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}
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ARM_MPU_Disable();
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for (i = 0; i < MPU_ID_QTY; i++) {
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ARM_MPU_ClrRegion(i);
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}
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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return 0;
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}
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int mpu_close(void)
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{
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ARM_MPU_Disable();
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return 0;
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}
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static int mpu_set_armv7(enum MPU_ID_T id, uint32_t addr, uint32_t len,
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int srd_bits, enum MPU_ATTR_T attr)
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{
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int ret;
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uint32_t rbar;
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uint32_t rasr;
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uint8_t xn;
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uint8_t ap;
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uint8_t size;
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if ((MPU->CTRL & MPU_CTRL_ENABLE_Msk) == 0) {
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ret = mpu_open();
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if (ret) {
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return ret;
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}
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}
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if (id >= MPU_ID_QTY) {
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return 2;
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}
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if (len < 32 || (len & (len - 1))) {
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return 3;
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}
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if (addr & (len - 1)) {
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return 4;
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}
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if (attr >= MPU_ATTR_QTY) {
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return 5;
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}
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if (attr == MPU_ATTR_READ_WRITE_EXEC || attr == MPU_ATTR_READ_EXEC ||
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attr == MPU_ATTR_EXEC) {
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xn = 0;
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} else {
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xn = 1;
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}
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ap = ARM_MPU_AP_NONE;
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if (attr == MPU_ATTR_READ_WRITE_EXEC || attr == MPU_ATTR_READ_WRITE) {
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ap = ARM_MPU_AP_FULL;
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} else if (attr == MPU_ATTR_READ_EXEC || attr == MPU_ATTR_READ) {
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ap = ARM_MPU_AP_RO;
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}
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size = __CLZ(__RBIT(len)) - 1;
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ARM_MPU_Disable();
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rbar = ARM_MPU_RBAR(id, addr);
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// Type Extention: 0
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// Shareable: 1
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// Cacheable: 1
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// Bufferable: 1
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// Subregion: 0
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rasr = ARM_MPU_RASR(xn, ap, 0, 1, 1, 1, srd_bits, size);
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ARM_MPU_SetRegion(rbar, rasr);
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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__DSB();
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__ISB();
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return 0;
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}
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/*
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* sub region is 8 bits, and if one bits is 1, the sub resion will be
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* disabled
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* like 0b00011111, the top 3 sub region will be disabled
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* if it is 0b11110000, the bottom 4 sub region will be disabled.
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*/
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static int mpu_get_top_srd(uint32_t rg_end, uint32_t fr_end,
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uint32_t sub_rg_sz)
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{
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int dis_nums;
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uint8_t srd_bits;
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dis_nums = (rg_end - fr_end) / sub_rg_sz;
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if ((fr_end & (sub_rg_sz - 1)) != 0)
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dis_nums += 1;
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srd_bits = 0xff;
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srd_bits &= ~((1UL << (8 - dis_nums)) - 1);
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return srd_bits;
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}
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static int mpu_get_bottom_srd(uint32_t rg_start, uint32_t fr_start,
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uint32_t sub_rg_sz)
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{
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int dis_nums;
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uint8_t srd_bits;
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dis_nums = (fr_start - rg_start) / sub_rg_sz;
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srd_bits = 0xff;
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srd_bits &= ((1UL << dis_nums) - 1);
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return srd_bits;
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}
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static int calc_sub_region_size(uint32_t fr_start)
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{
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int lsb_bit;
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uint32_t sz;
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//sub region size aligned to fram start
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lsb_bit = get_lsb_pos(fr_start);
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sz = 1 << lsb_bit;
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if (sz < 0x80) {
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/*cortex-m4 doesn't support sub region size less than 128 */
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TRACE(1,"no mpu region for fram start %x", fr_start);
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return -1;
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}
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if (sz > 0x4000)
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sz = 0x4000;
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return sz;
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}
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/*
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Allocate two mpu sections to protect the fast ram. The cortext M4
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mpu has a lot of restrict, such as one region's start address must
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be aligned to the size of region, and the sub region number is fixed
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to 8.
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The layout like:
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------------------
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| sub region 8 |
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------------------
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| sub region 7 |
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| ..... |
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| |
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------------------>fast_ram_end
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|////////////////|
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|////////////////|
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|////////////////|
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|////////////////|
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------------------>mpu region2
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|//sub region 8//|
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|////////////////|
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|////////////////|
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|////////////////|
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------------------>fast_ram_start aligned to sub region size
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| ..... |
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|sub region 1 |
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------------------
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|sub region 0 |
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------------------>mpu region1
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If the __fast_sram_text_exec_end__ exceed the region2's end, just leave
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the rest unprotect.
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*/
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static int mpu_fram_protect_armv7(uint32_t fr_start, uint32_t fr_end)
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{
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uint32_t fr_sz;
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uint32_t sub_rg_sz;
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uint32_t rg_sz;
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uint32_t rg_start;
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uint32_t rg_end;
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int ret = 0;
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int srd_bits;
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int finished = 0;
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fr_sz = fr_end - fr_start;
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sub_rg_sz = calc_sub_region_size(fr_start);
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if (sub_rg_sz < 0)
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return -1;
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/* according to cortex-m4 spec, the region is divived to 8 sub region*/
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rg_sz = sub_rg_sz * 8;
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/*now we just protect two region */
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if (fr_sz > (rg_sz * 2)) {
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TRACE(0,"Warning fram is too big, mpu can not protect so much");
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TRACE(2,"region_sz %x, fram size %x", rg_sz, fr_sz);
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}
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/*aliged the region start to region size according to cortext m4 spec*/
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srd_bits = 0;
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rg_start = fr_start & ~(rg_sz - 1);
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if (fr_start > rg_start) {
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int b_srd_bits = 0;
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b_srd_bits = mpu_get_bottom_srd(rg_start, fr_start, sub_rg_sz);
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srd_bits |= b_srd_bits;
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}
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rg_end = rg_start + rg_sz;
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if (fr_end < rg_end) {
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int t_srd_bits = 0;
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t_srd_bits = mpu_get_top_srd(rg_end, fr_end, sub_rg_sz);
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srd_bits |= t_srd_bits;
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finished = 1;
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}
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ret = mpu_set(MPU_ID_FRAM_TEXT1, rg_start, rg_sz, srd_bits, MPU_ATTR_READ);
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if (ret || finished)
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goto out;
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/* need another section, and start from next region*/
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rg_start += rg_sz;
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srd_bits = 0;
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rg_end = rg_start + rg_sz;
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if (fr_end < rg_end) {
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srd_bits = mpu_get_top_srd(rg_end, fr_end, sub_rg_sz);
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}
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ret = mpu_set(MPU_ID_FRAM_TEXT2, rg_start, rg_sz, srd_bits, MPU_ATTR_READ_EXEC);
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/* if fr_end large than two section, just pass */
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out:
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return ret;
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}
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int mpu_set(enum MPU_ID_T id, uint32_t addr, uint32_t len, int srd_bits,
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enum MPU_ATTR_T attr)
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{
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return mpu_set_armv7(id, addr, len, srd_bits, attr);
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}
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int mpu_clear(enum MPU_ID_T id)
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{
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uint32_t lock;
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if (id >= MPU_ID_QTY) {
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return 2;
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}
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lock = int_lock();
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ARM_MPU_ClrRegion(id);
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__DSB();
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__ISB();
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int_unlock(lock);
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return 0;
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}
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static int mpu_null_check_enable(void)
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{
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#ifdef CHIP_BEST1000
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uint32_t len = 0x400;
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#else
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uint32_t len = 0x800;
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#endif
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return mpu_set(MPU_ID_NULL_POINTER, 0, len, 0, MPU_ATTR_NO_ACCESS);
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}
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extern uint32_t __fast_sram_text_exec_start__[];
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extern uint32_t __fast_sram_text_exec_end__[];
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static int mpu_fast_ram_protect(void)
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{
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uint32_t ramx_start = (uint32_t)__fast_sram_text_exec_start__;
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uint32_t ramx_end = (uint32_t)__fast_sram_text_exec_end__;
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uint32_t ram_start = RAMX_TO_RAM(ramx_start);
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uint32_t ram_end = RAMX_TO_RAM(ramx_end);
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return mpu_fram_protect_armv7(ram_start, ram_end);
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}
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#if 0
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int mpu_fram_test(void)
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{
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uint32_t ramx_start = (uint32_t)__fast_sram_text_exec_start__;
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uint32_t ram_start = RAMX_TO_RAM(ramx_start);
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uint32_t test_start = ram_start - 1024;
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for (int i = 0; i < 1024; i++) {
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TRACE(1,"test_start %x", test_start);
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*(volatile uint32_t *)test_start = 0x1;
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test_start += 128;
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}
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uint32_t ramx_end = (uint32_t)__fast_sram_text_exec_end__;
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uint32_t ram_end = RAMX_TO_RAM(ramx_end);
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uint32_t test_end = ram_end + 1024;
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for (int i = 0; i < 1024; i++) {
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TRACE(1,"test_end %x", test_end);
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*(volatile uint32_t *)test_end = 0x1;
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test_end -= 128;
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}
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return 0;
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}
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#endif
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int mpu_setup(void)
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{
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mpu_null_check_enable();
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mpu_fast_ram_protect();
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return 0;
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}
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int mpu_setup_cp(const mpu_regions_t *mpu_table, uint32_t region_num)
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{
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int ret;
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int i;
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ret = mpu_open();
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if (ret) {
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return ret;
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}
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if (region_num > MPU_ID_QTY) {
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return -1;
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}
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for (i = 0; i < region_num; i++) {
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const mpu_regions_t *region;
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region = &mpu_table[i];
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ret = mpu_set(i, region->addr, region->len, 0, region->ap_attr);
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if (ret)
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break;
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}
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return ret;
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}
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#endif
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