208 lines
7.5 KiB
C
208 lines
7.5 KiB
C
/*----------------------------------------------------------------------------
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* RL-ARM - RTX
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*----------------------------------------------------------------------------
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* Name: RT_HAL_CM.H
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* Purpose: Hardware Abstraction Layer for Cortex-A definitions
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* Rev.: 21 Aug 2013
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*----------------------------------------------------------------------------
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*
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* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*---------------------------------------------------------------------------*/
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/* Definitions */
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#define INIT_CPSR_SYS 0x4000001F
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#define INIT_CPSR_USER 0x40000010
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#define CPSR_T_BIT 0x20
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#define CPSR_I_BIT 0x80
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#define CPSR_F_BIT 0x40
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#define MODE_USR 0x10
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_ABT 0x17
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#define MODE_UND 0x1B
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#define MODE_SYS 0x1F
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#define MAGIC_WORD 0xE25A2EA5
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#include "core_ca9.h"
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#if defined (__CC_ARM) /* ARM Compiler */
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#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
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#define __USE_EXCLUSIVE_ACCESS
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#else
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#undef __USE_EXCLUSIVE_ACCESS
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#endif
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#elif defined (__GNUC__) /* GNU Compiler */
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#undef __USE_EXCLUSIVE_ACCESS
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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#define __TARGET_FPU_VFP 1
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#else
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#define __TARGET_FPU_VFP 0
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#endif
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#define __inline inline
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#define __weak __attribute__((weak))
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#elif defined (__ICCARM__) /* IAR Compiler */
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#error IAR Compiler support not implemented for Cortex-A
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#endif
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static U8 priority = 0xff;
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extern const U32 GICDistributor_BASE;
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extern const U32 GICInterface_BASE;
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/* GIC registers - Distributor */
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#define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
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#define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
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#define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
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#define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
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#define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
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#define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
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/* GIC register - CPU Interface */
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#define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
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#define SGI_PENDSV 0 /* SGI0 */
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#define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf)))
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//Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
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#define OS_LOCK() int irq_dis = __disable_irq();\
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priority = GICI_ICCPMR; \
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GICI_ICCPMR = 0xff; \
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GICI_ICCPMR = GICI_ICCPMR - 1; \
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__DSB();\
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if(!irq_dis) __enable_irq(); \
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//Restore priority filter. Re-enable timer and PendSV signaling
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#define OS_UNLOCK() __DSB(); \
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GICI_ICCPMR = priority; \
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#define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
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#define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
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#define OS_UNPEND(fl)
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/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
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* OS_X_INIT enables the IRQ n in the GIC */
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#define OS_X_INIT(n) volatile char *reg; \
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reg = (char *)(&GICD_ICDIPR0 + n / 4); \
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reg += n % 4; \
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*reg = (char)0xff; \
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*reg = *reg - 1; \
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GICD_ICDISERx(n) = (U32)(1 << n % 32);
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#define OS_X_LOCK(n) OS_LOCK()
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#define OS_X_UNLOCK(n) OS_UNLOCK()
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#define OS_X_PEND_IRQ() OS_PEND_IRQ()
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#define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
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#define OS_X_UNPEND(fl)
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/* Functions */
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#ifdef __USE_EXCLUSIVE_ACCESS
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#define rt_inc(p) while(__strex((__ldrex(p)+1),p))
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#define rt_dec(p) while(__strex((__ldrex(p)-1),p))
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#else
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#define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
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#define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
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#endif
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__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
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U32 cnt,c2;
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#ifdef __USE_EXCLUSIVE_ACCESS
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do {
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if ((cnt = __ldrex(count)) == size) {
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__clrex();
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return (cnt); }
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} while (__strex(cnt+1, count));
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do {
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c2 = (cnt = __ldrex(first)) + 1;
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if (c2 == size) c2 = 0;
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} while (__strex(c2, first));
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#else
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int irq_dis;
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irq_dis = __disable_irq();
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if ((cnt = *count) < size) {
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*count = cnt+1;
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c2 = (cnt = *first) + 1;
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if (c2 == size) c2 = 0;
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*first = c2;
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}
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if(!irq_dis) __enable_irq ();
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#endif
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return (cnt);
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}
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__inline static void rt_systick_init (void) {
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/* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
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/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
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}
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__inline static void rt_svc_init (void) {
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/* Register pendSV - through SGI */
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volatile char *reg;
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reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
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reg += SGI_PENDSV % 4;
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/* Write 0xff to read priority level */
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*reg = (char)0xff;
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/* Read priority level and set the lowest possible*/
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*reg = *reg - 1;
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GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
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}
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extern void rt_set_PSP (U32 stack);
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extern U32 rt_get_PSP (void);
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extern void os_set_env (P_TCB p_TCB);
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extern void *_alloc_box (void *box_mem);
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extern int _free_box (void *box_mem, void *box);
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extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
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extern void rt_ret_val (P_TCB p_TCB, U32 v0);
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extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
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extern void dbg_init (void);
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extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
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extern void dbg_task_switch (U32 task_id);
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#define DBG_INIT()
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#define DBG_TASK_NOTIFY(p_tcb,create)
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#define DBG_TASK_SWITCH(task_id)
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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