192 lines
5.4 KiB
C++
192 lines
5.4 KiB
C++
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "app_pwl.h"
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#include "cmsis_os.h"
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#include "hal_gpio.h"
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#include "hal_iomux.h"
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#include "hal_trace.h"
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#include "pmu.h"
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#include "string.h"
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#include "tgt_hardware.h"
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#define APP_PWL_TRACE(s, ...)
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// TRACE(s, ##__VA_ARGS__)
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#if (CFG_HW_PLW_NUM > 0)
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static void app_pwl_timehandler(void const *param);
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osTimerDef(APP_PWL_TIMER0, app_pwl_timehandler); // define timers
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#if (CFG_HW_PLW_NUM == 2)
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osTimerDef(APP_PWL_TIMER1, app_pwl_timehandler);
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#endif
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struct APP_PWL_T {
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enum APP_PWL_ID_T id;
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struct APP_PWL_CFG_T config;
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uint8_t partidx;
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osTimerId timer;
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};
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static struct APP_PWL_T app_pwl[APP_PWL_ID_QTY];
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static void app_pwl_timehandler(void const *param) {
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struct APP_PWL_T *pwl = (struct APP_PWL_T *)param;
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struct APP_PWL_CFG_T *cfg = &(pwl->config);
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APP_PWL_TRACE(2, "%s %x", __func__, param);
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osTimerStop(pwl->timer);
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pwl->partidx++;
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if (cfg->periodic) {
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if (pwl->partidx >= cfg->parttotal) {
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pwl->partidx = 0;
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}
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} else {
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if (pwl->partidx >= cfg->parttotal) {
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return;
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}
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}
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APP_PWL_TRACE(3, "idx:%d pin:%d lvl:%d", pwl->partidx,
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cfg_hw_pinmux_pwl[pwl->id].pin, cfg->part[pwl->partidx].level);
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if (!cfg->part[pwl->partidx].level) {
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#if defined(__PMU_VIO_DYNAMIC_CTRL_MODE__)
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pmu_viorise_req(pwl->id == APP_PWL_ID_0 ? PMU_VIORISE_REQ_USER_PWL0
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: PMU_VIORISE_REQ_USER_PWL1,
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true);
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#endif
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hal_gpio_pin_set((enum HAL_GPIO_PIN_T)cfg_hw_pinmux_pwl[pwl->id].pin);
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} else {
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hal_gpio_pin_clr((enum HAL_GPIO_PIN_T)cfg_hw_pinmux_pwl[pwl->id].pin);
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#if defined(__PMU_VIO_DYNAMIC_CTRL_MODE__)
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pmu_viorise_req(pwl->id == APP_PWL_ID_0 ? PMU_VIORISE_REQ_USER_PWL0
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: PMU_VIORISE_REQ_USER_PWL1,
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false);
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#endif
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}
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osTimerStart(pwl->timer, cfg->part[pwl->partidx].time);
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}
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#endif
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int app_pwl_open(void) {
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#if (CFG_HW_PLW_NUM > 0)
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uint8_t i;
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APP_PWL_TRACE(1, "%s", __func__);
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for (i = 0; i < APP_PWL_ID_QTY; i++) {
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app_pwl[i].id = APP_PWL_ID_QTY;
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memset(&(app_pwl[i].config), 0, sizeof(struct APP_PWL_CFG_T));
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hal_iomux_init((struct HAL_IOMUX_PIN_FUNCTION_MAP *)&cfg_hw_pinmux_pwl[i],
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1);
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hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)cfg_hw_pinmux_pwl[i].pin,
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HAL_GPIO_DIR_OUT, 1);
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}
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app_pwl[APP_PWL_ID_0].timer = osTimerCreate(
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osTimer(APP_PWL_TIMER0), osTimerOnce, &app_pwl[APP_PWL_ID_0]);
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#if (CFG_HW_PLW_NUM == 2)
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app_pwl[APP_PWL_ID_1].timer = osTimerCreate(
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osTimer(APP_PWL_TIMER1), osTimerOnce, &app_pwl[APP_PWL_ID_1]);
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#endif
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#endif
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return 0;
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}
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int app_pwl_start(enum APP_PWL_ID_T id) {
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#if (CFG_HW_PLW_NUM > 0)
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struct APP_PWL_T *pwl = NULL;
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struct APP_PWL_CFG_T *cfg = NULL;
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if (id >= APP_PWL_ID_QTY) {
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return -1;
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}
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APP_PWL_TRACE(2, "%s %d", __func__, id);
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pwl = &app_pwl[id];
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cfg = &(pwl->config);
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if (pwl->id == APP_PWL_ID_QTY) {
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return -1;
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}
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pwl->partidx = 0;
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if (pwl->partidx >= cfg->parttotal) {
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return -1;
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}
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osTimerStop(pwl->timer);
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APP_PWL_TRACE(3, "idx:%d pin:%d lvl:%d", pwl->partidx,
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cfg_hw_pinmux_pwl[pwl->id].pin, cfg->part[pwl->partidx].level);
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if (!cfg->part[pwl->partidx].level) {
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#if defined(__PMU_VIO_DYNAMIC_CTRL_MODE__)
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pmu_viorise_req(pwl->id == APP_PWL_ID_0 ? PMU_VIORISE_REQ_USER_PWL0
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: PMU_VIORISE_REQ_USER_PWL1,
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false);
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#endif
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hal_gpio_pin_set((enum HAL_GPIO_PIN_T)cfg_hw_pinmux_pwl[pwl->id].pin);
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} else {
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hal_gpio_pin_clr((enum HAL_GPIO_PIN_T)cfg_hw_pinmux_pwl[pwl->id].pin);
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#if defined(__PMU_VIO_DYNAMIC_CTRL_MODE__)
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pmu_viorise_req(pwl->id == APP_PWL_ID_0 ? PMU_VIORISE_REQ_USER_PWL0
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: PMU_VIORISE_REQ_USER_PWL1,
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false);
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#endif
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}
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osTimerStart(pwl->timer, cfg->part[pwl->partidx].time);
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#endif
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return 0;
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}
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int app_pwl_setup(enum APP_PWL_ID_T id, struct APP_PWL_CFG_T *cfg) {
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#if (CFG_HW_PLW_NUM > 0)
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if (cfg == NULL || id >= APP_PWL_ID_QTY) {
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return -1;
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}
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APP_PWL_TRACE(2, "%s %d", __func__, id);
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hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)cfg_hw_pinmux_pwl[id].pin,
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HAL_GPIO_DIR_OUT, cfg->startlevel ? 0 : 1);
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app_pwl[id].id = id;
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memcpy(&(app_pwl[id].config), cfg, sizeof(struct APP_PWL_CFG_T));
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osTimerStop(app_pwl[id].timer);
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#endif
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return 0;
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}
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int app_pwl_stop(enum APP_PWL_ID_T id) {
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#if (CFG_HW_PLW_NUM > 0)
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if (id >= APP_PWL_ID_QTY) {
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return -1;
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}
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osTimerStop(app_pwl[id].timer);
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hal_gpio_pin_set((enum HAL_GPIO_PIN_T)cfg_hw_pinmux_pwl[id].pin);
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#endif
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return 0;
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}
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int app_pwl_close(void) {
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#if (CFG_HW_PLW_NUM > 0)
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uint8_t i;
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for (i = 0; i < APP_PWL_ID_QTY; i++) {
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if (app_pwl[i].id != APP_PWL_ID_QTY)
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app_pwl_stop((enum APP_PWL_ID_T)i);
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}
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#endif
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return 0;
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}
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