176 lines
5.5 KiB
C
176 lines
5.5 KiB
C
/*----------------------------------------------------------------------------
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* RL-ARM - RTX
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*----------------------------------------------------------------------------
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* Name: HAL_CM.C
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* Purpose: Hardware Abstraction Layer for Cortex-M
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* Rev.: V4.60
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*----------------------------------------------------------------------------
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*
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* Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*---------------------------------------------------------------------------*/
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#include "rt_TypeDef.h"
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#include "RTX_Conf.h"
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#include "rt_HAL_CM.h"
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/*----------------------------------------------------------------------------
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* Global Variables
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*---------------------------------------------------------------------------*/
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#ifdef DBG_MSG
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BIT dbg_msg;
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#endif
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/*----------------------------------------------------------------------------
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* Functions
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*---------------------------------------------------------------------------*/
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/*--------------------------- rt_init_stack ---------------------------------*/
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void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
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/* Prepare TCB and saved context for a first time start of a task. */
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U32 *stk,i,size;
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/* Prepare a complete interrupt frame for first task start */
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size = p_TCB->priv_stack >> 2;
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/* Write to the top of stack. */
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stk = &p_TCB->stack[size];
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/* Auto correct to 8-byte ARM stack alignment. */
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if ((U32)stk & 0x04) {
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stk--;
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}
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stk -= 16;
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/* Default xPSR and initial PC */
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stk[15] = INITIAL_xPSR;
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stk[14] = (U32)task_body;
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/* Clear R4-R11,R0-R3,R12,LR registers. */
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for (i = 0; i < 14; i++) {
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stk[i] = 0;
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}
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/* Assign a void pointer to R0. */
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stk[8] = (U32)p_TCB->msg;
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/* Initial Task stack pointer. */
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p_TCB->tsk_stack = (U32)stk;
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/* Task entry point. */
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p_TCB->ptask = task_body;
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/* Set a magic word for checking of stack overflow.
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For the main thread (ID: 0x01) the stack is in a memory area shared with the
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heap, therefore the last word of the stack is a moving target.
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We want to do stack/heap collision detection instead.
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*/
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if (p_TCB->task_id != 0x01) {
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p_TCB->stack[0] = MAGIC_WORD;
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#ifdef DEBUG
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for (i = 1; i < (stk - p_TCB->stack); i++) {
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p_TCB->stack[i] = 0xCCCCCCCC;
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}
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#endif
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}
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}
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/*--------------------------- rt_ret_val ----------------------------------*/
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static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
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/* Get pointer to task return value registers (R0..R3) in Stack */
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#if (__TARGET_FPU_VFP)
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if (p_TCB->stack_frame) {
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/* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */
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return (U32 *)(p_TCB->tsk_stack + 8*4 + 16*4);
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} else {
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/* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
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return (U32 *)(p_TCB->tsk_stack + 8*4);
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}
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#else
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/* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
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return (U32 *)(p_TCB->tsk_stack + 8*4);
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#endif
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}
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void rt_ret_val (P_TCB p_TCB, U32 v0) {
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U32 *ret;
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ret = rt_ret_regs(p_TCB);
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ret[0] = v0;
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}
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void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
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U32 *ret;
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ret = rt_ret_regs(p_TCB);
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ret[0] = v0;
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ret[1] = v1;
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}
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/*--------------------------- dbg_init --------------------------------------*/
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#ifdef DBG_MSG
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void dbg_init (void) {
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if ((DEMCR & DEMCR_TRCENA) &&
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(ITM_CONTROL & ITM_ITMENA) &&
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(ITM_ENABLE & (1UL << 31))) {
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dbg_msg = __TRUE;
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}
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}
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#endif
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/*--------------------------- dbg_task_notify -------------------------------*/
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#ifdef DBG_MSG
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void dbg_task_notify (P_TCB p_tcb, BOOL create) {
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while (ITM_PORT31_U32 == 0);
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ITM_PORT31_U32 = (U32)p_tcb->ptask;
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while (ITM_PORT31_U32 == 0);
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ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
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}
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#endif
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/*--------------------------- dbg_task_switch -------------------------------*/
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#ifdef DBG_MSG
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void dbg_task_switch (U32 task_id) {
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while (ITM_PORT31_U32 == 0);
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ITM_PORT31_U8 = task_id;
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}
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#endif
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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