447 lines
12 KiB
C
447 lines
12 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_addr_map.h"
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#include "hal_cmu.h"
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#include CHIP_SPECIFIC_HDR(reg_cmu)
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#ifdef AON_CMU_BASE
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#include CHIP_SPECIFIC_HDR(reg_aoncmu)
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#endif
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#include "cmsis.h"
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#include "hal_analogif.h"
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#include "hal_bootmode.h"
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#include "hal_cache.h"
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#include "hal_chipid.h"
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#include "hal_iomux.h"
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#include "hal_location.h"
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#include "hal_norflash.h"
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#include "hal_sleep.h"
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#include "hal_sysfreq.h"
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#include "hal_timer.h"
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#include "hal_trace.h"
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#if defined(CHIP_HAS_USB) && (defined(MCU_HIGH_PERFORMANCE_MODE) && !(defined(ULTRA_LOW_POWER) || defined(OSC_26M_X4_AUD2BB)))
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#define USB_PLL_INIT_ON
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#endif
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#if (!defined(ULTRA_LOW_POWER) && !defined(OSC_26M_X4_AUD2BB)) || \
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(!defined(FLASH_LOW_SPEED) && !defined(OSC_26M_X4_AUD2BB)) || \
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(defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED))
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#define AUD_PLL_INIT_ON
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#endif
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// SIMU_RES
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#define CMU_SIMU_RES_PASSED (0x9A55)
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#define CMU_SIMU_RES_FAILED (0xFA11)
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typedef void (*HAL_POWER_DOWN_WAKEUP_HANDLER)(void);
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static struct CMU_T * const cmu = (struct CMU_T *)CMU_BASE;
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#ifdef AON_CMU_BASE
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static struct AONCMU_T * const POSSIBLY_UNUSED aoncmu = (struct AONCMU_T *)AON_CMU_BASE;
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#endif
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#ifdef HAL_CMU_VALID_CRYSTAL_FREQ
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static const uint32_t valid_crystal_freq_list[] = HAL_CMU_VALID_CRYSTAL_FREQ;
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#define CRYSTAL_FREQ_ATTR BOOT_DATA_LOC
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#else
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#define CRYSTAL_FREQ_ATTR const
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#endif
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static uint32_t CRYSTAL_FREQ_ATTR crystal_freq = HAL_CMU_DEFAULT_CRYSTAL_FREQ;
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void BOOT_TEXT_FLASH_LOC hal_cmu_set_crystal_freq_index(uint32_t index)
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{
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#ifdef HAL_CMU_VALID_CRYSTAL_FREQ
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if (index >= ARRAY_SIZE(valid_crystal_freq_list)) {
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index %= ARRAY_SIZE(valid_crystal_freq_list);
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}
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crystal_freq = valid_crystal_freq_list[index];
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#endif
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}
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uint32_t BOOT_TEXT_SRAM_LOC hal_cmu_get_crystal_freq(void)
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{
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return crystal_freq;
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}
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uint32_t BOOT_TEXT_FLASH_LOC hal_cmu_get_default_crystal_freq(void)
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{
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return HAL_CMU_DEFAULT_CRYSTAL_FREQ;
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}
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void hal_cmu_write_lock(void)
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{
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cmu->WRITE_UNLOCK = 0xCAFE0000;
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}
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void hal_cmu_write_unlock(void)
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{
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cmu->WRITE_UNLOCK = 0xCAFE0001;
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}
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void hal_cmu_sys_reboot(void)
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{
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hal_cmu_reset_set(HAL_CMU_MOD_GLOBAL);
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}
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void hal_cmu_simu_init(void)
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{
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cmu->SIMU_RES = 0;
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}
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void hal_cmu_simu_pass(void)
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{
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cmu->SIMU_RES = CMU_SIMU_RES_PASSED;
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}
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void hal_cmu_simu_fail(void)
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{
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cmu->SIMU_RES = CMU_SIMU_RES_FAILED;
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}
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void hal_cmu_simu_tag(uint8_t shift)
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{
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cmu->SIMU_RES |= (1 << shift);
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}
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void hal_cmu_simu_set_val(uint32_t val)
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{
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cmu->SIMU_RES = val;
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}
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uint32_t hal_cmu_simu_get_val(void)
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{
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return cmu->SIMU_RES;
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}
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void hal_cmu_set_wakeup_pc(uint32_t pc)
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{
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#ifdef RAMRET_BASE
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uint32_t *wake_pc =
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#ifdef CHIP_BEST2000
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(uint32_t *)RAMRET_BASE;
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#else
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(uint32_t *)&aoncmu->WAKEUP_PC;
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STATIC_ASSERT(sizeof(HAL_POWER_DOWN_WAKEUP_HANDLER) <= sizeof(uint32_t), "Invalid func ptr size");
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#endif
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*wake_pc = pc;
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#endif
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}
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void hal_cmu_rom_wakeup_check(void)
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{
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#ifdef RAMRET_BASE
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union HAL_HW_BOOTMODE_T hw;
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uint32_t sw;
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HAL_POWER_DOWN_WAKEUP_HANDLER *wake_fn =
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#ifdef CHIP_BEST2000
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(HAL_POWER_DOWN_WAKEUP_HANDLER *)RAMRET_BASE;
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#else
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(HAL_POWER_DOWN_WAKEUP_HANDLER *)&aoncmu->WAKEUP_PC;
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#endif
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hw = hal_rom_hw_bootmode_get();
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if (hw.watchdog == 0 && hw.global == 0) {
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sw = hal_sw_bootmode_get();
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if ((sw & HAL_SW_BOOTMODE_POWER_DOWN_WAKEUP) && *wake_fn) {
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(*wake_fn)();
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}
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}
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*wake_fn = NULL;
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#endif
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}
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#ifndef HAL_CMU_PLL_T
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void hal_cmu_rom_enable_pll(void)
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{
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#ifdef CHIP_HAS_USB
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hal_cmu_pll_enable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
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hal_cmu_sys_select_pll(HAL_CMU_PLL_USB);
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hal_cmu_flash_select_pll(HAL_CMU_PLL_USB);
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#else
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hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
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hal_cmu_sys_select_pll(HAL_CMU_PLL_AUD);
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hal_cmu_flash_select_pll(HAL_CMU_PLL_AUD);
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#endif
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}
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void hal_cmu_programmer_enable_pll(void)
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{
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hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
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hal_cmu_flash_select_pll(HAL_CMU_PLL_AUD);
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hal_cmu_sys_select_pll(HAL_CMU_PLL_AUD);
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}
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void BOOT_TEXT_FLASH_LOC hal_cmu_init_pll_selection(void)
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{
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// !!!!!!
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// CAUTION:
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// hal_cmu_pll_enable()/hal_cmu_pll_disable() must be called after hal_chipid_init(),
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// for the init div values are extracted in hal_chipid_init().
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// !!!!!!
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#if defined(CHIP_BEST1000) || defined(CHIP_BEST2000)
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#ifdef CHIP_HAS_USB
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// Enable USB PLL before switching (clock mux requirement)
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// -- USB PLL might not be started in ROM
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hal_cmu_pll_enable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
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#endif
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hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
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#else // !(best1000 || best2000)
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// Disable the PLL which might be enabled in ROM
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#ifdef CHIP_HAS_USB
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hal_cmu_pll_disable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_ALL);
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#else
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hal_cmu_pll_disable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_ALL);
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#endif
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#endif // !(best1000 || best2000)
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#ifdef FLASH_LOW_SPEED
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#ifdef CHIP_HAS_USB
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// Switch flash clock to USB PLL, and then shutdown USB PLL,
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// to save power consumed in clock divider
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hal_cmu_flash_select_pll(HAL_CMU_PLL_USB);
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#endif
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#else
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// Switch flash clock to audio PLL
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hal_cmu_flash_select_pll(HAL_CMU_PLL_AUD);
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#endif
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#ifdef CHIP_HAS_PSRAM
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#ifdef PSRAM_LOW_SPEED
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#ifdef CHIP_HAS_USB
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// Switch psram clock to USB PLL, and then shutdown USB PLL,
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// to save power consumed in clock divider
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hal_cmu_mem_select_pll(HAL_CMU_PLL_USB);
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#endif
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#else
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// Switch psram clock to audio PLL
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hal_cmu_mem_select_pll(HAL_CMU_PLL_AUD);
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#endif
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#endif
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// Select system PLL after selecting flash/psram PLLs
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#ifdef ULTRA_LOW_POWER
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hal_cmu_low_freq_mode_init();
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#else
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#if defined(MCU_HIGH_PERFORMANCE_MODE) && defined(CHIP_HAS_USB)
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// Switch system clocks to USB PLL
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hal_cmu_sys_select_pll(HAL_CMU_PLL_USB);
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#else
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// Switch system clocks to audio PLL
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hal_cmu_sys_select_pll(HAL_CMU_PLL_AUD);
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#endif
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#endif
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#if defined(CHIP_BEST1000) || defined(CHIP_BEST2000)
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#ifndef USB_PLL_INIT_ON
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// Disable USB PLL after switching (clock mux requirement)
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hal_cmu_pll_disable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
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#endif
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#ifndef AUD_PLL_INIT_ON
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hal_cmu_pll_disable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
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#endif
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#else // !(best1000 || best2000)
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#ifdef USB_PLL_INIT_ON
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hal_cmu_pll_enable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
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#endif
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#ifdef AUD_PLL_INIT_ON
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hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
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#endif
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#endif // !(best1000 || best2000)
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#if defined(MCU_HIGH_PERFORMANCE_MODE) && !defined(ULTRA_LOW_POWER) && defined(OSC_26M_X4_AUD2BB)
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#error "Error configuration: MCU_HIGH_PERFORMANCE_MODE has no effect"
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#endif
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}
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#endif // !HAL_CMU_PLL_T
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static void BOOT_TEXT_FLASH_LOC hal_cmu_init_periph_clock(void)
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{
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#ifdef PERIPH_PLL_FREQ
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hal_cmu_periph_set_div(1);
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#endif
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// TODO: Move the following SDIO freq setting to hal_sdio.c
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#ifdef CHIP_HAS_SDIO
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hal_cmu_sdio_set_freq(HAL_CMU_PERIPH_FREQ_26M);
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#endif
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}
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void hal_cmu_rom_setup(void)
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{
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hal_cmu_lpu_wait_26m_ready();
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hal_cmu_simu_init();
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hal_cmu_rom_clock_init();
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hal_cmu_timer0_select_slow();
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#ifdef TIMER1_BASE
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hal_cmu_timer1_select_fast();
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#endif
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hal_sys_timer_open();
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// Init sys clock
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hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
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// Init flash clock (this should be done before load_boot_settings, for security register read)
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hal_cmu_flash_set_freq(HAL_CMU_FREQ_26M);
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// Reset flash controller (for JTAG reset and run)
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// Enable flash controller (flash controller is reset by default since BEST1400)
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hal_cmu_reset_set(HAL_CMU_MOD_O_FLASH);
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hal_cmu_reset_set(HAL_CMU_MOD_H_FLASH);
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hal_cmu_reset_clear(HAL_CMU_MOD_H_FLASH);
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hal_cmu_reset_clear(HAL_CMU_MOD_O_FLASH);
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// Disable cache (for JTAG reset and run)
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hal_cache_disable(HAL_CACHE_ID_I_CACHE);
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hal_cache_disable(HAL_CACHE_ID_D_CACHE);
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// Init APB clock
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hal_cmu_apb_init_div();
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}
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void hal_cmu_programmer_setup(void)
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{
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hal_cmu_ema_init();
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hal_sys_timer_open();
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#ifdef JTAG_ENABLE
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hal_iomux_set_jtag();
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hal_cmu_jtag_clock_enable();
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#endif
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#ifndef FPGA
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int ret;
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// Open analogif (ISPI)
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ret = hal_analogif_open();
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if (ret) {
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hal_cmu_simu_tag(31);
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do { volatile int i = 0; i++; } while (1);
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}
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// Init chip id
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// 1) Read id from ana/rf/pmu
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// 2) Init clock settings in ana/rf/pmu if the default h/w register values are bad
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hal_chipid_init();
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// Enable OSC X2/X4 in cmu after enabling their source in hal_chipid_init()
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hal_cmu_osc_x2_enable();
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hal_cmu_osc_x4_enable();
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#endif
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}
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#ifdef FPGA
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void BOOT_TEXT_FLASH_LOC hal_cmu_fpga_setup(void)
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{
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hal_cmu_timer0_select_slow();
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hal_sys_timer_open();
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hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, HAL_CMU_FREQ_52M);
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hal_cmu_apb_init_div();
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hal_cmu_ispi_set_freq(HAL_CMU_PERIPH_FREQ_26M);
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// Init peripheral clocks
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hal_cmu_init_periph_clock();
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hal_norflash_init();
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#if defined(CHIP_HAS_PSRAM) && defined(PSRAM_ENABLE)
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hal_psram_init();
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#endif
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}
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#else // !FPGA
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void BOOT_TEXT_FLASH_LOC hal_cmu_setup(void)
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{
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int ret;
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enum HAL_CMU_FREQ_T freq;
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hal_iomux_set_default_config();
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#ifdef JTAG_ENABLE
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hal_iomux_set_jtag();
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hal_cmu_jtag_clock_enable();
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#endif
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hal_cmu_module_init_state();
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hal_cmu_ema_init();
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hal_cmu_timer0_select_slow();
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#ifdef TIMER1_BASE
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hal_cmu_timer1_select_fast();
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#endif
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hal_sys_timer_open();
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hal_hw_bootmode_init();
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// Init system/flash/memory clocks before initializing clock setting
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// and before switching PLL
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hal_norflash_set_freq(HAL_CMU_FREQ_26M);
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hal_cmu_mem_set_freq(HAL_CMU_FREQ_26M);
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hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
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// Set ISPI module freq
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hal_cmu_ispi_set_freq(HAL_CMU_PERIPH_FREQ_26M);
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// Open analogif (ISPI)
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ret = hal_analogif_open();
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if (ret) {
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hal_cmu_simu_tag(31);
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do { volatile int i = 0; i++; } while (1);
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}
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// Init chip id
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// 1) Read id from ana/rf/pmu
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// 2) Init clock settings in ana/rf/pmu if the default h/w register values are bad
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hal_chipid_init();
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#ifdef CALIB_SLOW_TIMER
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// Calib slow timer after determining the crystal freq
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hal_sys_timer_calib();
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#endif
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// Enable OSC X2/X4 in cmu after enabling their source in hal_chipid_init()
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hal_cmu_osc_x2_enable();
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hal_cmu_osc_x4_enable();
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// Init PLL selection
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hal_cmu_init_pll_selection();
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// Init peripheral clocks
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hal_cmu_init_periph_clock();
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// Sleep setting
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#ifdef NO_LPU_26M
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while (hal_cmu_lpu_init(HAL_CMU_LPU_CLK_NONE) == -1);
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#else
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while (hal_cmu_lpu_init(HAL_CMU_LPU_CLK_26M) == -1);
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#endif
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// Init sys freq after applying the sleep setting (which might change sys freq)
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#ifdef NO_LPU_26M
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hal_sys_timer_delay(MS_TO_TICKS(20));
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#endif
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// Init system clock
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#ifdef ULTRA_LOW_POWER
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freq = HAL_CMU_FREQ_52M;
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#else
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freq = HAL_CMU_FREQ_104M;
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#endif
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hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, freq);
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// Init flash
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hal_norflash_init();
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}
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#endif // !FPGA
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