462 lines
10 KiB
C
462 lines
10 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __HAL_CMU_H__
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#define __HAL_CMU_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stdint.h"
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#include "plat_addr_map.h"
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#include CHIP_SPECIFIC_HDR(hal_cmu)
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#ifndef HAL_CMU_DEFAULT_CRYSTAL_FREQ
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#define HAL_CMU_DEFAULT_CRYSTAL_FREQ 26000000
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#endif
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#define LPU_TIMER_US(us) (((us) * 32 + 1000 - 1) / 1000)
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enum HAL_CMU_CLK_STATUS_T {
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HAL_CMU_CLK_DISABLED,
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HAL_CMU_CLK_ENABLED,
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};
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enum HAL_CMU_CLK_MODE_T {
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HAL_CMU_CLK_AUTO,
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HAL_CMU_CLK_MANUAL,
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};
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enum HAL_CMU_RST_STATUS_T {
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HAL_CMU_RST_SET,
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HAL_CMU_RST_CLR,
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};
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enum HAL_CMU_TIMER_ID_T {
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HAL_CMU_TIMER_ID_00,
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HAL_CMU_TIMER_ID_01,
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HAL_CMU_TIMER_ID_10,
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HAL_CMU_TIMER_ID_11,
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HAL_CMU_TIMER_ID_20,
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HAL_CMU_TIMER_ID_21,
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};
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#ifndef HAL_CMU_FREQ_T
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enum HAL_CMU_FREQ_T {
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HAL_CMU_FREQ_32K,
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HAL_CMU_FREQ_26M,
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HAL_CMU_FREQ_52M,
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HAL_CMU_FREQ_78M,
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HAL_CMU_FREQ_104M,
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HAL_CMU_FREQ_208M,
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HAL_CMU_FREQ_QTY
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};
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#endif
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#ifndef HAL_CMU_PLL_T
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enum HAL_CMU_PLL_T {
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HAL_CMU_PLL_AUD,
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HAL_CMU_PLL_USB,
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HAL_CMU_PLL_QTY
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};
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#endif
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#ifndef HAL_CMU_PLL_USER_T
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enum HAL_CMU_PLL_USER_T {
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HAL_CMU_PLL_USER_SYS,
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HAL_CMU_PLL_USER_AUD,
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HAL_CMU_PLL_USER_USB,
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HAL_CMU_PLL_USER_QTY,
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HAL_CMU_PLL_USER_ALL = HAL_CMU_PLL_USER_QTY,
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};
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#endif
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enum HAL_CMU_PERIPH_FREQ_T {
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HAL_CMU_PERIPH_FREQ_26M,
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HAL_CMU_PERIPH_FREQ_52M,
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HAL_CMU_PERIPH_FREQ_QTY
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};
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enum HAL_CMU_LPU_CLK_CFG_T {
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HAL_CMU_LPU_CLK_NONE,
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HAL_CMU_LPU_CLK_26M,
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HAL_CMU_LPU_CLK_PLL,
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HAL_CMU_LPU_CLK_QTY
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};
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enum HAL_CMU_LPU_SLEEP_MODE_T {
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HAL_CMU_LPU_SLEEP_MODE_SYS,
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HAL_CMU_LPU_SLEEP_MODE_CHIP,
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HAL_CMU_LPU_SLEEP_MODE_QTY
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};
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#ifndef HAL_PWM_ID_T
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enum HAL_PWM_ID_T {
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HAL_PWM_ID_0,
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HAL_PWM_ID_1,
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HAL_PWM_ID_2,
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HAL_PWM_ID_3,
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HAL_PWM_ID_QTY
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};
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#endif
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#ifndef HAL_I2S_ID_T
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enum HAL_I2S_ID_T {
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HAL_I2S_ID_0 = 0,
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HAL_I2S_ID_QTY,
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};
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#endif
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#ifndef HAL_SPDIF_ID_T
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enum HAL_SPDIF_ID_T {
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HAL_SPDIF_ID_0 = 0,
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HAL_SPDIF_ID_QTY,
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};
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#endif
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enum HAL_CMU_USB_CLOCK_SEL_T {
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HAL_CMU_USB_CLOCK_SEL_PLL,
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HAL_CMU_USB_CLOCK_SEL_24M_X2,
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HAL_CMU_USB_CLOCK_SEL_48M,
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HAL_CMU_USB_CLOCK_SEL_26M_X2,
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HAL_CMU_USB_CLOCK_SEL_26M_X4,
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};
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void hal_cmu_set_crystal_freq_index(uint32_t index);
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uint32_t hal_cmu_get_crystal_freq(void);
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uint32_t hal_cmu_get_default_crystal_freq(void);
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int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id);
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int hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id);
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enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id);
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int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mode);
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enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id);
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int hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id);
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int hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id);
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enum HAL_CMU_RST_STATUS_T hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id);
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int hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id);
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int hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id, uint32_t div);
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void hal_cmu_timer0_select_fast(void);
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void hal_cmu_timer0_select_slow(void);
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void hal_cmu_timer1_select_fast(void);
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void hal_cmu_timer1_select_slow(void);
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void hal_cmu_timer2_select_fast(void);
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void hal_cmu_timer2_select_slow(void);
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void hal_cmu_dsp_timer0_select_fast(void);
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void hal_cmu_dsp_timer0_select_slow(void);
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void hal_cmu_dsp_timer1_select_fast(void);
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void hal_cmu_dsp_timer1_select_slow(void);
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int hal_cmu_periph_set_div(uint32_t div);
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int hal_cmu_uart0_set_div(uint32_t div);
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int hal_cmu_uart1_set_div(uint32_t div);
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int hal_cmu_uart2_set_div(uint32_t div);
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int hal_cmu_spi_set_div(uint32_t div);
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int hal_cmu_slcd_set_div(uint32_t div);
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int hal_cmu_sdio_set_div(uint32_t div);
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int hal_cmu_sdmmc_set_div(uint32_t div);
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int hal_cmu_i2c_set_div(uint32_t div);
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int hal_cmu_uart0_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_uart1_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_uart2_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_spi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_slcd_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_sdio_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_sdmmc_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_i2c_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq);
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int hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id, uint32_t freq);
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int hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq);
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int hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq);
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int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq);
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enum HAL_CMU_FREQ_T hal_cmu_sys_get_freq(void);
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enum HAL_CMU_FREQ_T hal_cmu_flash_get_freq(void);
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int hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll);
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int hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll);
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int hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll);
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int hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll);
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int hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user);
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int hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user);
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void hal_cmu_audio_resample_enable(void);
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void hal_cmu_audio_resample_disable(void);
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int hal_cmu_get_audio_resample_status(void);
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int hal_cmu_codec_adc_set_div(uint32_t div);
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uint32_t hal_cmu_codec_adc_get_div(void);
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int hal_cmu_codec_dac_set_div(uint32_t div);
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uint32_t hal_cmu_codec_dac_get_div(void);
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void hal_cmu_codec_clock_enable(void);
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void hal_cmu_codec_clock_disable(void);
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void hal_cmu_codec_reset_set(void);
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void hal_cmu_codec_reset_clear(void);
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void hal_cmu_codec_iir_enable(uint32_t speed);
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void hal_cmu_codec_iir_disable(void);
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int hal_cmu_codec_iir_set_div(uint32_t div);
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void hal_cmu_codec_iir_eq_enable(uint32_t speed);
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void hal_cmu_codec_iir_eq_disable(void);
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void hal_cmu_codec_psap_enable(uint32_t speed);
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void hal_cmu_codec_psap_disable(void);
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void hal_cmu_codec_fir_enable(uint32_t speed);
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void hal_cmu_codec_fir_disable(void);
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int hal_cmu_codec_fir_set_div(uint32_t div);
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void hal_cmu_codec_fir_select_sys_clock(void);
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void hal_cmu_codec_fir_select_own_clock(void);
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void hal_cmu_codec_rs_enable(uint32_t speed);
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void hal_cmu_codec_rs_disable(void);
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int hal_cmu_codec_rs_set_div(uint32_t div);
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void hal_cmu_codec_rs_adc_enable(uint32_t speed);
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void hal_cmu_codec_rs_adc_disable(void);
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int hal_cmu_codec_rs_adc_set_div(uint32_t div);
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void hal_cmu_codec_set_fault_mask(uint32_t msk);
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void hal_cmu_i2s_clock_out_enable(enum HAL_I2S_ID_T id);
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void hal_cmu_i2s_clock_out_disable(enum HAL_I2S_ID_T id);
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void hal_cmu_i2s_set_slave_mode(enum HAL_I2S_ID_T id);
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void hal_cmu_i2s_set_master_mode(enum HAL_I2S_ID_T id);
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void hal_cmu_i2s_clock_enable(enum HAL_I2S_ID_T id);
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void hal_cmu_i2s_clock_disable(enum HAL_I2S_ID_T id);
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int hal_cmu_i2s_set_div(enum HAL_I2S_ID_T id, uint32_t div);
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int hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id);
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void hal_cmu_i2s_mclk_disable(void);
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void hal_cmu_pcm_clock_out_enable(void);
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void hal_cmu_pcm_clock_out_disable(void);
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void hal_cmu_pcm_set_slave_mode(int clk_pol);
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void hal_cmu_pcm_set_master_mode(void);
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void hal_cmu_pcm_clock_enable(void);
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void hal_cmu_pcm_clock_disable(void);
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int hal_cmu_pcm_set_div(uint32_t div);
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int hal_cmu_spdif_clock_enable(enum HAL_SPDIF_ID_T id);
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int hal_cmu_spdif_clock_disable(enum HAL_SPDIF_ID_T id);
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int hal_cmu_spdif_set_div(enum HAL_SPDIF_ID_T id, uint32_t div);
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void hal_cmu_usb_set_device_mode(void);
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void hal_cmu_usb_set_host_mode(void);
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void hal_cmu_rom_select_usb_clock(enum HAL_CMU_USB_CLOCK_SEL_T sel);
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void hal_cmu_usb_clock_enable(void);
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void hal_cmu_usb_clock_disable(void);
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void hal_cmu_bt_clock_enable(void);
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void hal_cmu_bt_clock_disable(void);
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void hal_cmu_bt_reset_set(void);
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void hal_cmu_bt_reset_clear(void);
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void hal_cmu_bt_module_init(void);
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void hal_cmu_bt_sys_clock_force_on(void);
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void hal_cmu_bt_sys_clock_auto(void);
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void hal_cmu_bt_sys_set_freq(enum HAL_CMU_FREQ_T freq);
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int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id);
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void hal_cmu_clock_out_disable(void);
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void hal_cmu_write_lock(void);
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void hal_cmu_write_unlock(void);
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void hal_cmu_sys_reboot(void);
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void hal_cmu_jtag_enable(void);
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void hal_cmu_jtag_disable(void);
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void hal_cmu_jtag_clock_enable(void);
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void hal_cmu_jtag_clock_disable(void);
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void hal_cmu_simu_init(void);
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void hal_cmu_simu_pass(void);
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void hal_cmu_simu_fail(void);
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void hal_cmu_simu_tag(uint8_t shift);
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void hal_cmu_simu_set_val(uint32_t val);
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uint32_t hal_cmu_simu_get_val(void);
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void hal_cmu_low_freq_mode_init(void);
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void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq);
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void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq);
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void hal_cmu_rom_enable_pll(void);
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void hal_cmu_programmer_enable_pll(void);
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void hal_cmu_init_pll_selection(void);
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void hal_cmu_rom_setup(void);
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void hal_cmu_programmer_setup(void);
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void hal_cmu_fpga_setup(void);
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void hal_cmu_setup(void);
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// Some internal functions
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void hal_cmu_apb_init_div(void);
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void hal_cmu_rom_clock_init(void);
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void hal_cmu_init_chip_feature(uint16_t feature);
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void hal_cmu_osc_x2_enable(void);
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void hal_cmu_osc_x4_enable(void);
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void hal_cmu_module_init_state(void);
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void hal_cmu_ema_init(void);
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void hal_cmu_lpu_wait_26m_ready(void);
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int hal_cmu_lpu_busy(void);
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int hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg);
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int hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode);
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void hal_cmu_set_wakeup_pc(uint32_t pc);
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volatile uint32_t *hal_cmu_get_bootmode_addr(void);
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volatile uint32_t *hal_cmu_get_memsc_addr(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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