211 lines
5.7 KiB
C
211 lines
5.7 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_addr_map.h"
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#ifdef BTPCM_BASE
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#include "plat_types.h"
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#include "reg_btpcmip.h"
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#include "hal_btpcmip.h"
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#include "hal_btpcm.h"
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#include "hal_uart.h"
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#include "hal_trace.h"
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#include "hal_timer.h"
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#include "hal_cmu.h"
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//#define BTPCM_CLOCK_SOURCE 240000000
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#define BTPCM_CLOCK_SOURCE 22579200
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//#define BTPCM_CLOCK_SOURCE 48000000
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//#define BTPCM_CLOCK_SOURCE 3072000
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//#define BTPCM_CLOCK_SOURCE 76800000
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//#define BTPCM_CLOCK_SOURCE 84672000
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//#define HAL_BTPCM_TX_FIFO_TRIGGER_LEVEL (BTPCMIP_FIFO_DEPTH/2)
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//#define HAL_BTPCM_RX_FIFO_TRIGGER_LEVEL (BTPCMIP_FIFO_DEPTH/2)
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#define HAL_BTPCM_TX_FIFO_TRIGGER_LEVEL (1)
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#define HAL_BTPCM_RX_FIFO_TRIGGER_LEVEL (0)
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#define HAL_BTPCM_YES 1
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#define HAL_BTPCM_NO 0
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static const char * const invalid_id = "Invalid BTPCM ID: %d\n";
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//static const char * const invalid_ch = "Invalid BTPCM CH: %d\n";
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static bool btpcm_opened[HAL_BTPCM_ID_NUM][AUD_STREAM_NUM];
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static inline POSSIBLY_UNUSED unsigned char reverse(unsigned char in)
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{
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uint8_t out = 0;
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uint32_t i = 0;
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for (i = 0; i < 8; ++i) {
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if((1<<i & in))
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out = out | (1<<(7-i));
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else
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out = out & (~(1<<(7-i)));
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}
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return out;
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}
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static inline uint32_t _btpcm_get_reg_base(enum HAL_BTPCM_ID_T id)
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{
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ASSERT(id < HAL_BTPCM_ID_NUM, invalid_id, id);
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switch(id) {
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case HAL_BTPCM_ID_0:
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default:
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return BTPCM_BASE;
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break;
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}
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return 0;
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}
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int hal_btpcm_open(enum HAL_BTPCM_ID_T id, enum AUD_STREAM_T stream)
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{
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uint32_t reg_base;
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reg_base = _btpcm_get_reg_base(id);
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if (!btpcm_opened[id][AUD_STREAM_PLAYBACK] && !btpcm_opened[id][AUD_STREAM_CAPTURE]) {
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// Init to slave mode before enabling module clock
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// Make sure the clock mux is switched when there is no clock active
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hal_cmu_pcm_set_slave_mode(true);
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hal_cmu_pcm_clock_enable();
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hal_cmu_clock_enable(HAL_CMU_MOD_O_PCM);
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hal_cmu_clock_enable(HAL_CMU_MOD_P_PCM);
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hal_cmu_reset_clear(HAL_CMU_MOD_O_PCM);
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hal_cmu_reset_clear(HAL_CMU_MOD_P_PCM);
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// After release pclk reset, need delay 2 tick to access any pcm reg.
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hal_sys_timer_delay(2);
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btpcmip_pcm_clk_open_en(reg_base,0);
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btpcmip_w_enable_rx_dma(reg_base, HAL_BTPCM_NO);
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btpcmip_w_enable_tx_dma(reg_base, HAL_BTPCM_NO);
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btpcmip_flush_tx_fifo(reg_base);
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btpcmip_flush_rx_fifo(reg_base);
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btpcmip_w_slot_sel(reg_base, 0);
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btpcmip_w_shortsync(reg_base, HAL_BTPCM_YES);
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btpcmip_w_signin(reg_base, HAL_BTPCM_YES);
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btpcmip_w_mask1mask2(reg_base, 0);
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btpcmip_w_enable_btpcmip(reg_base, HAL_BTPCM_YES);
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// Generate 10 clock cycles for BTPCM module to initialize its states
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for (int i = 0; i < 10; i++) {
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hal_cmu_pcm_set_slave_mode(false);
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hal_cmu_pcm_set_slave_mode(true);
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}
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//btpcmip_w_length(reg_base, 0x05); //16 bit
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}
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btpcm_opened[id][stream] = true;
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return 0;
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}
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int hal_btpcm_close(enum HAL_BTPCM_ID_T id, enum AUD_STREAM_T stream)
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{
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uint32_t reg_base;
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reg_base = _btpcm_get_reg_base(id);
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btpcm_opened[id][stream] = false;
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if (!btpcm_opened[id][AUD_STREAM_PLAYBACK] && !btpcm_opened[id][AUD_STREAM_CAPTURE]) {
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btpcmip_w_enable_btpcmip(reg_base, HAL_BTPCM_NO);
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//don't need flush rx and tx fifo
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hal_cmu_reset_set(HAL_CMU_MOD_P_PCM);
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hal_cmu_reset_set(HAL_CMU_MOD_O_PCM);
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hal_cmu_clock_disable(HAL_CMU_MOD_P_PCM);
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hal_cmu_clock_disable(HAL_CMU_MOD_O_PCM);
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hal_cmu_pcm_clock_disable();
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}
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return 0;
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}
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int hal_btpcm_start_stream(enum HAL_BTPCM_ID_T id, enum AUD_STREAM_T stream)
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{
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return 0;
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}
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int hal_btpcm_stop_stream(enum HAL_BTPCM_ID_T id, enum AUD_STREAM_T stream)
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{
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return 0;
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}
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int hal_btpcm_setup_stream(enum HAL_BTPCM_ID_T id, enum AUD_STREAM_T stream, struct HAL_BTPCM_CONFIG_T *cfg)
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{
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uint32_t reg_base;
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reg_base = _btpcm_get_reg_base(id);
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if (!btpcm_opened[id][stream]) {
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return 1;
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}
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if (stream == AUD_STREAM_PLAYBACK)
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{
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//dma config
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btpcmip_w_tx_fifo_threshold(reg_base, HAL_BTPCM_TX_FIFO_TRIGGER_LEVEL);
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btpcmip_w_enable_tx_dma(reg_base, HAL_BTPCM_YES);
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}
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else
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{
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//dma config
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btpcmip_w_rx_fifo_threshold(reg_base, HAL_BTPCM_RX_FIFO_TRIGGER_LEVEL);
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btpcmip_w_enable_rx_dma(reg_base, HAL_BTPCM_YES);
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}
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//hal_sys_timer_delay(2);
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btpcmip_pcm_clk_open_en(reg_base,1);
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return 0;
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}
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int hal_btpcm_send(enum HAL_BTPCM_ID_T id, uint8_t *value, uint32_t value_len)
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{
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uint32_t i = 0;
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uint32_t reg_base;
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reg_base = _btpcm_get_reg_base(id);
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for (i = 0; i < value_len; i += 4) {
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while (!(btpcmip_r_int_status(reg_base) & BTPCMIP_INT_STATUS_TX_FIFO_EMPTY_MASK));
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btpcmip_w_tx_fifo(reg_base, value[i+1]<<8 | value[i]);
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}
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return 0;
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}
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uint8_t hal_btpcm_recv(enum HAL_BTPCM_ID_T id, uint8_t *value, uint32_t value_len)
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{
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ASSERT(id < HAL_BTPCM_ID_NUM, invalid_id, id);
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return 0;
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}
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#endif
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