547 lines
16 KiB
C
547 lines
16 KiB
C
/**************************************************************************//**
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* @file cmsis_armcc.h
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* @brief CMSIS compiler specific macros, functions, instructions
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* @version V1.0.3
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* @date 15. May 2019
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __CMSIS_ARMCC_CA_H
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#define __CMSIS_ARMCC_CA_H
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
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#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
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#endif
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/* CMSIS compiler control architecture macros */
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#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
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#define __ARM_ARCH_7A__ 1
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#endif
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE __inline
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#endif
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#ifndef __FORCEINLINE
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#define __FORCEINLINE __forceinline
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static __inline
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#endif
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE static __forceinline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __declspec(noreturn)
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#endif
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#ifndef CMSIS_DEPRECATED
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#define CMSIS_DEPRECATED __attribute__((deprecated))
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT __packed struct
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __memory_changed()
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#endif
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/* ########################## Core Instruction Access ######################### */
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/**
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\brief No Operation
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*/
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#define __NOP __nop
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/**
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\brief Wait For Interrupt
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*/
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#define __WFI __wfi
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/**
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\brief Wait For Event
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*/
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#define __WFE __wfe
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/**
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\brief Send Event
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*/
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#define __SEV __sev
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/**
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\brief Instruction Synchronization Barrier
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*/
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#define __ISB() do {\
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__schedule_barrier();\
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__isb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Synchronization Barrier
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*/
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#define __DSB() do {\
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__schedule_barrier();\
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__dsb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Memory Barrier
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*/
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#define __DMB() do {\
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__schedule_barrier();\
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__dmb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV __rev
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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{
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rev16 r0, r0
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bx lr
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}
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#endif
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
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{
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revsh r0, r0
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bx lr
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}
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#endif
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/**
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\brief Rotate Right in unsigned value (32 bit)
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\param [in] op1 Value to rotate
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\param [in] op2 Number of Bits to rotate
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\return Rotated value
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*/
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#define __ROR __ror
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/**
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\brief Breakpoint
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __breakpoint(value)
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/**
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\brief Reverse bit order of value
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __RBIT __rbit
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/**
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\brief Count leading zeros
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ __clz
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/**
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\brief LDR Exclusive (8 bit)
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\details Executes a exclusive LDR instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
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#else
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#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
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#endif
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/**
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\brief LDR Exclusive (16 bit)
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\details Executes a exclusive LDR instruction for 16 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
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*/
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
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#else
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#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
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#endif
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/**
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\brief LDR Exclusive (32 bit)
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\details Executes a exclusive LDR instruction for 32 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint32_t at (*ptr)
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*/
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
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#else
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#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
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#endif
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/**
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\brief STR Exclusive (8 bit)
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\details Executes a exclusive STR instruction for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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#define __STREXB(value, ptr) __strex(value, ptr)
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#else
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#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
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#endif
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/**
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\brief STR Exclusive (16 bit)
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\details Executes a exclusive STR instruction for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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#define __STREXH(value, ptr) __strex(value, ptr)
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#else
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#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
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#endif
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/**
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\brief STR Exclusive (32 bit)
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\details Executes a exclusive STR instruction for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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#define __STREXW(value, ptr) __strex(value, ptr)
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#else
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#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
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#endif
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/**
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\brief Remove the exclusive lock
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\details Removes the exclusive lock which is created by LDREX.
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*/
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#define __CLREX __clrex
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/**
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\brief Signed Saturate
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\details Saturates a signed value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (1..32)
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\return Saturated value
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*/
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#define __SSAT __ssat
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/**
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\brief Unsigned Saturate
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\details Saturates an unsigned value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (0..31)
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\return Saturated value
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*/
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#define __USAT __usat
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/* ########################### Core Function Access ########################### */
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/**
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\brief Get FPSCR (Floating Point Status/Control)
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\return Floating Point Status/Control register value
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*/
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__STATIC_INLINE uint32_t __get_FPSCR(void)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#else
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return(0U);
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#endif
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}
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/**
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\brief Set FPSCR (Floating Point Status/Control)
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#else
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(void)fpscr;
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#endif
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}
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/** \brief Get CPSR (Current Program Status Register)
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\return CPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_CPSR(void)
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{
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register uint32_t __regCPSR __ASM("cpsr");
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return(__regCPSR);
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}
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/** \brief Set CPSR (Current Program Status Register)
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\param [in] cpsr CPSR value to set
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*/
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__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
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{
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register uint32_t __regCPSR __ASM("cpsr");
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__regCPSR = cpsr;
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}
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/** \brief Get Mode
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\return Processor Mode
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*/
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__STATIC_INLINE uint32_t __get_mode(void)
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{
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return (__get_CPSR() & 0x1FU);
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}
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/** \brief Set Mode
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\param [in] mode Mode value to set
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*/
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__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
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{
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MOV r1, lr
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MSR CPSR_C, r0
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BX r1
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}
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/** \brief Get Stack Pointer
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\return Stack Pointer
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*/
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__STATIC_INLINE __ASM uint32_t __get_SP(void)
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{
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MOV r0, sp
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BX lr
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}
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/** \brief Set Stack Pointer
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\param [in] stack Stack Pointer value to set
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*/
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__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
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{
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MOV sp, r0
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BX lr
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}
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/** \brief Get USR/SYS Stack Pointer
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\return USR/SYSStack Pointer
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*/
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__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
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{
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ARM
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PRESERVE8
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MRS R1, CPSR
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CPS #0x1F ;no effect in USR mode
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MOV R0, SP
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MSR CPSR_c, R1 ;no effect in USR mode
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ISB
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BX LR
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}
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/** \brief Set USR/SYS Stack Pointer
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
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{
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ARM
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PRESERVE8
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MRS R1, CPSR
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CPS #0x1F ;no effect in USR mode
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MOV SP, R0
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MSR CPSR_c, R1 ;no effect in USR mode
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ISB
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BX LR
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}
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/** \brief Get FPEXC (Floating Point Exception Control Register)
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\return Floating Point Exception Control Register value
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*/
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__STATIC_INLINE uint32_t __get_FPEXC(void)
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{
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#if (__FPU_PRESENT == 1)
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register uint32_t __regfpexc __ASM("fpexc");
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return(__regfpexc);
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#else
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return(0);
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#endif
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}
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/** \brief Set FPEXC (Floating Point Exception Control Register)
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\param [in] fpexc Floating Point Exception Control value to set
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*/
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__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
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{
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#if (__FPU_PRESENT == 1)
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register uint32_t __regfpexc __ASM("fpexc");
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__regfpexc = (fpexc);
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#endif
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}
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/*
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* Include common core functions to access Coprocessor 15 registers
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*/
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#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
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#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
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#define __get_CP64(cp, op1, Rt, CRm) \
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do { \
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uint32_t ltmp, htmp; \
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__ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
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(Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
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} while(0)
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#define __set_CP64(cp, op1, Rt, CRm) \
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do { \
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const uint64_t tmp = (Rt); \
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const uint32_t ltmp = (uint32_t)(tmp); \
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const uint32_t htmp = (uint32_t)(tmp >> 32U); \
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__ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
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} while(0)
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#include "ca/cmsis_cp15_ca.h"
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/** \brief Enable Floating Point Unit
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Critical section, called from undef handler, so systick is disabled
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*/
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__STATIC_INLINE __ASM void __FPU_Enable(void)
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{
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ARM
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//Permit access to VFP/NEON, registers by modifying CPACR
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MRC p15,0,R1,c1,c0,2
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ORR R1,R1,#0x00F00000
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MCR p15,0,R1,c1,c0,2
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//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
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ISB
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//Enable VFP/NEON
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VMRS R1,FPEXC
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ORR R1,R1,#0x40000000
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VMSR FPEXC,R1
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//Initialise VFP/NEON registers to 0
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MOV R2,#0
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//Initialise D16 registers to 0
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VMOV D0, R2,R2
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VMOV D1, R2,R2
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VMOV D2, R2,R2
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VMOV D3, R2,R2
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VMOV D4, R2,R2
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VMOV D5, R2,R2
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VMOV D6, R2,R2
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VMOV D7, R2,R2
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VMOV D8, R2,R2
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VMOV D9, R2,R2
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VMOV D10,R2,R2
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VMOV D11,R2,R2
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VMOV D12,R2,R2
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VMOV D13,R2,R2
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VMOV D14,R2,R2
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VMOV D15,R2,R2
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IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
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//Initialise D32 registers to 0
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VMOV D16,R2,R2
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VMOV D17,R2,R2
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VMOV D18,R2,R2
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VMOV D19,R2,R2
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|
VMOV D20,R2,R2
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|
VMOV D21,R2,R2
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VMOV D22,R2,R2
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VMOV D23,R2,R2
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VMOV D24,R2,R2
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|
VMOV D25,R2,R2
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VMOV D26,R2,R2
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|
VMOV D27,R2,R2
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|
VMOV D28,R2,R2
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|
VMOV D29,R2,R2
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|
VMOV D30,R2,R2
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|
VMOV D31,R2,R2
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|
ENDIF
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|
|
|
//Initialise FPSCR to a known state
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|
VMRS R1,FPSCR
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LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
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|
AND R1,R1,R2
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|
VMSR FPSCR,R1
|
|
|
|
BX LR
|
|
}
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|
|
|
#endif /* __CMSIS_ARMCC_CA_H */
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