441 lines
21 KiB
ArmAsm
441 lines
21 KiB
ArmAsm
;/*
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; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; *
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; * -----------------------------------------------------------------------------
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; *
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; * Project: CMSIS-RTOS RTX
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; * Title: Cortex-A Exception handlers
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; *
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; * -----------------------------------------------------------------------------
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; */
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NAME irq_ca.s
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MODE_FIQ EQU 0x11
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MODE_IRQ EQU 0x12
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MODE_SVC EQU 0x13
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MODE_ABT EQU 0x17
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MODE_UND EQU 0x1B
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CPSR_BIT_T EQU 0x20
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K_STATE_RUNNING EQU 2 ; osKernelState_t::osKernelRunning
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I_K_STATE_OFS EQU 8 ; osRtxInfo.kernel.state offset
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I_TICK_IRQN_OFS EQU 16 ; osRtxInfo.tick_irqn offset
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I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
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TCB_SP_FRAME EQU 34 ; osRtxThread_t.stack_frame offset
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TCB_SP_OFS EQU 56 ; osRtxThread_t.sp offset
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PRESERVE8
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SECTION .rodata:DATA:NOROOT(2)
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EXPORT irqRtxLib
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irqRtxLib DCB 0 ; Non weak library reference
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SECTION .data:DATA:NOROOT(2)
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EXPORT IRQ_PendSV
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IRQ_NestLevel DCD 0 ; IRQ nesting level counter
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IRQ_PendSV DCB 0 ; Pending SVC flag
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SECTION .text:CODE:NOROOT(2)
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Undef_Handler
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EXPORT Undef_Handler
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IMPORT CUndefHandler
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SRSFD SP!, #MODE_UND
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PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack
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MRS R0, SPSR
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TST R0, #CPSR_BIT_T ; Check mode
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MOVEQ R1, #4 ; R1 = 4 ARM mode
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MOVNE R1, #2 ; R1 = 2 Thumb mode
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SUB R0, LR, R1
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LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction
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BEQ Undef_Cont
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; Thumb instruction
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; Determine if it is a 32-bit Thumb instruction
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LDRH R0, [R0]
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MOV R2, #0x1C
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CMP R2, R0, LSR #11
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BHS Undef_Cont ; 16-bit Thumb instruction
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; 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction
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LDRH R2, [LR]
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ORR R0, R2, R0, LSL #16
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Undef_Cont
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MOV R2, LR ; Set LR to third argument
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AND R12, SP, #4 ; Ensure stack is 8-byte aligned
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SUB SP, SP, R12 ; Adjust stack
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PUSH {R12, LR} ; Store stack adjustment and dummy LR
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; R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)
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BL CUndefHandler
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POP {R12, LR} ; Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 ; Unadjust stack
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LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry
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SUB LR, LR, R0
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LDR R0, [SP, #28] ; Restore stacked SPSR
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MSR SPSR_CXSF, R0
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CLREX ; Clear exclusive monitor
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POP {R0-R4, R12} ; Restore stacked APCS registers
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ADD SP, SP, #8 ; Adjust SP for already-restored banked registers
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MOVS PC, LR
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PAbt_Handler
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EXPORT PAbt_Handler
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IMPORT CPAbtHandler
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SUB LR, LR, #4 ; Pre-adjust LR
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SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack
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PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
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MRC p15, 0, R0, c5, c0, 1 ; IFSR
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MRC p15, 0, R1, c6, c0, 2 ; IFAR
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MOV R2, LR ; Set LR to third argument
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AND R12, SP, #4 ; Ensure stack is 8-byte aligned
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SUB SP, SP, R12 ; Adjust stack
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PUSH {R12, LR} ; Store stack adjustment and dummy LR
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BL CPAbtHandler
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POP {R12, LR} ; Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 ; Unadjust stack
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CLREX ; Clear exclusive monitor
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POP {R0-R4, R12} ; Restore stack APCS registers
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RFEFD SP! ; Return from exception
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DAbt_Handler
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EXPORT DAbt_Handler
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IMPORT CDAbtHandler
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SUB LR, LR, #8 ; Pre-adjust LR
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SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack
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PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
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MRC p15, 0, R0, c5, c0, 0 ; DFSR
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MRC p15, 0, R1, c6, c0, 0 ; DFAR
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MOV R2, LR ; Set LR to third argument
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AND R12, SP, #4 ; Ensure stack is 8-byte aligned
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SUB SP, SP, R12 ; Adjust stack
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PUSH {R12, LR} ; Store stack adjustment and dummy LR
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BL CDAbtHandler
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POP {R12, LR} ; Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 ; Unadjust stack
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CLREX ; Clear exclusive monitor
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POP {R0-R4, R12} ; Restore stacked APCS registers
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RFEFD SP! ; Return from exception
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IRQ_Handler
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EXPORT IRQ_Handler
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IMPORT IRQ_GetActiveIRQ
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IMPORT IRQ_GetHandler
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IMPORT IRQ_EndOfInterrupt
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SUB LR, LR, #4 ; Pre-adjust LR
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SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
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CPS #MODE_SVC ; Change to SVC mode
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PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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ADD R1, R1, #1 ; Increment IRQ nesting level
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STR R1, [R0]
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MOV R3, SP ; Move SP into R3
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AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
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SUB SP, SP, R3 ; Adjust stack
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PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
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BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
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MOV R4, R0 ; Move interrupt ID to R4
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BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
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CMP R0, #0 ; Check if handler address is 0
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BEQ IRQ_End ; If 0, end interrupt and return
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CPSIE i ; Re-enable interrupts
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BLX R0 ; Call IRQ handler
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CPSID i ; Disable interrupts
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IRQ_End
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MOV R0, R4 ; Move interrupt ID to R0
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BLX IRQ_EndOfInterrupt ; Signal end of interrupt
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POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
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ADD SP, SP, R3 ; Unadjust stack
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BL osRtxContextSwitch ; Continue in context switcher
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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SUBS R1, R1, #1 ; Decrement IRQ nesting level
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STR R1, [R0]
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CLREX ; Clear exclusive monitor for interrupted code
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POP {R0-R3, R12, LR} ; Restore stacked APCS registers
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RFEFD SP! ; Return from IRQ handler
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SVC_Handler
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EXPORT SVC_Handler
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IMPORT IRQ_Disable
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IMPORT IRQ_Enable
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IMPORT osRtxUserSVC
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IMPORT osRtxInfo
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SRSFD SP!, #MODE_SVC ; Store SPSR_svc and LR_svc onto SVC stack
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PUSH {R12, LR}
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MRS R12, SPSR ; Load SPSR
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TST R12, #CPSR_BIT_T ; Thumb bit set?
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LDRHNE R12, [LR,#-2] ; Thumb: load halfword
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BICNE R12, R12, #0xFF00 ; extract SVC number
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LDREQ R12, [LR,#-4] ; ARM: load word
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BICEQ R12, R12, #0xFF000000 ; extract SVC number
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CMP R12, #0 ; Compare SVC number
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BNE SVC_User ; Branch if User SVC
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PUSH {R0-R3}
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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ADD R1, R1, #1 ; Increment IRQ nesting level
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STR R1, [R0]
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LDR R0, =osRtxInfo
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LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
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CMP R1, #K_STATE_RUNNING ; Check osKernelRunning
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BLT SVC_FuncCall ; Continue if kernel is not running
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LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
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BLX IRQ_Disable ; Disable OS Tick interrupt
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SVC_FuncCall
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POP {R0-R3}
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LDR R12, [SP] ; Reload R12 from stack
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CPSIE i ; Re-enable interrupts
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BLX R12 ; Branch to SVC function
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CPSID i ; Disable interrupts
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SUB SP, SP, #4
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STM SP, {SP}^ ; Store SP_usr onto stack
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POP {R12} ; Pop SP_usr into R12
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SUB R12, R12, #16 ; Adjust pointer to SP_usr
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LDMDB R12, {R2,R3} ; Load return values from SVC function
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PUSH {R0-R3} ; Push return values to stack
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LDR R0, =osRtxInfo
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LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
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CMP R1, #K_STATE_RUNNING ; Check osKernelRunning
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BLT SVC_ContextCheck ; Continue if kernel is not running
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LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
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BLX IRQ_Enable ; Enable OS Tick interrupt
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SVC_ContextCheck
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BL osRtxContextSwitch ; Continue in context switcher
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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SUB R1, R1, #1 ; Decrement IRQ nesting level
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STR R1, [R0]
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CLREX ; Clear exclusive monitor
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POP {R0-R3, R12, LR} ; Restore stacked APCS registers
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RFEFD SP! ; Return from exception
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SVC_User
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PUSH {R4, R5}
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LDR R5,=osRtxUserSVC ; Load address of SVC table
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LDR R4,[R5] ; Load SVC maximum number
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CMP R12,R4 ; Check SVC number range
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BHI SVC_Done ; Branch if out of range
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LDR R12,[R5,R12,LSL #2] ; Load SVC Function Address
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BLX R12 ; Call SVC Function
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SVC_Done
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CLREX ; Clear exclusive monitor
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POP {R4, R5, R12, LR}
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RFEFD SP! ; Return from exception
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osRtxContextSwitch
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EXPORT osRtxContextSwitch
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IMPORT osRtxPendSV_Handler
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IMPORT osRtxInfo
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IMPORT IRQ_Disable
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IMPORT IRQ_Enable
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PUSH {LR}
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; Check interrupt nesting level
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0] ; Load IRQ nest level
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CMP R1, #1
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BNE osRtxContextExit ; Nesting interrupts, exit context switcher
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LDR R12, =osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.run
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LDM R12, {R0, R1} ; Load osRtxInfo.thread.run: curr & next
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LDR R2, =IRQ_PendSV ; Load address of IRQ_PendSV flag
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LDRB R3, [R2] ; Load PendSV flag
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CMP R0, R1 ; Check if context switch is required
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BNE osRtxContextCheck ; Not equal, check if context save required
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CMP R3, #1 ; Compare IRQ_PendSV value
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BNE osRtxContextExit ; No post processing (and no context switch requested)
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osRtxContextCheck
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STR R1, [R12] ; Store run.next as run.curr
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; R0 = curr, R1 = next, R2 = &IRQ_PendSV, R3 = IRQ_PendSV, R12 = &osRtxInfo.thread.run
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PUSH {R1-R3, R12}
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CMP R0, #0 ; Is osRtxInfo.thread.run.curr == 0
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BEQ osRtxPostProcess ; Current deleted, skip context save
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osRtxContextSave
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MOV LR, R0 ; Move &osRtxInfo.thread.run.curr to LR
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MOV R0, SP ; Move SP_svc into R0
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ADD R0, R0, #20 ; Adjust SP_svc to R0 of the basic frame
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SUB SP, SP, #4
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STM SP, {SP}^ ; Save SP_usr to current stack
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POP {R1} ; Pop SP_usr into R1
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SUB R1, R1, #64 ; Adjust SP_usr to R4 of the basic frame
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STMIA R1!, {R4-R11} ; Save R4-R11 to user stack
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LDMIA R0!, {R4-R8} ; Load stacked R0-R3,R12 into R4-R8
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STMIA R1!, {R4-R8} ; Store them to user stack
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STM R1, {LR}^ ; Store LR_usr directly
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ADD R1, R1, #4 ; Adjust user sp to PC
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LDMIB R0!, {R5-R6} ; Load current PC, CPSR
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STMIA R1!, {R5-R6} ; Restore user PC and CPSR
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SUB R1, R1, #64 ; Adjust SP_usr to stacked R4
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; Check if VFP state need to be saved
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MRC p15, 0, R2, c1, c0, 2 ; VFP/NEON access enabled? (CPACR)
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AND R2, R2, #0x00F00000
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CMP R2, #0x00F00000
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BNE osRtxContextSave1 ; Continue, no VFP
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VMRS R2, FPSCR
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STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment
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VSTMDB R1!, {D0-D15} ; Save D0-D15
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#ifdef __ARM_ADVANCED_SIMD__
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VSTMDB R1!, {D16-D31} ; Save D16-D31
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#endif
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LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info
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#ifdef __ARM_ADVANCED_SIMD__
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ORR R2, R2, #4 ; NEON state
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#else
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ORR R2, R2, #2 ; VFP state
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#endif
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STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state
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osRtxContextSave1
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STR R1, [LR, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr
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osRtxPostProcess
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; RTX IRQ post processing check
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POP {R8-R11} ; Pop R8 = run.next, R9 = &IRQ_PendSV, R10 = IRQ_PendSV, R11 = &osRtxInfo.thread.run
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CMP R10, #1 ; Compare PendSV value
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BNE osRtxContextRestore ; Skip post processing if not pending
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MOV R4, SP ; Move SP_svc into R4
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AND R4, R4, #4 ; Get stack adjustment to ensure 8-byte alignment
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SUB SP, SP, R4 ; Adjust stack
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; Disable OS Tick
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LDR R5, =osRtxInfo ; Load address of osRtxInfo
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LDR R5, [R5, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
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MOV R0, R5 ; Set it as function parameter
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BLX IRQ_Disable ; Disable OS Tick interrupt
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MOV R6, #0 ; Set PendSV clear value
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B osRtxPendCheck
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osRtxPendExec
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STRB R6, [R9] ; Clear PendSV flag
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CPSIE i ; Re-enable interrupts
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BLX osRtxPendSV_Handler ; Post process pending objects
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CPSID i ; Disable interrupts
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osRtxPendCheck
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LDR R8, [R11, #4] ; Load osRtxInfo.thread.run.next
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STR R8, [R11] ; Store run.next as run.curr
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LDRB R0, [R9] ; Load PendSV flag
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CMP R0, #1 ; Compare PendSV value
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BEQ osRtxPendExec ; Branch to PendExec if PendSV is set
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; Re-enable OS Tick
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MOV R0, R5 ; Restore irqn as function parameter
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BLX IRQ_Enable ; Enable OS Tick interrupt
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ADD SP, SP, R4 ; Restore stack adjustment
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osRtxContextRestore
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LDR LR, [R8, #TCB_SP_OFS] ; Load next osRtxThread_t.sp
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LDRB R2, [R8, #TCB_SP_FRAME] ; Load next osRtxThread_t.stack_frame
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ANDS R2, R2, #0x6 ; Check stack frame for VFP context
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MRC p15, 0, R2, c1, c0, 2 ; Read CPACR
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ANDEQ R2, R2, #0xFF0FFFFF ; VFP/NEON state not stacked, disable VFP/NEON
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ORRNE R2, R2, #0x00F00000 ; VFP/NEON state is stacked, enable VFP/NEON
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MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
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BEQ osRtxContextRestore1 ; No VFP
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ISB ; Sync if VFP was enabled
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#ifdef __ARM_ADVANCED_SIMD__
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VLDMIA LR!, {D16-D31} ; Restore D16-D31
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#endif
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VLDMIA LR!, {D0-D15} ; Restore D0-D15
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LDR R2, [LR]
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VMSR FPSCR, R2 ; Restore FPSCR
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ADD LR, LR, #8 ; Adjust sp pointer to R4
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osRtxContextRestore1
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LDMIA LR!, {R4-R11} ; Restore R4-R11
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ADD R12, LR, #32 ; Adjust sp and save it into R12
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PUSH {R12} ; Push sp onto stack
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LDM SP, {SP}^ ; Restore SP_usr directly
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ADD SP, SP, #4 ; Adjust SP_svc
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LDMIA LR!, {R0-R3, R12} ; Load user registers R0-R3,R12
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STMIB SP!, {R0-R3, R12} ; Store them to SP_svc
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LDM LR, {LR}^ ; Restore LR_usr directly
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LDMIB LR!, {R0-R1} ; Load user registers PC,CPSR
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ADD SP, SP, #4
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STMIB SP!, {R0-R1} ; Store them to SP_svc
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SUB SP, SP, #32 ; Adjust SP_svc to stacked LR
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osRtxContextExit
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POP {PC} ; Return
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END
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