180 lines
3.3 KiB
ArmAsm
180 lines
3.3 KiB
ArmAsm
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_addr_map.h"
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#ifdef NOSTD
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#define HEAP_SECTION_SIZE 0
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#else
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#define HEAP_SECTION_SIZE 0x40
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#endif
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#define STACK_SECTION_SIZE 0x1000
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#define CP_STACK_SECTION_SIZE 0x1000
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LR_rom ROM_BASE NOCOMPRESS
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{
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rom_vectors +0
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{
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*(.vectors, +FIRST)
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}
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rom_text +0 FIXED
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{
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*(.text*)
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#ifndef NOSTD
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*(InRoot$$Sections)
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*armlib*(+TEXT)
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*armlib*(+CONST)
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#endif
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*(.rodata*)
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}
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#ifdef CHIP_HAS_AUDIO_CONST_ROM
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rom_audio_const +0
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{
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*audio_const_rom.o(.audio_const_index)
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*audio_const_rom.o(.rodata*)
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}
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#endif
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rom_build_id +0
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{
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#ifndef NOSTD
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*(.eh_frame*)
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#endif
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*(.note.gnu.build-id)
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}
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rom_got_info +0
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{
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*(.got)
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*(.got.plt)
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*(.igot.plt)
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*(.dynamic)
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}
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.ARM.extab +0
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{
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*(.ARM.extab*, .gnu.linkonce.armextab.*)
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}
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.ARM.exidx +0
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{
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*(.ARM.exidx*, .gnu.linkonce.armexidx.*)
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}
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rom_text0_end +0 EMPTY 0
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{
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}
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vector_table RAM_BASE UNINIT VECTOR_SECTION_SIZE
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{
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*(.bss.vector_table, +FIRST)
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}
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reboot_param (ImageBase(vector_table) + VECTOR_SECTION_SIZE) UNINIT REBOOT_PARAM_SECTION_SIZE
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{
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*(.bss.reboot_param, +FIRST)
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}
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rom_ramx RAM_TO_RAMX(ImageBase(reboot_param) + REBOOT_PARAM_SECTION_SIZE)
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{
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*(.rom_ramx)
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}
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rom_data RAMX_TO_RAM(+0)
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{
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*(.data*)
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#ifndef NOSTD
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*armlib*(+DATA)
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#endif
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}
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rom_bss +0 UNINIT
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{
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*(.bss*)
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*(COMMON)
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#ifndef NOSTD
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*armlib*(+BSS)
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#endif
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}
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ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SECTION_SIZE
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{
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}
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scratch_buf +0 UNINIT
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{
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*(.bss.scratch_buf)
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}
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ARM_LIB_STACK (RAM_BASE + RAM_SIZE - STACK_SECTION_SIZE) ALIGN 8 EMPTY STACK_SECTION_SIZE
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{
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}
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/* Check if data + heap + stack exceeds RAM limit */
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ScatterAssert(ImageBase(ARM_LIB_STACK) >= ImageLimit(ARM_LIB_HEAP))
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ScatterAssert(ImageLimit(ARM_LIB_STACK) <= (RAM_BASE + RAM_SIZE))
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free_ram ImageLimit(scratch_buf) EMPTY (ImageBase(ARM_LIB_STACK) - ImageLimit(scratch_buf))
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{
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}
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#if defined(CHIP_HAS_CP) && (RAMCP_SIZE > 0)
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cp_ramx_last_dummy RAMCPX_BASE EMPTY 0
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{
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}
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cp_ram_last_dummy RAMCP_BASE EMPTY 0
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{
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}
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cp_stack (RAMCP_BASE + RAMCP_SIZE - CP_STACK_SECTION_SIZE) EMPTY CP_STACK_SECTION_SIZE
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{
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}
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ScatterAssert(ImageBase(cp_stack) >= ImageLimit(cp_ram_last_dummy))
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ScatterAssert(ImageLimit(cp_stack) <= RAMCP_BASE + RAMCP_SIZE)
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#endif
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}
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LR_build_info +0
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{
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lr_build_info_start +0 FIXED EMPTY 0
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{
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}
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rom_export_fn (ROM_BASE + ROM_SIZE - ROM_BUILD_INFO_SECTION_SIZE - ROM_EXPORT_FN_SECTION_SIZE) FIXED
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{
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*(.export_fn)
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}
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rom_build_info (ROM_BASE + ROM_SIZE - ROM_BUILD_INFO_SECTION_SIZE) FIXED
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{
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*(.build_info, +FIRST)
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}
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free_rom ImageLimit(lr_build_info_start) EMPTY (ImageBase(rom_export_fn) - ImageLimit(lr_build_info_start))
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{
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}
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ScatterAssert(LoadLimit(rom_build_info) <= (ROM_BASE + ROM_SIZE))
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}
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