261 lines
7.7 KiB
C
261 lines
7.7 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __HAL_SPDIFIP_H__
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#define __HAL_SPDIFIP_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "plat_types.h"
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#include "reg_spdifip.h"
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#define spdifip_read32(b,a) \
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(*(volatile uint32_t *)(b+a))
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#define spdifip_write32(v,b,a) \
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((*(volatile uint32_t *)(b+a)) = v)
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static inline void spdifip_w_enable_spdifip(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_ENABLE_REG_REG_OFFSET);
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if (v)
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val |= SPDIFIP_ENABLE_REG_SPDIF_ENABLE_MASK;
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else
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val &= ~SPDIFIP_ENABLE_REG_SPDIF_ENABLE_MASK;
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spdifip_write32(val, reg_base, SPDIFIP_ENABLE_REG_REG_OFFSET);
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}
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#if 0
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static inline void spdifip_w_enable_clk_gen(uint32_t reg_base, uint32_t v)
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{
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if (v)
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spdifip_write32(1, reg_base, SPDIFIP_CLK_GEN_ENABLE_REG_REG_OFFSET);
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else
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spdifip_write32(0, reg_base, SPDIFIP_CLK_GEN_ENABLE_REG_REG_OFFSET);
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}
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#endif
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#if 0
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static inline void spdifip_w_enable_rx_block(uint32_t reg_base, uint32_t v)
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{
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if (v)
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spdifip_write32(1, reg_base, SPDIFIP_RX_BLOCK_ENABLE_REG_REG_OFFSET);
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else
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spdifip_write32(0, reg_base, SPDIFIP_RX_BLOCK_ENABLE_REG_REG_OFFSET);
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}
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#endif
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static inline void spdifip_w_sample_en(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_RX_CFG_REG_OFFSET);
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if (v)
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val |= SPDIFIP_RX_CFG_SAMPLEEN_MASK;
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else
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val &= ~SPDIFIP_RX_CFG_SAMPLEEN_MASK;
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spdifip_write32(val, reg_base, SPDIFIP_RX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_enable_rx(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_RX_CFG_REG_OFFSET);
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if (v)
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val |= SPDIFIP_RX_CFG_RXEN_MASK;
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else
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val &= ~SPDIFIP_RX_CFG_RXEN_MASK;
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spdifip_write32(val, reg_base, SPDIFIP_RX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_rx_format_cfg_reg(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_RX_CFG_REG_OFFSET);
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val &= ~SPDIFIP_RX_CFG_FORMAT_MASK;
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val |= v<<SPDIFIP_RX_CFG_FORMAT_SHIFT;
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spdifip_write32(val, reg_base, SPDIFIP_RX_CFG_REG_OFFSET);
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}
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#if 1
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static inline void spdifip_w_enable_rx_channel0(uint32_t reg_base, uint32_t v)
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{
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if (v)
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spdifip_write32(1, reg_base, SPDIFIP_RX_ENABLE_REG_OFFSET);
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else
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spdifip_write32(0, reg_base, SPDIFIP_RX_ENABLE_REG_OFFSET);
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}
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#endif
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#if 0
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static inline void spdifip_w_enable_tx_block(uint32_t reg_base, uint32_t v)
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{
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if (v)
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spdifip_write32(1, reg_base, SPDIFIP_TX_BLOCK_ENABLE_REG_REG_OFFSET);
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else
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spdifip_write32(0, reg_base, SPDIFIP_TX_BLOCK_ENABLE_REG_REG_OFFSET);
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}
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#endif
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static inline void spdifip_w_enable_tx(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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if (v)
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val |= SPDIFIP_TX_CFG_TXEN_MASK;
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else
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val &= ~SPDIFIP_TX_CFG_TXEN_MASK;
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spdifip_write32(val, reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_tx_valid(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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if (v)
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val |= SPDIFIP_TX_CFG_TXVALID_MASK;
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else
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val &= ~SPDIFIP_TX_CFG_TXVALID_MASK;
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spdifip_write32(val, reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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}
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#if 1
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static inline void spdifip_w_tx_ratio(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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val &= ~SPDIFIP_TX_CFG_RATIO_MASK;
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val |= v<<SPDIFIP_TX_CFG_RATIO_SHIFT;;
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spdifip_write32(val, reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_tx_chnst_en(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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val &= ~SPDIFIP_TX_CFG_CHSTEN_MASK;
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val |= v<<SPDIFIP_TX_CFG_CHSTEN_SHIFT;;
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spdifip_write32(val, reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_tx_userdata_en(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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val &= ~SPDIFIP_TX_CFG_USRDATAEN_MASK;
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val |= v<<SPDIFIP_TX_CFG_USRDATAEN_SHIFT;;
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spdifip_write32(val, reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_tx_format_cfg_reg(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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val &= ~SPDIFIP_TX_CFG_FORMAT_MASK;
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val |= v<<SPDIFIP_TX_CFG_FORMAT_SHIFT;;
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spdifip_write32(val, reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_enable_tx_channel0(uint32_t reg_base, uint32_t v)
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{
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if (v)
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spdifip_write32(1, reg_base, SPDIFIP_TX_ENABLE_REG_OFFSET);
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else
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spdifip_write32(0, reg_base, SPDIFIP_TX_ENABLE_REG_OFFSET);
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}
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#endif
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#if 0
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static inline void spdifip_w_tx_resolution(uint32_t reg_base, uint32_t v)
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{
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spdifip_write32(v<<SPDIFIP_TX_CFG_WLEN_SHIFT, reg_base, SPDIFIP_TX_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_rx_resolution(uint32_t reg_base, uint32_t v)
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{
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spdifip_write32(v<<SPDIFIP_RX_CFG_WLEN_SHIFT, reg_base, SPDIFIP_RX_CFG_REG_OFFSET);
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}
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#endif
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static inline void spdifip_w_clk_cfg_reg(uint32_t reg_base, uint32_t v)
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{
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spdifip_write32(v, reg_base, SPDIFIP_CLK_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_tx_left_fifo(uint32_t reg_base, uint32_t v)
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{
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spdifip_write32(v, reg_base, SPDIFIP_LEFT_TX_BUFF_REG_OFFSET);
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}
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static inline void spdifip_w_tx_right_fifo(uint32_t reg_base, uint32_t v)
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{
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spdifip_write32(v, reg_base, SPDIFIP_RIGHT_TX_BUFF_REG_OFFSET);
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}
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static inline void spdifip_w_tx_fifo_threshold(uint32_t reg_base, uint32_t v)
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{
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spdifip_write32(v<<SPDIFIP_TX_FIFO_CFG_LEVEL_SHIFT, reg_base, SPDIFIP_TX_FIFO_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_rx_fifo_threshold(uint32_t reg_base, uint32_t v)
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{
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spdifip_write32(v<<SPDIFIP_RX_FIFO_CFG_LEVEL_SHIFT, reg_base, SPDIFIP_RX_FIFO_CFG_REG_OFFSET);
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}
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static inline void spdifip_w_tx_fifo_reset(uint32_t reg_base)
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{
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spdifip_write32(SPDIFIP_TX_FIFO_FLUSH_MASK, reg_base, SPDIFIP_TX_FIFO_FLUSH_REG_OFFSET);
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}
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static inline void spdifip_w_rx_fifo_reset(uint32_t reg_base)
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{
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spdifip_write32(SPDIFIP_RX_FIFO_FLUSH_MASK, reg_base, SPDIFIP_RX_FIFO_FLUSH_REG_OFFSET);
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}
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static inline uint32_t spdifip_r_int_status(uint32_t reg_base)
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{
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return spdifip_read32(reg_base, SPDIFIP_INT_STATUS_REG_OFFSET);
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}
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static inline void spdifip_w_enable_tx_dma(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_DMA_CTRL_REG_OFFSET);
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if (v)
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val |= SPDIFIP_DMA_CTRL_TX_ENABLE_MASK;
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else
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val &= ~SPDIFIP_DMA_CTRL_TX_ENABLE_MASK;
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spdifip_write32(val, reg_base, SPDIFIP_DMA_CTRL_REG_OFFSET);
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}
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static inline void spdifip_w_enable_rx_dma(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = spdifip_read32(reg_base, SPDIFIP_DMA_CTRL_REG_OFFSET);
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if (v)
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val |= SPDIFIP_DMA_CTRL_RX_ENABLE_MASK;
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else
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val &= ~SPDIFIP_DMA_CTRL_RX_ENABLE_MASK;
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spdifip_write32(val, reg_base, SPDIFIP_DMA_CTRL_REG_OFFSET);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HAL_SPDIFIP_H__ */
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