589 lines
16 KiB
C
589 lines
16 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifdef CHIP_HAS_PSRAMUHS
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#include "hal_psramuhs.h"
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#include "hal_cache.h"
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#include "hal_location.h"
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#include "hal_timer.h"
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#include "hal_trace.h"
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#include "plat_addr_map.h"
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#include "plat_types.h"
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#include "pmu.h"
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#include "psramuhsphy.h"
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#include "reg_psramuhs_mc.h"
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// #define PSRAMUHS_DUAL_8BIT
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// #define PSRAMUHS_BURST_REFRESH
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// #define PSRAMUHS_DUMMY_CYCLE
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// #define PSRAMUHS_PRA_ENABLE
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// #define PSRAMUHS_DUAL_SWITCH
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// #define PSRAMUHS_DIG_LOOPBACK
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// #define PSRAMUHS_ANA_LOOPBACK
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// #define PSRAMUHS_AUTO_PRECHARGE
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// #define PSRAMUHS_WRAP_ENABLE
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#if defined(CHIP_BEST2001) && !defined(PSRAMUHS_DUMMY_CYCLE)
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#define PSRAMUHS_DUMMY_CYCLE
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#endif
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#define TX_FIFO_DEPTH 4
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#define RX_FIFO_DEPTH 4
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enum CP_FSM_STATE_T {
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CP_FSM_STATE_SELF_REFRESH = 1,
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CP_FSM_STATE_PD = 2,
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CP_FSM_STATE_READY = 4,
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};
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enum MEMIF_CMD_T {
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MEMIF_NO_CMD = 0x00,
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MEMIF_WRITE = 0x01,
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MEMIF_READ = 0x02,
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MEMIF_MRS = 0x05,
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MEMIF_MRR = 0x06,
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MEMIF_REF = 0x08,
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MEMIF_SREF = 0x09,
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MEMIF_PD = 0x10,
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MEMIF_NOP = 0x20,
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MEMIF_RST = 0xFF,
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MEMIF_ZQCL = 0x85,
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MEMIF_ZQCS = 0x45,
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MEMIF_ZQCRST = 0x25,
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MEMIF_START_CLOCK = 0x40,
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MEMIF_STOP_CLOCK = 0x80,
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MEMIF_NEW_CMD = 0x7F,
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};
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static struct PSRAMUHS_MC_T *const psramuhs_mc =
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(struct PSRAMUHS_MC_T *)PSRAMUHS_CTRL_BASE;
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#if (PSRAMUHS_SPEED != 0)
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static const uint32_t psramuhs_run_clk = PSRAMUHS_SPEED * 1000 * 1000;
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#else
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#error "invalid PSRAMUHS_SPEED"
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#endif
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static int hal_psramuhsip_mc_busy(void) {
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return !!(psramuhs_mc->REG_404 & PSRAM_UHS_MC_BUSY);
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}
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static int hal_psramuhsip_wb_busy(void) {
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return !!(psramuhs_mc->REG_404 & PSRAM_UHS_MC_WB_FILL_LEVEL_MASK);
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}
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int hal_psramuhsip_mc_in_sleep(void) {
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return GET_BITFIELD(psramuhs_mc->REG_404, PSRAM_UHS_MC_CP_FSM_STATE) ==
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CP_FSM_STATE_PD;
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}
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int hal_psramuhsip_rx_fifo_empty(void) {
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return !!(psramuhs_mc->REG_404 & PSRAM_UHS_MC_MGR_RXFIFO_R_EMPTY);
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}
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int hal_psramuhsip_tx_fifo_full(void) {
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return !!(psramuhs_mc->REG_404 & PSRAM_UHS_MC_MGR_TXFIFO_W_FULL);
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}
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uint32_t hal_psramuhsip_get_rx_fifo_len(void) {
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return GET_BITFIELD(psramuhs_mc->REG_404, PSRAM_UHS_MC_MGR_RXFIFO_FULL_CNT);
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}
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uint32_t hal_psramuhsip_get_tx_fifo_free_len(void) {
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return GET_BITFIELD(psramuhs_mc->REG_404, PSRAM_UHS_MC_MGR_TXFIFO_EMPTY_CNT);
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}
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void hal_psramuhsip_mc_busy_wait(void) {
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while (hal_psramuhsip_mc_busy())
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;
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}
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void hal_psramuhsip_wb_busy_wait(void) {
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while (hal_psramuhsip_wb_busy())
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;
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}
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void hal_psramuhsip_flush_tx_fifo(void) {
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hal_psramuhsip_mc_busy_wait();
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psramuhs_mc->REG_01C = PSRAM_UHS_MC_MGR_TX_FIFO_CLR;
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hal_psramuhsip_mc_busy_wait();
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}
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void hal_psramuhsip_flush_rx_fifo(void) {
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hal_psramuhsip_mc_busy_wait();
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psramuhs_mc->REG_01C = PSRAM_UHS_MC_MGR_RX_FIFO_CLR;
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hal_psramuhsip_mc_busy_wait();
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}
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void hal_psramuhsip_flush_all_fifo(void) {
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hal_psramuhsip_mc_busy_wait();
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psramuhs_mc->REG_01C =
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PSRAM_UHS_MC_MGR_TX_FIFO_CLR | PSRAM_UHS_MC_MGR_RX_FIFO_CLR;
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hal_psramuhsip_mc_busy_wait();
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}
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void hal_psramuhsip_xfer_addr_len(uint32_t addr, uint32_t len) {
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psramuhs_mc->REG_008 = addr;
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psramuhs_mc->REG_00C = len;
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}
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void hal_psramuhsip_write_fifo(uint32_t *data, uint32_t len) {
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for (int i = 0; i < len; i++) {
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psramuhs_mc->REG_014 = *data++;
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}
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}
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void hal_psramuhsip_read_fifo(uint32_t *data, uint32_t len) {
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for (int i = 0; i < len; i++) {
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*data++ = psramuhs_mc->REG_018;
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}
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}
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void hal_psramuhsip_set_reg_data_mask(void) {
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#ifdef PSRAMUHS_DUAL_8BIT
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psramuhs_mc->REG_010 = 0xFFFC;
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#else
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psramuhs_mc->REG_010 = 0xFFFE;
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#endif
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}
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void hal_psramuhsip_set_mem_data_mask(void) { psramuhs_mc->REG_010 = 0; }
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void hal_psramuhsip_set_reg_fifo_width(void) { psramuhs_mc->REG_0B0 = 0; }
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void hal_psramuhsip_set_mem_fifo_width(void) {
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// 128 bits if PSRAMUHS_DUAL_8BIT; 64 bits otherwise
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psramuhs_mc->REG_0B0 = PSRAM_UHS_MC_MGR_FIFO_TEST_EN;
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}
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void hal_psramuhsip_set_cmd(enum MEMIF_CMD_T cmd) {
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psramuhs_mc->REG_004 = cmd;
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}
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POSSIBLY_UNUSED void psramuhs_read_reg(uint32_t reg, uint32_t *val) {
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hal_psramuhsip_flush_all_fifo();
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hal_psramuhsip_xfer_addr_len(reg, 1);
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hal_psramuhsip_set_cmd(MEMIF_MRR);
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while (hal_psramuhsip_rx_fifo_empty())
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;
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hal_psramuhsip_read_fifo(val, 1);
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}
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static void psramuhs_send_cmd_reg(enum MEMIF_CMD_T cmd, uint32_t reg,
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uint32_t val) {
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#if !defined(PSRAMUHS_DIG_LOOPBACK) && !defined(PSRAMUHS_ANA_LOOPBACK)
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#ifdef PSRAMUHS_DUAL_8BIT
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val &= 0xFF;
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val |= (val << 8);
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#endif
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hal_psramuhsip_flush_all_fifo();
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// hal_psramuhsip_set_reg_fifo_width();
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// hal_psramuhsip_set_reg_data_mask();
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hal_psramuhsip_write_fifo(&val, 1);
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hal_psramuhsip_xfer_addr_len(reg, 1);
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hal_psramuhsip_set_cmd(cmd);
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while (hal_psramuhsip_get_tx_fifo_free_len() != TX_FIFO_DEPTH)
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;
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hal_psramuhsip_mc_busy_wait();
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// hal_psramuhsip_set_mem_fifo_width();
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// hal_psramuhsip_set_mem_data_mask();
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#endif
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}
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static void psramuhs_write_reg(uint32_t reg, uint32_t val) {
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psramuhs_send_cmd_reg(MEMIF_MRS, reg, val);
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}
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static void psramuhs_single_cmd(enum MEMIF_CMD_T cmd) {
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#if !defined(PSRAMUHS_DIG_LOOPBACK) && !defined(PSRAMUHS_ANA_LOOPBACK)
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hal_psramuhsip_flush_all_fifo();
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hal_psramuhsip_set_cmd(cmd);
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hal_psramuhsip_mc_busy_wait();
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#endif
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}
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static POSSIBLY_UNUSED void psramuhs_start_clock(void) {
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psramuhs_single_cmd(MEMIF_START_CLOCK);
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}
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static POSSIBLY_UNUSED void psramuhs_stop_clock(void) {
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psramuhs_single_cmd(MEMIF_STOP_CLOCK);
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}
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static POSSIBLY_UNUSED void psramuhs_reset(void) {
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psramuhs_single_cmd(MEMIF_RST);
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}
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static POSSIBLY_UNUSED void psramuhs_zq_calib_reset(void) {
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psramuhs_send_cmd_reg(MEMIF_ZQCRST, 7, 0);
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}
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static POSSIBLY_UNUSED void psramuhs_zq_calib(void) {
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psramuhs_send_cmd_reg(MEMIF_ZQCL, 5, 0);
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}
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static void psramuhs_set_timing(uint32_t clk) {
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uint32_t reg;
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uint32_t val;
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uint32_t burst_len;
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reg = 0;
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if (clk <= 200000000) {
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val = 7;
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} else if (clk <= 333000000) {
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val = 6;
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} else if (clk <= 400000000) {
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val = 5;
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} else if (clk <= 533000000) {
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val = 4;
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} else if (clk <= 667000000) {
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val = 0;
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} else if (clk <= 800000000) {
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val = 1;
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} else if (clk <= 933000000) {
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val = 2;
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} else {
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val = 3;
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}
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// Latency, drive
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val = (val << 0) | (2 << 3);
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#if 0
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//refresh disable
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val |= (1 << 7);
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#endif
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psramuhs_write_reg(reg, val);
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reg = 2;
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#if defined(__ARM_ARCH_ISA_ARM) || defined(DSP_ENABLE)
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#ifdef PSRAMUHS_DUAL_8BIT
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burst_len = 0x1; // 32B
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#else
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burst_len = 0x2; // 64B
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#endif
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#else
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#ifdef PSRAMUHS_DUAL_8BIT
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burst_len = 0x0; // 16B
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#else
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burst_len = 0x1; // 32B
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#endif
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#endif
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#ifdef PSRAMUHS_PRA_ENABLE
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// Burst len, pra enable
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val = (burst_len << 0) | (1 << 4);
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#else
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// Burst len, auto-precharge
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#ifdef PSRAMUHS_AUTO_PRECHARGE
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val = (burst_len << 0) | (1 << 3);
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#else
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val = (burst_len << 0);
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#endif
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#endif
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// wrap enable
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#ifdef PSRAMUHS_WRAP_ENABLE
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val |= (1 << 2);
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#endif
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psramuhs_write_reg(reg, val);
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reg = 6;
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// Vref trim
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val = (8 << 0);
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psramuhs_write_reg(reg, val);
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hal_sys_timer_delay_us(5);
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psramuhs_zq_calib_reset();
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psramuhs_zq_calib();
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}
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void hal_psramuhs_sleep(void) {}
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void hal_psramuhs_wakeup(void) {}
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static void hal_psramuhs_mc_set_timing(uint32_t clk) {
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uint32_t val1, val2;
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uint32_t val;
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if (clk <= 200000000) {
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val1 = 9;
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val2 = 5;
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} else if (clk <= 333000000) {
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val1 = 13;
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val2 = 5;
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} else if (clk <= 400000000) {
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val1 = 16;
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val2 = 6;
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} else if (clk <= 533000000) {
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val1 = 20;
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val2 = 10;
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} else if (clk <= 667000000) {
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val1 = 24;
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val2 = 12;
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} else if (clk <= 800000000) {
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val1 = 29;
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val2 = 14;
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} else if (clk <= 933000000) {
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val1 = 33;
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val2 = 16;
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} else {
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val1 = 37;
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val2 = 18;
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}
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if (clk >= 466000000)
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val2--;
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psramuhs_mc->REG_028 = PSRAM_UHS_MC_WRITE_LATENCY(val2);
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psramuhs_mc->REG_02C = PSRAM_UHS_MC_READ_LATENCY(val1);
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// tCEM_MAX <= 7.8 us when MRW2[5]==1 && MRR4[2]==0, or <= 3.9 us when
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// MRW2[5]==0 || MRR4[2]==1
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val = (clk / 1000000) * 30 / 10 - 1;
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psramuhs_mc->REG_04C =
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PSRAM_UHS_MC_T_REFI(val) | PSRAM_UHS_MC_NUM_OF_BURST_RFS(0x1000);
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// tRC >= 60 ns
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val = ((clk / 1000000) * 60 + (1000 - 1)) / 1000;
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psramuhs_mc->REG_050 = PSRAM_UHS_MC_T_RC(val);
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// tRFC >= 60 ns
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val = ((clk / 1000000) * 60 + (1000 - 1)) / 1000;
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psramuhs_mc->REG_054 = PSRAM_UHS_MC_T_RFC(val);
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#ifdef PSRAMUHS_AUTO_PRECHARGE
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// tCPHR >= 5 ns (auto precharge)
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#if PSRAMUHS_SPEED >= 900
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val = ((clk / 1000000) * 5 + (1000 - 1)) / 1000;
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#else /*PSRAMUHS_SPEED == 1000*/
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val = 20;
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#endif /*PSRAMUHS_SPEED == 1000*/
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psramuhs_mc->REG_05C = PSRAM_UHS_MC_T_CPHR_AP(val);
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// tCPHW >= 30 ns (auto precharge)
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#if PSRAMUHS_SPEED >= 900
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val = ((clk / 1000000) * 30 + (1000 - 1)) / 1000;
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#else /*PSRAMUHS_SPEED == 1000*/
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val = 100;
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#endif /*PSRAMUHS_SPEED == 1000*/
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psramuhs_mc->REG_064 = PSRAM_UHS_MC_T_CPHW_AP(val);
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#else /*PSRAMUHS_AUTO_PRECHARGE*/
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// tCPHR >= 20 ns (no auto precharge)
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#if PSRAMUHS_SPEED >= 900
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val = ((clk / 1000000) * 20 + (1000 - 1)) / 1000;
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#else /*PSRAMUHS_SPEED == 1000*/
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val = 20;
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#endif /*PSRAMUHS_SPEED == 1000*/
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psramuhs_mc->REG_058 = PSRAM_UHS_MC_T_CPHR(val);
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// tCPHW >= 30 ns (no auto precharge)
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#if PSRAMUHS_SPEED >= 900
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val = ((clk / 1000000) * 30 + (1000 - 1)) / 1000;
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#else /*PSRAMUHS_SPEED == 1000*/
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val = 100;
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#endif /*PSRAMUHS_SPEED == 1000*/
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psramuhs_mc->REG_060 = PSRAM_UHS_MC_T_CPHW(val);
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#endif /*PSRAMUHS_AUTO_PRECHARGE*/
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// tMRR >= 20ns
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val = 20; //((clk / 1000000) * 20 + (1000 - 1)) / 1000;
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psramuhs_mc->REG_068 = PSRAM_UHS_MC_T_MRR(val);
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// tMRW >= 100 ns
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val = ((clk / 1000000) * 100 + (1000 - 1)) / 1000;
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psramuhs_mc->REG_06C = PSRAM_UHS_MC_T_MRS(val);
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// tCEM >= 4 cycles
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psramuhs_mc->REG_070 = PSRAM_UHS_MC_T_CEM(4);
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// tRST >= 10 us
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val = (clk / 1000000) * 10;
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psramuhs_mc->REG_074 = PSRAM_UHS_MC_T_RST(val);
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// tSRF >= 100 ns
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val = ((clk / 1000000) + (10 - 1)) / 10;
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psramuhs_mc->REG_078 = PSRAM_UHS_MC_T_SRF(val);
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// tSRF >= 70 ns
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val = ((clk / 1000000) * 70 + (1000 - 1)) / 1000;
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psramuhs_mc->REG_07C = PSRAM_UHS_MC_T_XSR(val);
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// tHS >= 150 us
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val = (clk / 1000000) * 150;
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psramuhs_mc->REG_080 = PSRAM_UHS_MC_T_HS(val);
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// tXPHS >= 100 ns
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val = ((clk / 1000000) + (10 - 1)) / 10;
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psramuhs_mc->REG_084 = PSRAM_UHS_MC_T_XPHS(val);
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// tXHS >= 150 us
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val = (clk / 1000000) * 150;
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psramuhs_mc->REG_088 = PSRAM_UHS_MC_T_XHS(val);
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// tZQCAL >= 1 us
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val = (clk / 1000000) * 1;
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psramuhs_mc->REG_08C = PSRAM_UHS_MC_T_ZQCAL(val);
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// tZQCRST >= 1 us
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val = (clk / 1000000) * 1;
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psramuhs_mc->REG_090 = PSRAM_UHS_MC_T_ZQCRST(val);
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// NOP dummy cycles, same as tXPHS >= 100 ns
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val = ((clk / 1000000) + (10 - 1)) / 10;
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psramuhs_mc->REG_0A0 =
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PSRAM_UHS_MC_STOP_CLK_IN_NOP | PSRAM_UHS_MC_NOP_DMY_CYC(val);
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psramuhs_mc->REG_0A4 = PSRAM_UHS_MC_QUEUE_IDLE_CYCLE(50000);
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// tDQSCK in [2 ns, 6.5 ns], expanded time >= tDQSCK_MAX
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val = ((clk / 1000000) * 65 / 10 + (1000 - 1)) / 1000;
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psramuhs_mc->REG_0A8 = PSRAM_UHS_MC_T_EXPANDRD(val);
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}
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static void hal_psramuhs_mc_init(uint32_t clk) {
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uint32_t val;
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uint32_t burst_len;
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uint32_t boundary;
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|
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val = PSRAM_UHS_MC_CHIP_TYPE;
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#ifdef PSRAMUHS_DUAL_8BIT
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val |= PSRAM_UHS_MC_CHIP_BIT;
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#endif
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#ifdef PSRAMUHS_DUAL_SWITCH
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val |= PSRAM_UHS_MC_CHIP_SWITCH;
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#endif
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#ifdef PSRAMUHS_16BIT
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val |= PSRAM_UHS_MC_CHIP_IO_X16 | PSRAM_UHS_MC_CHIP_CA_PATTERN(2);
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#else
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val |= PSRAM_UHS_MC_CHIP_CA_PATTERN(1);
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#endif
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#if (PSRAMUHS_SIZE == 0x800000)
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val |= PSRAM_UHS_MC_CHIP_MEM_SIZE(1);
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#elif (PSRAMUHS_SIZE == 0x1000000)
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val |= PSRAM_UHS_MC_CHIP_MEM_SIZE(2);
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#elif (PSRAMUHS_SIZE == 0x2000000)
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val |= PSRAM_UHS_MC_CHIP_MEM_SIZE(3);
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#else
|
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ASSERT(false, "Bad PSRAMUHS_SIZE=0x%08X", PSRAMUHS_SIZE);
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#endif
|
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psramuhs_mc->REG_000 = val;
|
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psramuhs_mc->REG_024 =
|
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PSRAM_UHS_MC_STOP_CLK_IDLE | PSRAM_UHS_MC_AUTOWAKEUP_EN;
|
|
// Burst length: 1=32 bytes (Cortex-M) or 2=64 bytes (Cortex-A), Page
|
|
// boundary: 2K bytes
|
|
#ifdef PSRAMUHS_WRAP_ENABLE
|
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#if defined(__ARM_ARCH_ISA_ARM) || defined(DSP_ENABLE)
|
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burst_len = 0x2; // 64B
|
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#else
|
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burst_len = 0x1; // 32B
|
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#endif
|
|
#else
|
|
#ifdef PSRAMUHS_DUAL_8BIT
|
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burst_len = 0x6; // 0:16B 5;2KB 6:4KB
|
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#else
|
|
burst_len = 0x5; // 0:16B 5;2KB 6:4KB
|
|
#endif
|
|
#endif
|
|
#ifdef PSRAMUHS_DUAL_8BIT
|
|
boundary = 2;
|
|
#else
|
|
boundary = 1;
|
|
#endif
|
|
psramuhs_mc->REG_034 = PSRAM_UHS_MC_BURST_LENGTH(burst_len) |
|
|
PSRAM_UHS_MC_PAGE_BOUNDARY(boundary);
|
|
|
|
// AXI bus width: 128 bits
|
|
psramuhs_mc->REG_038 = PSRAM_UHS_MC_BUS_WIDTH;
|
|
// Write buffer level with high priority: 0~15
|
|
psramuhs_mc->REG_03C = PSRAM_UHS_MC_HIGH_PRI_LEVEL(8);
|
|
#ifdef PSRAMUHS_PRA_ENABLE
|
|
psramuhs_mc->REG_040 = PSRAM_UHS_MC_PRA_ENABLE | PSRAM_UHS_MC_PRA_MAX_CNT(32);
|
|
#else
|
|
#ifdef PSRAMUHS_AUTO_PRECHARGE
|
|
psramuhs_mc->REG_040 =
|
|
PSRAM_UHS_MC_AUTO_PRECHARGE | PSRAM_UHS_MC_PRA_MAX_CNT(32);
|
|
#else
|
|
psramuhs_mc->REG_040 = PSRAM_UHS_MC_PRA_MAX_CNT(32);
|
|
#endif
|
|
#endif
|
|
#ifdef PSRAMUHS_WRAP_ENABLE
|
|
psramuhs_mc->REG_040 |= PSRAM_UHS_MC_CP_WRAP_EN;
|
|
#endif
|
|
psramuhs_mc->REG_048 = PSRAM_UHS_MC_FRE_RATIO(2);
|
|
#ifdef PSRAMUHS_DUMMY_CYCLE
|
|
psramuhs_mc->REG_840 |= PSRAM_UHS_MC_PHY_DUMMY_CYC_EN;
|
|
#endif
|
|
#if defined(CHIP_BEST2001)
|
|
psramuhs_mc->REG_840 |= PSRAM_UHS_MC_PHY_IDLE_PAD_EN;
|
|
#endif
|
|
psramuhs_mc->REG_844 = PSRAM_UHS_MC_T_WPST(2);
|
|
|
|
hal_psramuhsip_set_reg_fifo_width();
|
|
hal_psramuhsip_set_reg_data_mask();
|
|
|
|
hal_psramuhs_mc_set_timing(clk);
|
|
|
|
psramuhs_mc->REG_400 = PSRAM_UHS_MC_INIT_COMPLETE;
|
|
|
|
#ifdef PSRAMUHS_DIG_LOOPBACK
|
|
psramuhs_mc->REG_840 |= PSRAM_UHS_MC_PHY_LOOPBACK_EN;
|
|
psramuhs_mc->REG_044 |= PSRAM_UHS_MC_SNP_DISABLE;
|
|
#endif
|
|
#ifdef PSRAMUHS_ANA_LOOPBACK
|
|
psramuhs_mc->REG_044 |= PSRAM_UHS_MC_SNP_DISABLE;
|
|
psramuhs_mc->REG_0B0 |= PSRAM_UHS_MC_MGR_FIFO_TEST_EN;
|
|
psramuhs_mc->REG_840 |= PSRAM_UHS_MC_ANA_LOOPBACK_EN;
|
|
#endif
|
|
|
|
#if !defined(PSRAMUHS_DIG_LOOPBACK) && !defined(PSRAMUHS_ANA_LOOPBACK)
|
|
psramuhsphy_init_calib();
|
|
#endif
|
|
}
|
|
|
|
void hal_psramuhs_mc_entry_auto_lp() {
|
|
psramuhs_mc->REG_024 |=
|
|
PSRAM_UHS_MC_ENTRY_SLEEP_IDLE | PSRAM_UHS_MC_ENTRY_SELF_REFRESH_IDLE;
|
|
}
|
|
|
|
void hal_psramuhs_snoop_enable() {
|
|
psramuhs_mc->REG_044 &= ~PSRAM_UHS_MC_SNP_DISABLE;
|
|
}
|
|
void hal_psramuhs_snoop_disable() {
|
|
psramuhs_mc->REG_044 |= PSRAM_UHS_MC_SNP_DISABLE;
|
|
}
|
|
void hal_psramuhs_refresh_enable() {
|
|
#ifdef PSRAMUHS_BURST_REFRESH
|
|
psramuhs_mc->REG_020 =
|
|
PSRAM_UHS_MC_REFRESH_MODE | PSRAM_UHS_MC_BURST_REFRESH_EN;
|
|
#else
|
|
psramuhs_mc->REG_020 = PSRAM_UHS_MC_REFRESH_MODE;
|
|
#endif
|
|
}
|
|
void hal_psramuhs_init(void) {
|
|
#if PSRAMUHS_ENABLE
|
|
#error "must set MPU befor 2001 eco"
|
|
#endif
|
|
|
|
hal_cache_wrap_enable(HAL_CACHE_ID_I_CACHE);
|
|
hal_cache_wrap_enable(HAL_CACHE_ID_D_CACHE);
|
|
|
|
hal_cmu_ddr_clock_enable();
|
|
hal_cmu_clock_enable(HAL_CMU_MOD_O_PSRAMUHS);
|
|
hal_cmu_clock_enable(HAL_CMU_MOD_H_PSRAMUHS);
|
|
hal_cmu_reset_clear(HAL_CMU_MOD_O_PSRAMUHS);
|
|
hal_cmu_reset_clear(HAL_CMU_MOD_H_PSRAMUHS);
|
|
|
|
psramuhsphy_open(psramuhs_run_clk);
|
|
hal_psramuhs_mc_init(psramuhs_run_clk);
|
|
psramuhs_start_clock();
|
|
hal_sys_timer_delay_us(3);
|
|
psramuhs_reset();
|
|
psramuhs_stop_clock();
|
|
psramuhs_set_timing(psramuhs_run_clk);
|
|
hal_psramuhs_refresh_enable();
|
|
#if !defined(PSRAMUHS_DIG_LOOPBACK) && !defined(PSRAMUHS_ANA_LOOPBACK)
|
|
hal_psramuhs_snoop_disable();
|
|
psramuhsphy_calib(psramuhs_run_clk);
|
|
hal_psramuhs_snoop_enable();
|
|
#endif
|
|
// hal_psramuhs_mc_entry_auto_lp();
|
|
}
|
|
|
|
#endif
|