75381150fd
Formatting Pass 1 Lots of fixups to adding stdint and stdbool all over the place Formatting Pass 2 Formatting Pass 3 Formatting Pass 4 Update app_bt_stream.cpp
153 lines
3.2 KiB
C
153 lines
3.2 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifdef CHIP_HAS_SPIPHY
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#include "hal_phyif.h"
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#include "cmsis.h"
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#include "hal_location.h"
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#include "hal_spi.h"
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#include "plat_types.h"
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#define PHY_READ_CMD(r) ((1 << 24) | (((r)&0xFF) << 16))
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#define PHY_WRITE_CMD(r, v) ((((r)&0xFF) << 16) | ((v)&0xFFFF))
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#define PHY_READ_VAL(v) ((v)&0xFFFF)
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#define SPIPHY_REG_CS(r) ((r) >> 12)
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#define SPIPHY_REG_PAGE(r) (((r) >> 8) & 0xF)
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#define SPIPHY_REG_OFFSET(r) ((r)&0xFF)
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static const struct HAL_SPI_CFG_T spi_cfg = {
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.clk_delay_half = false,
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.clk_polarity = false,
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.slave = false,
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.dma_rx = false,
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.dma_tx = false,
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.rx_sep_line = true,
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.cs = 0,
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.rate = 6500000,
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.tx_bits = 25,
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.rx_bits = 25,
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.rx_frame_bits = 0,
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};
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static uint8_t BOOT_BSS_LOC phyif_open_map;
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static uint8_t BOOT_BSS_LOC phy_cs;
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static int hal_phyif_rawread(unsigned short reg, unsigned short *val) {
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int ret;
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unsigned int data;
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unsigned int cmd;
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data = 0;
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cmd = PHY_READ_CMD(reg);
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ret = hal_spiphy_recv(&cmd, &data, 4);
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if (ret) {
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return ret;
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}
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*val = PHY_READ_VAL(data);
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return 0;
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}
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static int hal_phyif_rawwrite(unsigned short reg, unsigned short val) {
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int ret;
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unsigned int cmd;
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cmd = PHY_WRITE_CMD(reg, val);
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ret = hal_spiphy_send(&cmd, 4);
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if (ret) {
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return ret;
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}
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return 0;
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}
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int hal_phyif_reg_read(unsigned short reg, unsigned short *val) {
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uint32_t lock;
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int ret;
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uint8_t cs;
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// uint8_t page;
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cs = SPIPHY_REG_CS(reg);
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// page = SPIPHY_REG_PAGE(reg);
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reg = SPIPHY_REG_OFFSET(reg);
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lock = int_lock();
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if (cs != phy_cs) {
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hal_spiphy_activate_cs(cs);
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phy_cs = cs;
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}
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ret = hal_phyif_rawread(reg, val);
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int_unlock(lock);
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return ret;
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}
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int hal_phyif_reg_write(unsigned short reg, unsigned short val) {
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uint32_t lock;
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int ret;
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uint8_t cs;
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// uint8_t page;
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cs = SPIPHY_REG_CS(reg);
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// page = SPIPHY_REG_PAGE(reg);
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reg = SPIPHY_REG_OFFSET(reg);
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lock = int_lock();
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if (cs != phy_cs) {
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hal_spiphy_activate_cs(cs);
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phy_cs = cs;
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}
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ret = hal_phyif_rawwrite(reg, val);
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int_unlock(lock);
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return ret;
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}
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int hal_phyif_open(uint32_t cs) {
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int ret;
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uint32_t lock;
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ret = 0;
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lock = int_lock();
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if (phyif_open_map == 0) {
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ret = hal_spiphy_open(&spi_cfg);
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}
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if (ret == 0) {
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phyif_open_map |= (1 << cs);
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}
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int_unlock(lock);
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return ret;
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}
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int hal_phyif_close(uint32_t cs) {
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int ret;
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uint32_t lock;
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ret = 0;
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lock = int_lock();
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phyif_open_map &= ~(1 << cs);
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if (phyif_open_map == 0) {
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ret = hal_spiphy_close(spi_cfg.cs);
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}
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int_unlock(lock);
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return ret;
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}
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#endif
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