91 lines
1.9 KiB
C
91 lines
1.9 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __NORFLASH_CFG_H__
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#define __NORFLASH_CFG_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "plat_types.h"
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#define STATUS_S10_LB_BIT_SHIFT 2
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#define STATUS_S10_LB_BIT_MASK (1 << STATUS_S10_LB_BIT_SHIFT)
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#define STATUS_S11_LB1_BIT_SHIFT 3
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#define STATUS_S11_LB1_BIT_MASK (1 << STATUS_S11_LB1_BIT_SHIFT)
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enum SEC_REG_BASE_T {
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SEC_REG_BASE_0X1000,
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SEC_REG_BASE_0X0000,
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};
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enum SEC_REG_SIZE_T {
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SEC_REG_SIZE_1024,
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SEC_REG_SIZE_512,
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SEC_REG_SIZE_256,
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};
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enum SEC_REG_OFFSET_T {
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SEC_REG_OFFSET_0X1000,
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SEC_REG_OFFSET_0X0100,
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};
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enum SEC_REG_CNT_T {
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SEC_REG_CNT_3,
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SEC_REG_CNT_4,
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};
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enum SEC_REG_PP_T {
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SEC_REG_PP_256,
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SEC_REG_PP_1024,
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};
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enum SEC_REG_LB_T {
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SEC_REG_LB_S11_S13,
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SEC_REG_LB_S10,
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};
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struct norflash_cfg_struct_t {
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uint8_t neg_phase:1;
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uint8_t pos_neg:1;
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uint8_t cmdquad:1;
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uint8_t samdly:3;
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uint8_t div; /* least 2 */
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uint8_t dualmode:1;
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uint8_t holdpin:1;
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uint8_t wprpin:1;
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uint8_t quadmode:1;
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uint8_t mod_clk:4;
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uint8_t spiruen:3;
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uint8_t spirden:3;
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uint8_t dualiocmd;
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uint8_t rdcmd;
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uint8_t frdcmd;
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uint8_t qrdcmd; /* quad io cmd */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif
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