154 lines
6.2 KiB
C
154 lines
6.2 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_PSRAM_PHY_V2_H__
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#define __REG_PSRAM_PHY_V2_H__
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#include "plat_types.h"
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struct PSRAM_PHY_T {
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__IO uint32_t REG_000;
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__IO uint32_t REG_004;
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__IO uint32_t REG_008;
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__IO uint32_t REG_00C;
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__IO uint32_t REG_010;
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__IO uint32_t REG_014;
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__IO uint32_t REG_018;
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__IO uint32_t REG_01C;
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__IO uint32_t REG_020;
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__IO uint32_t REG_024;
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__IO uint32_t REG_028;
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__IO uint32_t REG_02C;
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__IO uint32_t REG_030;
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__IO uint32_t REG_034;
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__IO uint32_t REG_038;
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__IO uint32_t REG_03C;
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__IO uint32_t REG_040;
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__IO uint32_t REG_044;
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__IO uint32_t REG_048;
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__IO uint32_t REG_04C;
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__IO uint32_t REG_050;
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__IO uint32_t REG_054;
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__IO uint32_t REG_058;
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__IO uint32_t REG_05C;
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};
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// reg_00
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#define PSRAM_ULP_PHY_CHIP_TYPE (1 << 0)
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#define PSRAM_ULP_PHY_CHIP_BIT (1 << 1)
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#define PSRAM_ULP_PHY_MEMORY_WIDTH(n) (((n) & 0x3) << 2)
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#define PSRAM_ULP_PHY_MEMORY_WIDTH_MASK (0x3 << 2)
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#define PSRAM_ULP_PHY_MEMORY_WIDTH_SHIFT (2)
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#define PSRAM_ULP_PHY_FRE_RATIO(n) (((n) & 0x3) << 4)
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#define PSRAM_ULP_PHY_FRE_RATIO_MASK (0x3 << 4)
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#define PSRAM_ULP_PHY_FRE_RATIO_SHIFT (4)
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// reg_04
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#define PSRAM_ULP_PHY_CTRL_DELAY(n) (((n) & 0x3) << 0)
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#define PSRAM_ULP_PHY_CTRL_DELAY_MASK (0x3 << 0)
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#define PSRAM_ULP_PHY_CTRL_DELAY_SHIFT (0)
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#define PSRAM_ULP_PHY_RX_DLY_EN (1 << 2)
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#define PSRAM_ULP_PHY_ALIGN_BYPASS (1 << 3)
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#define PSRAM_ULP_PHY_PHY_LOOPBACK_EN (1 << 4)
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#define PSRAM_ULP_PHY_PHY_DUMMY_CYC_EN (1 << 5)
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// reg_08
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#define PSRAM_ULP_PHY_T_WPST(n) (((n) & 0x7) << 0)
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#define PSRAM_ULP_PHY_T_WPST_MASK (0x7 << 0)
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#define PSRAM_ULP_PHY_T_WPST_SHIFT (0)
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// reg_0c
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#define PSRAM_ULP_PHY_RESERVED(n) (((n) & 0x3F) << 0)
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#define PSRAM_ULP_PHY_RESERVED_MASK (0x3F << 0)
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#define PSRAM_ULP_PHY_RESERVED_SHIFT (0)
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// reg_00
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// reg_10
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#define PSRAM_ULP_PHY_CMD_CONFLICT_CLR (1 << 0)
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// reg_40
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#define PSRAM_ULP_PHY_PHY_CFG_UPDATE (1 << 0)
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// reg_44
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#define PSRAM_ULP_PHY_CMD_CONFLICT_STS (1 << 0)
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#define PSRAM_ULP_PHY_PHY_FSM_STATE(n) (((n) & 0xF) << 1)
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#define PSRAM_ULP_PHY_PHY_FSM_STATE_MASK (0xF << 1)
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#define PSRAM_ULP_PHY_PHY_FSM_STATE_SHIFT (1)
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// reg_48
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#define PSRAM_ULP_PHY_REG_LDO_PU (1 << 0)
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#define PSRAM_ULP_PHY_REG_LDO_PRECHARGE (1 << 1)
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#define PSRAM_ULP_PHY_REG_LDO_IEN1(n) (((n) & 0xF) << 2)
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#define PSRAM_ULP_PHY_REG_LDO_IEN1_MASK (0xF << 2)
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#define PSRAM_ULP_PHY_REG_LDO_IEN1_SHIFT (2)
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#define PSRAM_ULP_PHY_REG_LDO_IEN2(n) (((n) & 0xF) << 6)
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#define PSRAM_ULP_PHY_REG_LDO_IEN2_MASK (0xF << 6)
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#define PSRAM_ULP_PHY_REG_LDO_IEN2_SHIFT (6)
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#define PSRAM_ULP_PHY_REG_LDO_VTUNE(n) (((n) & 0x7) << 10)
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#define PSRAM_ULP_PHY_REG_LDO_VTUNE_MASK (0x7 << 10)
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#define PSRAM_ULP_PHY_REG_LDO_VTUNE_SHIFT (10)
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// reg_4c
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#define PSRAM_ULP_PHY_REG_PSRAM_PU (1 << 0)
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#define PSRAM_ULP_PHY_REG_PSRAM_SWRC(n) (((n) & 0x3) << 1)
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#define PSRAM_ULP_PHY_REG_PSRAM_SWRC_MASK (0x3 << 1)
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#define PSRAM_ULP_PHY_REG_PSRAM_SWRC_SHIFT (1)
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#define PSRAM_ULP_PHY_REG_PSRAM_TXDRV(n) (((n) & 0x7) << 3)
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#define PSRAM_ULP_PHY_REG_PSRAM_TXDRV_MASK (0x7 << 3)
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#define PSRAM_ULP_PHY_REG_PSRAM_TXDRV_SHIFT (3)
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#define PSRAM_ULP_PHY_REG_PSRAM_LOOPBACK_EN (1 << 6)
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// reg_50
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#define PSRAM_ULP_PHY_REG_DLL_PU (1 << 0)
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#define PSRAM_ULP_PHY_REG_DLL_SWRC(n) (((n) & 0x3) << 1)
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#define PSRAM_ULP_PHY_REG_DLL_SWRC_MASK (0x3 << 1)
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#define PSRAM_ULP_PHY_REG_DLL_SWRC_SHIFT (1)
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#define PSRAM_ULP_PHY_REG_DLL_RANGE(n) (((n) & 0x3) << 3)
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#define PSRAM_ULP_PHY_REG_DLL_RANGE_MASK (0x3 << 3)
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#define PSRAM_ULP_PHY_REG_DLL_RANGE_SHIFT (3)
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#define PSRAM_ULP_PHY_REG_DLL_DLY_INI(n) (((n) & 0xFF) << 5)
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#define PSRAM_ULP_PHY_REG_DLL_DLY_INI_MASK (0xFF << 5)
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#define PSRAM_ULP_PHY_REG_DLL_DLY_INI_SHIFT (5)
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#define PSRAM_ULP_PHY_REG_DLL(n) (((n) & 0xFF) << 13)
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#define PSRAM_ULP_PHY_REG_DLL_MASK (0xFF << 13)
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#define PSRAM_ULP_PHY_REG_DLL_SHIFT (13)
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#define PSRAM_ULP_PHY_REG_DLL_RESETB (1 << 21)
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#define PSRAM_ULP_PHY_REG_DLL_CK_RDY (1 << 22)
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// reg_54
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY(n) (((n) & 0x1F) << 0)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY_MASK (0x1F << 0)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY_SHIFT (0)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY(n) (((n) & 0x1F) << 5)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY_MASK (0x1F << 5)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY_SHIFT (5)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY(n) (((n) & 0x1F) << 10)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY_MASK (0x1F << 10)
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#define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY_SHIFT (10)
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#define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY(n) (((n) & 0x1F) << 15)
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#define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY_MASK (0x1F << 15)
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#define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY_SHIFT (15)
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// reg_58
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#define PSRAM_ULP_PHY_DLL_DLY_IN(n) (((n) & 0x3F) << 0)
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#define PSRAM_ULP_PHY_DLL_DLY_IN_MASK (0x3F << 0)
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#define PSRAM_ULP_PHY_DLL_DLY_IN_SHIFT (0)
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#define PSRAM_ULP_PHY_DLL_LOCK (1 << 6)
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#define PSRAM_ULP_PHY_DLL_ALL_ZERO (1 << 7)
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#define PSRAM_ULP_PHY_DLL_ALL_ONE (1 << 8)
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#endif
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