369 lines
17 KiB
C
369 lines
17 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_I2CIP_H_
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#define __REG_I2CIP_H_
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#include "plat_types.h"
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#define I2CIP_TX_FIFO_DEPTH (8)
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#define I2CIP_RX_FIFO_DEPTH (8)
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#define NANO_TO_MICRO 1000
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#define I2CIP_SS_SCL_HCNT_REG_OFFSET 0x14
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#define I2CIP_SS_SCL_HCNT_SHIFT (0)
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#define I2CIP_SS_SCL_HCNT_MASK ((0xffff)<<I2CIP_SS_SCL_HCNT_SHIFT)
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#define I2CIP_SS_SCL_LCNT_REG_OFFSET 0x18
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#define I2CIP_SS_SCL_LCNT_SHIFT (0)
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#define I2CIP_SS_SCL_LCNT_MASK ((0xffff)<<I2CIP_SS_SCL_LCNT_SHIFT)
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#define I2CIP_FS_SCL_HCNT_REG_OFFSET 0x1C
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#define I2CIP_FS_SCL_HCNT_SHIFT (0)
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#define I2CIP_FS_SCL_HCNT_MASK ((0xffff)<<I2CIP_FS_SCL_HCNT_SHIFT)
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#define I2CIP_FS_SCL_LCNT_REG_OFFSET 0x20
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#define I2CIP_FS_SCL_LCNT_SHIFT (0)
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#define I2CIP_FS_SCL_LCNT_MASK ((0xffff)<<I2CIP_FS_SCL_LCNT_SHIFT)
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#define I2CIP_HS_SCL_HCNT_REG_OFFSET 0x24
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#define I2CIP_HS_SCL_HCNT_SHIFT (0)
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#define I2CIP_HS_SCL_HCNT_MASK ((0xffff)<<I2CIP_HS_SCL_hCNT_SHIFT)
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#define I2CIP_HS_SCL_LCNT_REG_OFFSET 0x28
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#define I2CIP_HS_SCL_LCNT_SHIFT (0)
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#define I2CIP_HS_SCL_LCNT_MASK ((0xffff)<<I2CIP_HS_SCL_LCNT_SHIFT)
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/* High and low times in different speed modes (in ns) */
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#define MIN_SS_SCL_HIGHTIME 4000
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#define MIN_SS_SCL_LOWTIME 4700
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#define MIN_FS_SCL_HIGHTIME 600
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#define MIN_FS_SCL_LOWTIME 1300
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#define MIN_HS_SCL_HIGHTIME 60
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#define MIN_HS_SCL_LOWTIME 160
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/* Worst case timeout for 1 byte is kept as 2ms */
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#define I2C_BYTE_TO (CONFIG_SYSTICK_HZ/500)
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#define I2C_STOPDET_TO (CONFIG_SYSTICK_HZ/500)
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#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
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/* i2c control register definitions */
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#define I2CIP_CTRL_REG_OFFSET 0x0
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#define I2CIP_SPEED_SHIFT (1)
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#define I2CIP_SPEED_MASK ((0x3)<<I2CIP_SPEED_SHIFT)
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#define I2CIP_HIGH_SPEED_SHIFT (1)
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#define I2CIP_HIGH_SPEED_MASK ((0x3)<<I2CIP_HIGH_SPEED_SHIFT)
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#define I2CIP_FAST_SPEED_SHIFT (1)
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#define I2CIP_FAST_SPEED_MASK ((0x2)<<I2CIP_HIGH_SPEED_SHIFT)
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#define I2CIP_STANDARD_SPEED_SHIFT (1)
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#define I2CIP_STANDARD_SPEED_MASK ((0x1)<<I2CIP_STANDARD_SPEED_SHIFT)
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#define I2CIP_SLAVE_DISABLE_SHIFT (6)
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#define I2CIP_SLAVE_DISABLE_MASK ((0x1)<<I2CIP_SLAVE_DISABLE_SHIFT)
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#define I2CIP_RESTART_ENABLE_SHIFT (5)
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#define I2CIP_RESTART_ENABLE_MASK ((0x1)<<I2CIP_RESTART_ENABLE_SHIFT)
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#define I2CIP_MASTER_MODE_SHIFT (0)
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#define I2CIP_MASTER_MODE_MASK ((0x1)<<I2CIP_MASTER_MODE_SHIFT)
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#define I2CIP_10BITADDR_MASTER_SHIFT (4)
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#define I2CIP_10BITADDR_MASTER_MASK ((0x1)<<I2CIP_10BITADDR_MASTER_SHIFT)
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#define I2CIP_10BITADDR_SLAVE_SHIFT (3)
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#define I2CIP_10BITADDR_SLAVE_MASK ((0x1)<<I2CIP_10BITADDR_SLAVE_SHIFT)
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/* i2c target address register definitions */
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#define I2CIP_TARGET_ADDRESS_REG_OFFSET 0x04
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#define I2CIP_TARGET_ADDRESS_SHIFT 0
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#define I2CIP_TARGET_ADDRESS_MASK ((0x3ff)<<I2CIP_TARGET_ADDRESS_SHIFT)
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#define I2CIP_TARGET_ADDRESS_IC_10BITADDR_MASTER_SHIFT 12
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#define I2CIP_TARGET_ADDRESS_IC_10BITADDR_MASTER_MASK (1 << I2CIP_TARGET_ADDRESS_IC_10BITADDR_MASTER_SHIFT)
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#define I2CIP_TARGET_ADDRESS_SPECIAL_BIT_SHIFT 11
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#define I2CIP_TARGET_ADDRESS_SPECIAL_BIT_MASK ((0x1)<<I2CIP_TARGET_ADDRESS_SPECIAL_BIT_SHIFT)
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#define I2CIP_TARGET_ADDRESS_GC_OR_START_SHIFT 10
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#define I2CIP_TARGET_ADDRESS_GC_OR_START_MASK ((0x1)<<I2CIP_TARGET_ADDRESS_GC_OR_START_SHIFT)
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/* i2c slave address register definitions */
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#define I2CIP_ADDRESS_AS_SLAVE_REG_OFFSET 0x08
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#define I2CIP_ADDRESS_AS_SLAVE_SHIFT (0)
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#define I2CIP_ADDRESS_AS_SLAVE_MASK ((0x3ff)<<I2CIP_ADDRESS_AS_SLAVE_SHIFT)
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/* i2c data buffer and command register definitions */
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#define I2CIP_CMD_DATA_REG_OFFSET 0x10
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#define I2CIP_CMD_DATA_CMD_SHIFT (8)
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#define I2CIP_CMD_DATA_CMD_MASK ((0x1)<<I2CIP_CMD_DATA_CMD_SHIFT)
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#define I2CIP_CMD_DATA_CMD_READ_SHIFT (8)
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#define I2CIP_CMD_DATA_CMD_READ_MASK ((0x1)<<I2CIP_CMD_DATA_CMD_READ_SHIFT)
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#define I2CIP_CMD_DATA_CMD_WRITE_SHIFT (8)
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#define I2CIP_CMD_DATA_CMD_WRITE_MASK ((0x0)<<I2CIP_CMD_DATA_CMD_WRITE_SHIFT)
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#define I2CIP_CMD_DATA_STOP_SHIFT (9)
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#define I2CIP_CMD_DATA_STOP_MASK ((0x1)<<I2CIP_CMD_DATA_STOP_SHIFT)
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#define I2CIP_CMD_DATA_RESTART_SHIFT (10)
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#define I2CIP_CMD_DATA_RESTART_MASK ((0x1)<<I2CIP_CMD_DATA_RESTART_SHIFT)
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/* i2c interrupt status register definitions */
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#define I2CIP_INT_STATUS_REG_OFFSET 0x2C
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#define I2CIP_INT_STATUS_GEN_CALL_SHIFT (11)
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#define I2CIP_INT_STATUS_GEN_CALL_MASK ((0x1)<<I2CIP_INT_STATUS_GEN_CALL_SHIFT)
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#define I2CIP_INT_STATUS_START_DET_SHIFT (10)
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#define I2CIP_INT_STATUS_START_DET_MASK ((0x1)<<I2CIP_INT_STATUS_START_DET_SHIFT)
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#define I2CIP_INT_STATUS_STOP_DET_SHIFT (9)
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#define I2CIP_INT_STATUS_STOP_DET_MASK ((0x1)<<I2CIP_INT_STATUS_STOP_DET_SHIFT)
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#define I2CIP_INT_STATUS_ACTIVITY_SHIFT (8)
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#define I2CIP_INT_STATUS_ACTIVITY_MASK ((0x1)<<I2CIP_INT_STATUS_ACTIVITY_SHIFT)
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#define I2CIP_INT_STATUS_RX_DONE_SHIFT (7)
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#define I2CIP_INT_STATUS_RX_DONE_MASK ((0x1)<<I2CIP_INT_STATUS_RX_DONE_SHIFT)
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#define I2CIP_INT_STATUS_TX_ABRT_SHIFT (6)
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#define I2CIP_INT_STATUS_TX_ABRT_MASK ((0x1)<<I2CIP_INT_STATUS_TX_ABRT_SHIFT)
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#define I2CIP_INT_STATUS_RD_REQ_SHIFT (5)
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#define I2CIP_INT_STATUS_RD_REQ_MASK ((0x1)<<I2CIP_INT_STATUS_RD_REQ_SHIFT)
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#define I2CIP_INT_STATUS_TX_EMPTY_SHIFT (4)
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#define I2CIP_INT_STATUS_TX_EMPTY_MASK ((0x1)<<I2CIP_INT_STATUS_TX_EMPTY_SHIFT)
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#define I2CIP_INT_STATUS_TX_OVER_SHIFT (3)
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#define I2CIP_INT_STATUS_TX_OVER_MASK ((0x1)<<I2CIP_INT_STATUS_TX_OVER_SHIFT)
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#define I2CIP_INT_STATUS_RX_FULL_SHIFT (2)
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#define I2CIP_INT_STATUS_RX_FULL_MASK ((0x1)<<I2CIP_INT_STATUS_RX_FULL_SHIFT)
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#define I2CIP_INT_STATUS_RX_OVER_SHIFT (1)
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#define I2CIP_INT_STATUS_RX_OVER_MASK ((0x1)<<I2CIP_INT_STATUS_RX_OVER_SHIFT)
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#define I2CIP_INT_STATUS_RX_UNDER_SHIFT (0)
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#define I2CIP_INT_STATUS_RX_UNDER_MASK ((0x1)<<I2CIP_INT_STATUS_RX_UNDER_SHIFT)
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/* i2c raw interrupt status register definitions */
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#define I2CIP_RAW_INT_STATUS_REG_OFFSET 0x34
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#define I2CIP_RAW_INT_STATUS_GEN_CALL_SHIFT (11)
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#define I2CIP_RAW_INT_STATUS_GEN_CALL_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_GEN_CALL_SHIFT)
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#define I2CIP_RAW_INT_STATUS_START_DET_SHIFT (10)
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#define I2CIP_RAW_INT_STATUS_START_DET_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_START_DET_SHIFT)
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#define I2CIP_RAW_INT_STATUS_STOP_DET_SHIFT (9)
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#define I2CIP_RAW_INT_STATUS_STOP_DET_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_STOP_DET_SHIFT)
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#define I2CIP_RAW_INT_STATUS_ACTIVITY_SHIFT (8)
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#define I2CIP_RAW_INT_STATUS_ACTIVITY_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_ACTIVITY_SHIFT)
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#define I2CIP_RAW_INT_STATUS_RX_DONE_SHIFT (7)
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#define I2CIP_RAW_INT_STATUS_RX_DONE_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_RX_DONE_SHIFT)
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#define I2CIP_RAW_INT_STATUS_TX_ABRT_SHIFT (6)
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#define I2CIP_RAW_INT_STATUS_TX_ABRT_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_TX_ABRT_SHIFT)
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#define I2CIP_RAW_INT_STATUS_RD_REQ_SHIFT (5)
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#define I2CIP_RAW_INT_STATUS_RD_REQ_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_RD_REQ_SHIFT)
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#define I2CIP_RAW_INT_STATUS_TX_EMPTY_SHIFT (4)
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#define I2CIP_RAW_INT_STATUS_TX_EMPTY_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_TX_EMPTY_SHIFT)
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#define I2CIP_RAW_INT_STATUS_TX_OVER_SHIFT (3)
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#define I2CIP_RAW_INT_STATUS_TX_OVER_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_TX_OVER_SHIFT)
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#define I2CIP_RAW_INT_STATUS_RX_FULL_SHIFT (2)
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#define I2CIP_RAW_INT_STATUS_RX_FULL_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_RX_FULL_SHIFT)
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#define I2CIP_RAW_INT_STATUS_RX_OVER_SHIFT (1)
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#define I2CIP_RAW_INT_STATUS_RX_OVER_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_RX_OVER_SHIFT)
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#define I2CIP_RAW_INT_STATUS_RX_UNDER_SHIFT (0)
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#define I2CIP_RAW_INT_STATUS_RX_UNDER_MASK ((0x1)<<I2CIP_RAW_INT_STATUS_RX_UNDER_SHIFT)
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/* fifo threshold register definitions */
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#define I2CIP_RX_THRESHOLD_REG_OFFSET 0x38
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#define I2CIP_RX_TL_DEPTH (I2CIP_RX_FIFO_DEPTH - 1)
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#define I2CIP_RX_TL_QUARTER (I2CIP_RX_FIFO_DEPTH/4 - 1)
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#define I2CIP_RX_TL_HALF (I2CIP_RX_FIFO_DEPTH/2 - 1)
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#define I2CIP_RX_TL_THREE_QUARTER (I2CIP_RX_FIFO_DEPTH*3/4 - 1)
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#define I2CIP_RX_TL_1_BYTE (0)
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#define I2CIP_TX_THRESHOLD_REG_OFFSET 0x3C
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#define I2CIP_TX_TL_DEPTH ((I2CIP_TX_FIFO_DEPTH))
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#define I2CIP_TX_TL_QUARTER (I2CIP_TX_FIFO_DEPTH/4)
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#define I2CIP_TX_TL_HALF (I2CIP_TX_FIFO_DEPTH/2)
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#define I2CIP_TX_TL_THREE_QUARTER (I2CIP_TX_FIFO_DEPTH*3/4)
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#define I2CIP_TX_TL_1_BYTE (1)
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#define I2CIP_TX_TL_ZERO (0)
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/* i2c enable register definitions */
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#define I2CIP_ENABLE_REG_OFFSET 0x6c
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#define I2CIP_ENABLE_SHIFT 0
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#define I2CIP_ENABLE_MASK ((0x1)<<I2CIP_ENABLE_SHIFT)
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/* i2c status register definitions */
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#define I2CIP_STATUS_REG_OFFSET 0x70
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#define I2CIP_STATUS_SA_SHIFT (6)
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#define I2CIP_STATUS_SA_MASK ((0x1)<<I2CIP_STATUS_SA_SHIFT)
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#define I2CIP_STATUS_SHIFT (5)
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#define I2CIP_STATUS_MASK ((0x1)<<I2CIP_STATUS_SHIFT)
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#define I2CIP_STATUS_RFF_SHIFT (4)
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#define I2CIP_STATUS_RFF_MASK ((0x1)<<I2CIP_STATUS_RFF_SHIFT)
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#define I2CIP_STATUS_RFNE_SHIFT (3)
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#define I2CIP_STATUS_RFNE_MASK ((0x1)<<I2CIP_STATUS_RFNE_SHIFT)
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#define I2CIP_STATUS_TFE_SHIFT (2)
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#define I2CIP_STATUS_TFE_MASK ((0x1)<<I2CIP_STATUS_TFE_SHIFT)
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#define I2CIP_STATUS_TFNF_SHIFT (1)
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#define I2CIP_STATUS_TFNF_MASK ((0x1)<<I2CIP_STATUS_TFNF_SHIFT)
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#define I2CIP_STATUS_ACT_SHIFT (0)
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#define I2CIP_STATUS_ACT_MASK ((0x1)<<I2CIP_STATUS_ACT_SHIFT)
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/* i2c interrupt mask register */
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#define I2CIP_INT_MASK_REG_OFFSET 0x30
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#define I2CIP_INT_MASK_GEN_CALL_SHIFT (11)
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#define I2CIP_INT_MASK_GEN_CALL_MASK ((0x1)<<I2CIP_INT_MASK_GEN_CALL_SHIFT)
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#define I2CIP_INT_MASK_START_DET_SHIFT (10)
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#define I2CIP_INT_MASK_START_DET_MASK ((0x1)<<I2CIP_INT_MASK_START_DET_SHIFT)
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#define I2CIP_INT_MASK_STOP_DET_SHIFT (9)
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#define I2CIP_INT_MASK_STOP_DET_MASK ((0x1)<<I2CIP_INT_MASK_STOP_DET_SHIFT)
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#define I2CIP_INT_MASK_ACTIVITY_SHIFT (8)
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#define I2CIP_INT_MASK_ACTIVITY_MASK ((0x1)<<I2CIP_INT_MASK_ACTIVITY_SHIFT)
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#define I2CIP_INT_MASK_RX_DONE_SHIFT (7)
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#define I2CIP_INT_MASK_RX_DONE_MASK ((0x1)<<I2CIP_INT_MASK_RX_DONE_SHIFT)
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#define I2CIP_INT_MASK_TX_ABRT_SHIFT (6)
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#define I2CIP_INT_MASK_TX_ABRT_MASK ((0x1)<<I2CIP_INT_MASK_TX_ABRT_SHIFT)
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#define I2CIP_INT_MASK_RD_REQ_SHIFT (5)
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#define I2CIP_INT_MASK_RD_REQ_MASK ((0x1)<<I2CIP_INT_MASK_RD_REQ_SHIFT)
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#define I2CIP_INT_MASK_TX_EMPTY_SHIFT (4)
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#define I2CIP_INT_MASK_TX_EMPTY_MASK ((0x1)<<I2CIP_INT_MASK_TX_EMPTY_SHIFT)
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#define I2CIP_INT_MASK_TX_OVER_SHIFT (3)
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#define I2CIP_INT_MASK_TX_OVER_MASK ((0x1)<<I2CIP_INT_MASK_TX_OVER_SHIFT)
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#define I2CIP_INT_MASK_RX_FULL_SHIFT (2)
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#define I2CIP_INT_MASK_RX_FULL_MASK ((0x1)<<I2CIP_INT_MASK_RX_FULL_SHIFT)
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#define I2CIP_INT_MASK_RX_OVER_SHIFT (1)
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#define I2CIP_INT_MASK_RX_OVER_MASK ((0x1)<<I2CIP_INT_MASK_RX_OVER_SHIFT)
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#define I2CIP_INT_MASK_RX_UNDER_SHIFT (0)
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#define I2CIP_INT_MASK_RX_UNDER_MASK ((0x1)<<I2CIP_INT_MASK_RX_UNDER_SHIFT)
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#define I2CIP_INT_UNMASK_ALL (0)
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#define I2CIP_INT_MASK_ALL \
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(I2CIP_INT_MASK_GEN_CALL_MASK | \
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I2CIP_INT_MASK_START_DET_MASK | \
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I2CIP_INT_MASK_STOP_DET_MASK | \
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I2CIP_INT_MASK_ACTIVITY_MASK | \
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I2CIP_INT_MASK_RX_DONE_MASK | \
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I2CIP_INT_MASK_TX_ABRT_MASK | \
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I2CIP_INT_MASK_RD_REQ_MASK | \
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I2CIP_INT_MASK_TX_EMPTY_MASK | \
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I2CIP_INT_MASK_TX_OVER_MASK | \
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I2CIP_INT_MASK_RX_FULL_MASK | \
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I2CIP_INT_MASK_RX_OVER_MASK | \
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I2CIP_INT_MASK_RX_UNDER_MASK)
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#define I2CIP_INT_MASK_ERROR_MASK \
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(I2CIP_INT_MASK_TX_ABRT_MASK | \
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I2CIP_INT_MASK_TX_OVER_MASK | \
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I2CIP_INT_MASK_RX_OVER_MASK | \
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I2CIP_INT_MASK_RX_UNDER_MASK)
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/* i2c enable status register definitions */
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#define I2CIP_ENABLE_STATUS_REG_OFFSET 0x9c
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#define I2CIP_ENABLE_STATUS_ENABLE_SHIFT 0
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#define I2CIP_ENABLE_STATUS_ENABLE_MASK ((0x1)<<I2CIP_ENABLE_STATUS_ENABLE_SHIFT)
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/* i2c tx fifo level register definitions */
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#define I2CIP_TX_FIFO_LEVEL_REG_OFFSET 0x74
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/* i2c rx fifo level register definitions */
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#define I2CIP_RX_FIFO_LEVEL_REG_OFFSET 0x78
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/* i2c sda hold time register */
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#define I2CIP_SDA_HOLD_REG_OFFSET 0x7c
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/* i2c clear all intr register */
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#define I2CIP_CLR_ALL_INTR_REG_OFFSET 0x40
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/* i2c clear rx under register */
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#define I2CIP_CLR_RX_UNDER_REG_OFFSET 0x44
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/* i2c clear rx over register */
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#define I2CIP_CLR_RX_OVER_REG_OFFSET 0x48
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/* i2c clear tx over register */
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#define I2CIP_CLR_TX_OVER_REG_OFFSET 0x4c
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/* i2c clear rd req register */
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#define I2CIP_CLR_RD_REQ_REG_OFFSET 0x50
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/* i2c clear tx abrt register */
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#define I2CIP_CLR_TX_ABRT_REG_OFFSET 0x54
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/* i2c clear rx done register */
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#define I2CIP_CLR_RX_DONE_REG_OFFSET 0x58
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/* i2c clear activity register */
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#define I2CIP_CLR_ACTIVITY_REG_OFFSET 0x5c
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/* i2c clear stop det register */
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#define I2CIP_CLR_STOP_DET_REG_OFFSET 0x60
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/* i2c clear start det register */
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#define I2CIP_CLR_START_DET_REG_OFFSET 0x64
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/* i2c clear gen call register */
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#define I2CIP_CLR_GEN_CALL_REG_OFFSET 0x68
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/* i2c tx abrt source register */
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#define I2CIP_TX_ABRT_SOURCE_REG_OFFSET 0x80
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SHIFT (15)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SHIFT (14)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SHIFT (13)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ARB_LOST_SHIFT (12)
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#define I2CIP_TX_ABRT_SOURCE_ARB_LOST_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ARB_LOST_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SHIFT (11)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SHIFT (10)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SHIFT (9)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SHIFT (8)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SHIFT (7)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SHIFT (6)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_GCALL_READ_SHIFT (5)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_GCALL_READ_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_GCALL_READ_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SHIFT (4)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SHIFT (3)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SHIFT (2)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SHIFT (1)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SHIFT)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SHIFT (0)
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#define I2CIP_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MASK ((0x1)<<I2CIP_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SHIFT)
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/* i2c dma control register */
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#define I2CIP_DMA_CR_REG_OFFSET 0x88
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#define I2CIP_DMA_CR_TDMAE_SHIFT (1)
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#define I2CIP_DMA_CR_TDMAE_MASK ((0x1)<<I2CIP_DMA_CR_TDMAE_SHIFT)
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#define I2CIP_DMA_CR_RDMAE_SHIFT (0)
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#define I2CIP_DMA_CR_RDMAE_MASK ((0x1)<<I2CIP_DMA_CR_RDMAE_SHIFT)
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/* i2c tx dma transfer threshold register */
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#define I2CIP_DMA_TX_TL_REG_OFFSET 0x8c
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#define I2CIP_DMA_TX_TL_DEPTH (I2CIP_TX_FIFO_DEPTH)
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#define I2CIP_DMA_TX_TL_HALF (I2CIP_DMA_TX_TL_DEPTH/2)
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#define I2CIP_DMA_TX_TL_1_BYTE (1)
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/* i2c rx dma transfer threshold register */
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#define I2CIP_DMA_RX_TL_REG_OFFSET 0x90
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#define I2CIP_DMA_RX_TL_DEPTH (I2CIP_RX_FIFO_DEPTH)
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#define I2CIP_DMA_RX_TL_HALF (I2CIP_DMA_RX_TL_DEPTH/2)
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#define I2CIP_DMA_RX_TL_1_BYTE (1)
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#define I2CIP_IC_ENABLE_STATUS_REG_OFFSET 0x9C
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#define I2CIP_STATUS_IC_EN (1 << 0)
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#define I2CIP_STATUS_SLV_RX_ABORTED (1 << 1)
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#define I2CIP_STATUS_SLV_FIFO_FILLED_AND_FLUSHED (1 << 2)
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#define I2CIP_IC_FS_SPKLEN_REG_OFFSET 0xA0
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#define I2CIP_IC_FS_SPKLEN_SHIFT 0
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#define I2CIP_IC_FS_SPKLEN_MASK (0xFF << I2CIP_IC_FS_SPKLEN_SHIFT)
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#define I2CIP_IC_FS_SPKLEN(n) BITFIELD_VAL(I2CIP_IC_FS_SPKLEN, n)
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#define I2CIP_IC_HS_SPKLEN_REG_OFFSET 0xA4
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#define I2CIP_IC_HS_SPKLEN_SHIFT 0
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#define I2CIP_IC_HS_SPKLEN_MASK (0xFF << I2CIP_IC_FS_SPKLEN_SHIFT)
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#define I2CIP_IC_HS_SPKLEN(n) BITFIELD_VAL(I2CIP_IC_FS_SPKLEN, n)
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#define I2CIP_IC_VAD_PATH_REG_OFFSET 0xA8
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#define I2CIP_IC_PUSH_DATA_BYPASS (1 << 0)
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/* Speed Selection */
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#define IC_SPEED_MODE_STANDARD 1
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#define IC_SPEED_MODE_FAST 2
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#define IC_SPEED_MODE_MAX 3
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#define I2C_MAX_SPEED 3400000
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#define I2C_FSP_SPEED 1000000
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#define I2C_FAST_SPEED 400000
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#define I2C_STANDARD_SPEED 100000
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#endif /* __REG_I2CIP_H_ */
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