647 lines
17 KiB
C
647 lines
17 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifdef CHIP_HAS_TRANSQ
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#include "hal_transq.h"
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#include "cmsis_nvic.h"
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#include "hal_cmu.h"
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#include "hal_trace.h"
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#include "plat_addr_map.h"
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#include "reg_transq.h"
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#include "stdbool.h"
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// BITMAP:
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// [High Priority Slots] ...... [Normal Priority Slots]
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// 31 30 29 28 27 26 25 ...... 10 9 8 7 6 5 4 3 2 1 0
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static struct TRANSQ_T *const transq[HAL_TRANSQ_ID_QTY] = {
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(struct TRANSQ_T *)TRANSQ0_BASE,
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#if (CHIP_HAS_TRANSQ > 1)
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(struct TRANSQ_T *)TRANSQ1_BASE,
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#endif
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};
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static struct TRANSQ_T *const peer_transq[HAL_TRANSQ_ID_QTY] = {
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(struct TRANSQ_T *)TRANSQ0_PEER_BASE,
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#if (CHIP_HAS_TRANSQ > 1)
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(struct TRANSQ_T *)TRANSQ1_PEER_BASE,
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#endif
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};
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static const IRQn_Type remote_irq_num[HAL_TRANSQ_ID_QTY] = {
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TRANSQ0_RMT_IRQn,
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#if (CHIP_HAS_TRANSQ > 1)
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TRANSQ1_RMT_IRQn,
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#endif
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};
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static const IRQn_Type local_irq_num[HAL_TRANSQ_ID_QTY] = {
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TRANSQ0_LCL_IRQn,
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#if (CHIP_HAS_TRANSQ > 1)
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TRANSQ1_LCL_IRQn,
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#endif
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};
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static struct HAL_TRANSQ_CFG_T transq_cfg[HAL_TRANSQ_ID_QTY];
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static uint8_t next_tx_slot[HAL_TRANSQ_ID_QTY][HAL_TRANSQ_PRI_QTY];
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static uint8_t active_tx_slot[HAL_TRANSQ_ID_QTY][HAL_TRANSQ_PRI_QTY];
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static bool tx_slot_full[HAL_TRANSQ_ID_QTY][HAL_TRANSQ_PRI_QTY];
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static uint8_t next_rx_slot[HAL_TRANSQ_ID_QTY][HAL_TRANSQ_PRI_QTY];
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static uint32_t rx_irq_mask[HAL_TRANSQ_ID_QTY][HAL_TRANSQ_PRI_QTY];
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static uint32_t construct_mask(uint32_t lsb, uint32_t width) {
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int i;
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uint32_t result;
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if (lsb >= 32 || width == 0) {
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return 0;
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}
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result = 0;
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for (i = lsb; i < lsb + width; i++) {
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result |= (1 << i);
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}
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return result;
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}
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static uint32_t get_next_rx_slot(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri, uint32_t slot) {
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slot++;
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if (pri == HAL_TRANSQ_PRI_HIGH) {
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if (slot >= TRANSQ_SLOT_NUM) {
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slot = TRANSQ_SLOT_NUM - transq_cfg[id].slot.rx_num[pri];
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}
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} else {
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if (slot >= transq_cfg[id].slot.rx_num[pri]) {
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slot = 0;
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}
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}
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return slot;
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}
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static uint32_t get_next_tx_slot(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri, uint32_t slot) {
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slot++;
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if (pri == HAL_TRANSQ_PRI_HIGH) {
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if (slot >= TRANSQ_SLOT_NUM) {
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slot = TRANSQ_SLOT_NUM - transq_cfg[id].slot.tx_num[pri];
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}
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} else {
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if (slot >= transq_cfg[id].slot.tx_num[pri]) {
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slot = 0;
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}
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}
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return slot;
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}
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static void hal_transq_remote_irq_handler(void) {
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enum HAL_TRANSQ_ID_T id;
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enum HAL_TRANSQ_PRI_T pri;
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uint32_t status;
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uint32_t slot;
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#if (CHIP_HAS_TRANSQ > 1)
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IRQn_Type irq = NVIC_GetCurrentActiveIRQ();
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for (id = HAL_TRANSQ_ID_0; id < HAL_TRANSQ_ID_QTY; id++) {
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if (irq == remote_irq_num[id]) {
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break;
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}
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}
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if (id >= HAL_TRANSQ_ID_QTY) {
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return;
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}
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#else
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id = HAL_TRANSQ_ID_0;
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#endif
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while ((status = peer_transq[id]->RMT_MIS) != 0) {
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slot = next_rx_slot[id][HAL_TRANSQ_PRI_HIGH];
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if (slot < TRANSQ_SLOT_NUM && (status & (1 << slot))) {
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pri = HAL_TRANSQ_PRI_HIGH;
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} else {
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pri = HAL_TRANSQ_PRI_NORMAL;
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slot = next_rx_slot[id][HAL_TRANSQ_PRI_NORMAL];
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ASSERT(slot < TRANSQ_SLOT_NUM && (status & (1 << slot)),
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"TRANSQ-%d: Rx IRQ when no slot or out of order: status=0x%08x "
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"next=%d pri_next=%d",
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id, status, next_rx_slot[id][HAL_TRANSQ_PRI_NORMAL],
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next_rx_slot[id][HAL_TRANSQ_PRI_HIGH]);
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}
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// Mask IRQ from corresponding slots
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peer_transq[id]->RMT_INTMASK &= ~rx_irq_mask[id][pri];
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if (transq_cfg[id].rx_handler) {
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transq_cfg[id].rx_handler(pri);
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}
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}
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}
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static int hal_transq_active_tx_valid(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri) {
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return (active_tx_slot[id][pri] >= TRANSQ_SLOT_NUM ||
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active_tx_slot[id][pri] != next_tx_slot[id][pri] ||
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tx_slot_full[id][pri]);
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}
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static void hal_transq_local_irq_handler(void) {
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enum HAL_TRANSQ_ID_T id;
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enum HAL_TRANSQ_PRI_T pri;
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uint32_t status;
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uint32_t slot, next_slot;
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uint32_t lock;
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#if (CHIP_HAS_TRANSQ > 1)
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IRQn_Type irq = NVIC_GetCurrentActiveIRQ();
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for (id = HAL_TRANSQ_ID_0; id < HAL_TRANSQ_ID_QTY; id++) {
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if (irq == local_irq_num[id]) {
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break;
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}
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}
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if (id >= HAL_TRANSQ_ID_QTY) {
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return;
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}
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#else
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id = HAL_TRANSQ_ID_0;
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#endif
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while ((status = transq[id]->LERR_MIS) != 0) {
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transq[id]->LERR_ISC.LERR_INTCLR = status;
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ASSERT(false, "TRANSQ-%d: Tx on active slot: 0x%08x", id, status);
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}
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while ((status = transq[id]->LDONE_MIS) != 0) {
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if (transq_cfg[id].tx_handler) {
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lock = int_lock();
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ASSERT(hal_transq_active_tx_valid(id, HAL_TRANSQ_PRI_HIGH),
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"TRANSQ-%d: Corrupted pri active tx: active=%d next=%d full=%d",
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id, active_tx_slot[id][HAL_TRANSQ_PRI_HIGH],
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next_tx_slot[id][HAL_TRANSQ_PRI_HIGH],
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tx_slot_full[id][HAL_TRANSQ_PRI_HIGH]);
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ASSERT(hal_transq_active_tx_valid(id, HAL_TRANSQ_PRI_NORMAL),
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"TRANSQ-%d: Corrupted active tx: active=%d next=%d full=%d", id,
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active_tx_slot[id][HAL_TRANSQ_PRI_NORMAL],
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next_tx_slot[id][HAL_TRANSQ_PRI_NORMAL],
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tx_slot_full[id][HAL_TRANSQ_PRI_NORMAL]);
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slot = active_tx_slot[id][HAL_TRANSQ_PRI_HIGH];
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if (slot < TRANSQ_SLOT_NUM && (status & (1 << slot))) {
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pri = HAL_TRANSQ_PRI_HIGH;
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} else {
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pri = HAL_TRANSQ_PRI_NORMAL;
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slot = active_tx_slot[id][HAL_TRANSQ_PRI_NORMAL];
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ASSERT(slot < TRANSQ_SLOT_NUM && (status & (1 << slot)),
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"TRANSQ-%d: Tx done IRQ when slot empty or out of order: "
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"status=0x%08x next=%d pri_next=%d",
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id, status, active_tx_slot[id][HAL_TRANSQ_PRI_NORMAL],
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active_tx_slot[id][HAL_TRANSQ_PRI_HIGH]);
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}
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// Clear the interrupt
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transq[id]->LDONE_ISC.LDONE_INTCLR = (1 << slot);
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next_slot = get_next_tx_slot(id, pri, slot);
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if (!tx_slot_full[id][pri] && next_slot == next_tx_slot[id][pri]) {
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// No tx in progress
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active_tx_slot[id][pri] = TRANSQ_SLOT_NUM;
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} else {
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tx_slot_full[id][pri] = false;
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if (transq_cfg[id].slot.tx_num[pri] == 1) {
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// No tx in progress
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active_tx_slot[id][pri] = TRANSQ_SLOT_NUM;
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} else {
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// Some tx in progress
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active_tx_slot[id][pri] = next_slot;
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}
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}
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int_unlock(lock);
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transq_cfg[id].tx_handler(pri,
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(const uint8_t *)transq[id]->WSLOT[slot].ADDR,
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transq[id]->WSLOT[slot].LEN);
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} else {
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transq[id]->LDONE_INTMASK = 0;
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}
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}
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}
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enum HAL_TRANSQ_RET_T hal_transq_get_rx_status(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri,
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bool *ready) {
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uint32_t lock;
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uint32_t slot;
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if (id >= HAL_TRANSQ_ID_QTY) {
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return HAL_TRANSQ_RET_BAD_ID;
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}
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if (pri >= HAL_TRANSQ_PRI_QTY) {
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return HAL_TRANSQ_RET_BAD_PRI;
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}
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if (transq_cfg[id].slot.rx_num[pri] == 0) {
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return HAL_TRANSQ_RET_BAD_RX_NUM;
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}
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if (transq_cfg[id].rx_handler) {
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// Rx will be processed by IRQ handler
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return HAL_TRANSQ_RET_BAD_MODE;
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}
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lock = int_lock();
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slot = next_rx_slot[id][pri];
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if (slot < TRANSQ_SLOT_NUM &&
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peer_transq[id]->RMT_ISC.RMT_RIS & (1 << slot)) {
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*ready = true;
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} else {
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*ready = false;
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}
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int_unlock(lock);
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return HAL_TRANSQ_RET_OK;
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}
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enum HAL_TRANSQ_RET_T hal_transq_get_tx_status(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri,
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bool *done) {
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uint32_t lock;
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uint32_t slot, next_slot;
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if (id >= HAL_TRANSQ_ID_QTY) {
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return HAL_TRANSQ_RET_BAD_ID;
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}
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if (pri >= HAL_TRANSQ_PRI_QTY) {
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return HAL_TRANSQ_RET_BAD_PRI;
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}
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if (transq_cfg[id].slot.tx_num[pri] == 0) {
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return HAL_TRANSQ_RET_BAD_TX_NUM;
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}
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if (transq_cfg[id].tx_handler) {
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// Tx done will be processed by IRQ handler
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return HAL_TRANSQ_RET_BAD_MODE;
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}
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lock = int_lock();
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slot = active_tx_slot[id][pri];
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ASSERT(hal_transq_active_tx_valid(id, pri),
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"TRANSQ-%d: Corrupted active tx: pri=%d active=%d next=%d full=%d", id,
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pri, active_tx_slot[id][pri], next_tx_slot[id][pri],
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tx_slot_full[id][pri]);
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if (transq[id]->LDONE_ISC.LDONE_RIS & (1 << slot)) {
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*done = true;
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// Clear the interrupt
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transq[id]->LDONE_ISC.LDONE_INTCLR = (1 << slot);
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next_slot = get_next_tx_slot(id, pri, slot);
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if (!tx_slot_full[id][pri] && next_slot == next_tx_slot[id][pri]) {
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// No tx in progress
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active_tx_slot[id][pri] = TRANSQ_SLOT_NUM;
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} else {
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tx_slot_full[id][pri] = false;
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if (transq_cfg[id].slot.tx_num[pri] == 1) {
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// No tx in progress
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active_tx_slot[id][pri] = TRANSQ_SLOT_NUM;
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} else {
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// Some tx in progress
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active_tx_slot[id][pri] = next_slot;
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}
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}
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} else {
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*done = false;
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}
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int_unlock(lock);
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return HAL_TRANSQ_RET_OK;
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}
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enum HAL_TRANSQ_RET_T hal_transq_rx_first(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri,
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const uint8_t **data, uint32_t *len) {
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enum HAL_TRANSQ_RET_T ret;
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uint32_t slot;
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// uint32_t lock;
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if (id >= HAL_TRANSQ_ID_QTY) {
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return HAL_TRANSQ_RET_BAD_ID;
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}
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if (pri >= HAL_TRANSQ_PRI_QTY) {
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return HAL_TRANSQ_RET_BAD_PRI;
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}
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if (transq_cfg[id].slot.rx_num[pri] == 0) {
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return HAL_TRANSQ_RET_BAD_RX_NUM;
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}
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// lock = int_lock();
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slot = next_rx_slot[id][pri];
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if (slot < TRANSQ_SLOT_NUM &&
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peer_transq[id]->RMT_ISC.RMT_RIS & (1 << slot)) {
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// Msg available
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ret = HAL_TRANSQ_RET_OK;
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if (data) {
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*data = (const uint8_t *)peer_transq[id]->RSLOT[slot].ADDR;
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}
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if (len) {
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*len = peer_transq[id]->RSLOT[slot].LEN;
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}
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} else {
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// No msg. Re-enable IRQ
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ret = HAL_TRANSQ_RET_RX_EMPTY;
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if (data) {
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*data = NULL;
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}
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if (len) {
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*len = 0;
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}
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peer_transq[id]->RMT_INTMASK |= rx_irq_mask[id][pri];
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}
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// int_unlock(lock);
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return ret;
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}
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enum HAL_TRANSQ_RET_T hal_transq_rx_next(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri,
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const uint8_t **data, uint32_t *len) {
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enum HAL_TRANSQ_RET_T ret;
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uint32_t slot;
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// uint32_t lock;
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if (id >= HAL_TRANSQ_ID_QTY) {
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return HAL_TRANSQ_RET_BAD_ID;
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}
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if (pri >= HAL_TRANSQ_PRI_QTY) {
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return HAL_TRANSQ_RET_BAD_PRI;
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}
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if (transq_cfg[id].slot.rx_num[pri] == 0) {
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return HAL_TRANSQ_RET_BAD_RX_NUM;
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}
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ret = HAL_TRANSQ_RET_OK;
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// lock = int_lock();
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slot = next_rx_slot[id][pri];
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if (slot < TRANSQ_SLOT_NUM &&
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peer_transq[id]->RMT_ISC.RMT_RIS & (1 << slot)) {
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// Clear cur IRQ
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peer_transq[id]->RMT_ISC.RMT_INTCLR = (1 << slot);
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// Update next_rx_slot
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slot = get_next_rx_slot(id, pri, slot);
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next_rx_slot[id][pri] = slot;
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if (slot < TRANSQ_SLOT_NUM &&
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peer_transq[id]->RMT_ISC.RMT_RIS & (1 << slot)) {
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// Next msg available
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if (data) {
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*data = (const uint8_t *)peer_transq[id]->RSLOT[slot].ADDR;
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}
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if (len) {
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*len = peer_transq[id]->RSLOT[slot].LEN;
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}
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} else {
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// No msg
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ret = HAL_TRANSQ_RET_RX_EMPTY;
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}
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} else {
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// No msg
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ret = HAL_TRANSQ_RET_RX_EMPTY;
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}
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if (ret == HAL_TRANSQ_RET_RX_EMPTY) {
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if (data) {
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*data = NULL;
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}
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if (len) {
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*len = 0;
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}
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// Re-enable IRQ
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peer_transq[id]->RMT_INTMASK |= rx_irq_mask[id][pri];
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}
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// int_unlock(lock);
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return ret;
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}
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enum HAL_TRANSQ_RET_T hal_transq_tx(enum HAL_TRANSQ_ID_T id,
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enum HAL_TRANSQ_PRI_T pri,
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const uint8_t *data, uint32_t len) {
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enum HAL_TRANSQ_RET_T ret;
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uint32_t lock;
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uint32_t slot;
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if (id >= HAL_TRANSQ_ID_QTY) {
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return HAL_TRANSQ_RET_BAD_ID;
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}
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if (pri >= HAL_TRANSQ_PRI_QTY) {
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return HAL_TRANSQ_RET_BAD_PRI;
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}
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if (transq_cfg[id].slot.tx_num[pri] == 0) {
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return HAL_TRANSQ_RET_BAD_TX_NUM;
|
|
}
|
|
|
|
lock = int_lock();
|
|
|
|
if (tx_slot_full[id][pri]) {
|
|
ret = HAL_TRANSQ_RET_TX_FULL;
|
|
} else {
|
|
ret = HAL_TRANSQ_RET_OK;
|
|
|
|
slot = next_tx_slot[id][pri];
|
|
|
|
transq[id]->WSLOT[slot].ADDR = (uint32_t)data;
|
|
transq[id]->WSLOT[slot].LEN = len;
|
|
transq[id]->RMT_INTSET = (1 << slot);
|
|
|
|
// Update active_tx_slot if this is the only tx in progress
|
|
if (active_tx_slot[id][pri] >= TRANSQ_SLOT_NUM) {
|
|
active_tx_slot[id][pri] = slot;
|
|
}
|
|
|
|
// Update next_tx_slot
|
|
next_tx_slot[id][pri] = get_next_tx_slot(id, pri, slot);
|
|
|
|
if (next_tx_slot[id][pri] == active_tx_slot[id][pri]) {
|
|
tx_slot_full[id][pri] = true;
|
|
}
|
|
}
|
|
|
|
int_unlock(lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
enum HAL_TRANSQ_RET_T
|
|
hal_transq_update_num(enum HAL_TRANSQ_ID_T id,
|
|
const struct HAL_TRANSQ_SLOT_NUM_T *slot) {
|
|
uint32_t tx_mask;
|
|
|
|
if (id >= HAL_TRANSQ_ID_QTY) {
|
|
return HAL_TRANSQ_RET_BAD_ID;
|
|
}
|
|
if (slot == NULL) {
|
|
return HAL_TRANSQ_RET_BAD_SLOT;
|
|
}
|
|
if (slot->tx_num[HAL_TRANSQ_PRI_NORMAL] + slot->tx_num[HAL_TRANSQ_PRI_HIGH] >
|
|
TRANSQ_SLOT_NUM) {
|
|
return HAL_TRANSQ_RET_BAD_TX_NUM;
|
|
}
|
|
if (slot->rx_num[HAL_TRANSQ_PRI_NORMAL] + slot->rx_num[HAL_TRANSQ_PRI_HIGH] >
|
|
TRANSQ_SLOT_NUM) {
|
|
return HAL_TRANSQ_RET_BAD_RX_NUM;
|
|
}
|
|
|
|
transq_cfg[id].slot = *slot;
|
|
|
|
rx_irq_mask[id][HAL_TRANSQ_PRI_NORMAL] =
|
|
construct_mask(0, slot->rx_num[HAL_TRANSQ_PRI_NORMAL]);
|
|
rx_irq_mask[id][HAL_TRANSQ_PRI_HIGH] =
|
|
construct_mask(TRANSQ_SLOT_NUM - slot->rx_num[HAL_TRANSQ_PRI_HIGH],
|
|
slot->rx_num[HAL_TRANSQ_PRI_HIGH]);
|
|
|
|
tx_mask = construct_mask(0, slot->tx_num[HAL_TRANSQ_PRI_NORMAL]) |
|
|
construct_mask(TRANSQ_SLOT_NUM - slot->tx_num[HAL_TRANSQ_PRI_HIGH],
|
|
slot->tx_num[HAL_TRANSQ_PRI_HIGH]);
|
|
|
|
transq[id]->RMT_INTMASK = tx_mask;
|
|
transq[id]->LERR_INTMASK = tx_mask;
|
|
if (transq_cfg[id].tx_handler) {
|
|
transq[id]->LDONE_INTMASK = tx_mask;
|
|
} else {
|
|
transq[id]->LDONE_INTMASK = 0;
|
|
}
|
|
|
|
return HAL_TRANSQ_RET_OK;
|
|
}
|
|
|
|
enum HAL_TRANSQ_RET_T hal_transq_open(enum HAL_TRANSQ_ID_T id,
|
|
const struct HAL_TRANSQ_CFG_T *cfg) {
|
|
const struct HAL_TRANSQ_SLOT_NUM_T *slot;
|
|
uint32_t ctrl;
|
|
enum HAL_TRANSQ_RET_T ret;
|
|
|
|
if (id >= HAL_TRANSQ_ID_QTY) {
|
|
return HAL_TRANSQ_RET_BAD_ID;
|
|
}
|
|
if (cfg == NULL) {
|
|
return HAL_TRANSQ_RET_BAD_CFG;
|
|
}
|
|
|
|
#ifdef CHIP_BEST2000
|
|
hal_cmu_clock_enable(HAL_CMU_MOD_P_TRANSQ_WF);
|
|
hal_cmu_reset_clear(HAL_CMU_MOD_P_TRANSQ_WF);
|
|
#elif defined(CHIP_BEST2001) && !defined(CHIP_BEST2001_DSP)
|
|
// 2001 dsp has enable transq clk at hal_cmu_dsp_clock_enable()
|
|
hal_cmu_clock_enable(HAL_CMU_MOD_P_TQWF);
|
|
hal_cmu_reset_clear(HAL_CMU_MOD_P_TQWF);
|
|
hal_cmu_clock_enable(HAL_CMU_MOD_P_TQA7);
|
|
hal_cmu_reset_clear(HAL_CMU_MOD_P_TQA7);
|
|
#endif
|
|
|
|
transq_cfg[id] = *cfg;
|
|
|
|
slot = &cfg->slot;
|
|
|
|
ret = hal_transq_update_num(id, slot);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
next_tx_slot[id][HAL_TRANSQ_PRI_NORMAL] =
|
|
slot->tx_num[HAL_TRANSQ_PRI_NORMAL] ? 0 : TRANSQ_SLOT_NUM;
|
|
active_tx_slot[id][HAL_TRANSQ_PRI_NORMAL] = TRANSQ_SLOT_NUM;
|
|
tx_slot_full[id][HAL_TRANSQ_PRI_NORMAL] = false;
|
|
next_rx_slot[id][HAL_TRANSQ_PRI_NORMAL] =
|
|
slot->rx_num[HAL_TRANSQ_PRI_NORMAL] ? 0 : TRANSQ_SLOT_NUM;
|
|
|
|
next_tx_slot[id][HAL_TRANSQ_PRI_HIGH] =
|
|
slot->tx_num[HAL_TRANSQ_PRI_HIGH]
|
|
? (TRANSQ_SLOT_NUM - slot->tx_num[HAL_TRANSQ_PRI_HIGH])
|
|
: TRANSQ_SLOT_NUM;
|
|
active_tx_slot[id][HAL_TRANSQ_PRI_HIGH] = TRANSQ_SLOT_NUM;
|
|
tx_slot_full[id][HAL_TRANSQ_PRI_HIGH] = false;
|
|
next_rx_slot[id][HAL_TRANSQ_PRI_HIGH] =
|
|
slot->rx_num[HAL_TRANSQ_PRI_HIGH]
|
|
? (TRANSQ_SLOT_NUM - slot->rx_num[HAL_TRANSQ_PRI_HIGH])
|
|
: TRANSQ_SLOT_NUM;
|
|
|
|
transq[id]->LDONE_ISC.LDONE_INTCLR = ~0UL;
|
|
transq[id]->LERR_ISC.LERR_INTCLR = ~0UL;
|
|
transq[id]->RMT_ISC.RMT_INTCLR = ~0UL;
|
|
|
|
ctrl = CTRL_REMOTE_IRQ_EN | CTRL_LOCAL_ERR_IRQ_EN;
|
|
if (cfg->tx_handler) {
|
|
ctrl |= CTRL_LOCAL_DONE_IRQ_EN;
|
|
}
|
|
transq[id]->CTRL = ctrl;
|
|
|
|
if (cfg->rx_handler) {
|
|
NVIC_SetVector(remote_irq_num[id], (uint32_t)hal_transq_remote_irq_handler);
|
|
NVIC_SetPriority(remote_irq_num[id], IRQ_PRIORITY_NORMAL);
|
|
NVIC_ClearPendingIRQ(remote_irq_num[id]);
|
|
NVIC_EnableIRQ(remote_irq_num[id]);
|
|
}
|
|
|
|
NVIC_SetVector(local_irq_num[id], (uint32_t)hal_transq_local_irq_handler);
|
|
NVIC_SetPriority(local_irq_num[id], IRQ_PRIORITY_NORMAL);
|
|
NVIC_ClearPendingIRQ(local_irq_num[id]);
|
|
NVIC_EnableIRQ(local_irq_num[id]);
|
|
|
|
return HAL_TRANSQ_RET_OK;
|
|
}
|
|
|
|
enum HAL_TRANSQ_RET_T hal_transq_close(enum HAL_TRANSQ_ID_T id) {
|
|
if (id >= HAL_TRANSQ_ID_QTY) {
|
|
return HAL_TRANSQ_RET_BAD_ID;
|
|
}
|
|
|
|
transq[id]->CTRL = 0;
|
|
NVIC_DisableIRQ(remote_irq_num[id]);
|
|
NVIC_DisableIRQ(local_irq_num[id]);
|
|
|
|
return HAL_TRANSQ_RET_OK;
|
|
}
|
|
|
|
#endif // CHIP_HAS_TRANSQ
|