528 lines
18 KiB
C
528 lines
18 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "hal_tdm.h"
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#include "hal_dma.h"
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#include "hal_i2s.h"
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#include "hal_trace.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#ifndef CHIP_HAS_TDM
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#include "hal_i2s_tdm.h"
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#endif
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#if 0
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#define TDM_TRACE TRACE
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#define TDM_DUMP8 DUMP8
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#else
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#define TDM_TRACE(n, str, ...)
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#define TDM_DUMP8(str, ...)
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#endif
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#ifdef CHIP_HAS_TDM
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static const char *const invalid_id = "Invalid I2S ID: %d\n";
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static inline uint32_t _tdm_get_reg_base(enum HAL_I2S_ID_T id) {
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ASSERT(id < HAL_I2S_ID_QTY, invalid_id, id);
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switch (id) {
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case HAL_I2S_ID_0:
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return (I2S0_BASE | I2SIP_TDM_CTRL_REG_OFFSET);
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break;
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#if defined(CHIP_HAS_I2S) && (CHIP_HAS_I2S > 1)
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case HAL_I2S_ID_1:
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return (I2S1_BASE | I2SIP_TDM_CTRL_REG_OFFSET);
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break;
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#endif
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default:
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break;
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}
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return 0;
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}
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static inline bool tdm_slot_cycles_in_arrays(uint8_t slot_cycles) {
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if (slot_cycles == (uint8_t)HAL_TDM_SLOT_CYCLES_16 ||
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slot_cycles == (uint8_t)HAL_TDM_SLOT_CYCLES_32)
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return true;
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else
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return false;
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}
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static inline bool tdm_cycles_in_arrays(uint16_t cycles) {
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if (cycles == (uint16_t)HAL_TDM_CYCLES_16 ||
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cycles == (uint16_t)HAL_TDM_CYCLES_32 ||
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cycles == (uint16_t)HAL_TDM_CYCLES_64 ||
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cycles == (uint16_t)HAL_TDM_CYCLES_128 ||
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cycles == (uint16_t)HAL_TDM_CYCLES_256)
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return true;
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else
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return false;
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}
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static inline bool tdm_fs_cycles_in_arrays(uint16_t fs_cycles) {
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if (fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_1 ||
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fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_8 ||
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fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_16 ||
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fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_32 ||
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fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_64 ||
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fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_128 ||
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fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_ONE_LESS)
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return true;
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else
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return false;
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}
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static void tdm_get_config(enum HAL_I2S_ID_T i2s_id,
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struct HAL_TDM_CONFIG_T *tdm_config) {
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volatile uint32_t *base_addr;
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uint32_t val;
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base_addr = (uint32_t *)_tdm_get_reg_base(i2s_id);
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val = *base_addr;
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if ((val & (TDM_MODE_FS_ASSERTED_AT_LAST << TDM_MODE_FS_ASSERTED_SHIFT)) ==
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(TDM_MODE_FS_ASSERTED_AT_LAST << TDM_MODE_FS_ASSERTED_SHIFT)) {
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tdm_config->mode = HAL_TDM_MODE_FS_ASSERTED_AT_LAST;
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} else {
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tdm_config->mode = HAL_TDM_MODE_FS_ASSERTED_AT_FIRST;
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}
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if ((val & (TDM_FS_EDGE_NEGEDGE << TDM_FS_EDGE_SHIFT)) ==
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(TDM_FS_EDGE_NEGEDGE << TDM_FS_EDGE_SHIFT)) {
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tdm_config->edge = HAL_TDM_FS_EDGE_NEGEDGE;
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} else {
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tdm_config->edge = HAL_TDM_FS_EDGE_POSEDGE;
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}
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if ((val & (TDM_FRAME_WIDTH_16_CYCLES << TDM_FRAME_WIDTH_SHIFT)) ==
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(TDM_FRAME_WIDTH_16_CYCLES << TDM_FRAME_WIDTH_SHIFT)) {
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tdm_config->cycles = HAL_TDM_CYCLES_16;
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} else if ((val & (TDM_FRAME_WIDTH_32_CYCLES << TDM_FRAME_WIDTH_SHIFT)) ==
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(TDM_FRAME_WIDTH_32_CYCLES << TDM_FRAME_WIDTH_SHIFT)) {
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tdm_config->cycles = HAL_TDM_CYCLES_32;
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} else if ((val & (TDM_FRAME_WIDTH_64_CYCLES << TDM_FRAME_WIDTH_SHIFT)) ==
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(TDM_FRAME_WIDTH_64_CYCLES << TDM_FRAME_WIDTH_SHIFT)) {
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tdm_config->cycles = HAL_TDM_CYCLES_64;
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} else if ((val & (TDM_FRAME_WIDTH_128_CYCLES << TDM_FRAME_WIDTH_SHIFT)) ==
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(TDM_FRAME_WIDTH_128_CYCLES << TDM_FRAME_WIDTH_SHIFT)) {
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tdm_config->cycles = HAL_TDM_CYCLES_128;
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} else if ((val & (TDM_FRAME_WIDTH_256_CYCLES << TDM_FRAME_WIDTH_SHIFT)) ==
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(TDM_FRAME_WIDTH_256_CYCLES << TDM_FRAME_WIDTH_SHIFT)) {
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tdm_config->cycles = HAL_TDM_CYCLES_256;
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} else {
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tdm_config->cycles = HAL_TDM_CYCLES_256;
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}
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if ((val & (TDM_FS_WIDTH_8_CYCLES << TDM_FS_WIDTH_SHIFT)) ==
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(TDM_FS_WIDTH_8_CYCLES << TDM_FS_WIDTH_SHIFT)) {
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_8;
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} else if ((val & (TDM_FS_WIDTH_16_CYCLES << TDM_FS_WIDTH_SHIFT)) ==
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(TDM_FS_WIDTH_16_CYCLES << TDM_FS_WIDTH_SHIFT)) {
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_16;
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} else if ((val & (TDM_FS_WIDTH_32_CYCLES << TDM_FS_WIDTH_SHIFT)) ==
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(TDM_FS_WIDTH_32_CYCLES << TDM_FS_WIDTH_SHIFT)) {
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_32;
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} else if ((val & (TDM_FS_WIDTH_64_CYCLES << TDM_FS_WIDTH_SHIFT)) ==
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(TDM_FS_WIDTH_64_CYCLES << TDM_FS_WIDTH_SHIFT)) {
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_64;
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} else if ((val & (TDM_FS_WIDTH_128_CYCLES << TDM_FS_WIDTH_SHIFT)) ==
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(TDM_FS_WIDTH_128_CYCLES << TDM_FS_WIDTH_SHIFT)) {
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_128;
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} else if ((val & (TDM_FS_WIDTH_1_CYCLE << TDM_FS_WIDTH_SHIFT)) ==
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(TDM_FS_WIDTH_1_CYCLE << TDM_FS_WIDTH_SHIFT)) {
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_ONE_LESS;
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} else {
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_ONE_LESS;
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}
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if ((val & (TDM_SLOT_WIDTH_16_BIT << TDM_SLOT_WIDTH_SHIFT)) ==
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(TDM_SLOT_WIDTH_16_BIT << TDM_SLOT_WIDTH_SHIFT)) {
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tdm_config->slot_cycles = HAL_TDM_SLOT_CYCLES_16;
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} else {
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tdm_config->slot_cycles = HAL_TDM_SLOT_CYCLES_32;
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}
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tdm_config->data_offset = ((val >> TDM_DATA_OFFSET_SHIT) & 0x7);
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}
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static void tdm_set_config(enum HAL_I2S_ID_T i2s_id,
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struct HAL_TDM_CONFIG_T *tdm_config) {
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volatile uint32_t *base_addr;
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uint32_t val = 0;
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base_addr = (uint32_t *)_tdm_get_reg_base(i2s_id);
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ASSERT(tdm_config->mode < HAL_TDM_MODE_NUM, "%s: mode = %d error!", __func__,
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tdm_config->mode);
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ASSERT(tdm_config->edge < HAL_TDM_FS_EDGE_NUM, "%s: edge = %d error!",
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__func__, tdm_config->edge);
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ASSERT(tdm_cycles_in_arrays((uint16_t)tdm_config->cycles),
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"%s: cycles = %d error!", __func__, tdm_config->cycles);
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ASSERT(tdm_fs_cycles_in_arrays((uint16_t)tdm_config->fs_cycles),
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"%s: fs_cycles = %d cycles = %d error!", __func__,
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tdm_config->fs_cycles, tdm_config->cycles);
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ASSERT(tdm_slot_cycles_in_arrays((uint8_t)tdm_config->slot_cycles),
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"%s: slot_cycles = %d error!", __func__, tdm_config->slot_cycles);
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if (tdm_config->mode == HAL_TDM_MODE_FS_ASSERTED_AT_LAST) {
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val |= (TDM_MODE_FS_ASSERTED_AT_LAST << TDM_MODE_FS_ASSERTED_SHIFT);
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}
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if (tdm_config->edge == HAL_TDM_FS_EDGE_NEGEDGE) {
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val |= (TDM_FS_EDGE_NEGEDGE << TDM_FS_EDGE_SHIFT);
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}
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if (tdm_config->cycles == HAL_TDM_CYCLES_16) {
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val |= (TDM_FRAME_WIDTH_16_CYCLES << TDM_FRAME_WIDTH_SHIFT);
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} else if (tdm_config->cycles == HAL_TDM_CYCLES_32) {
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val |= (TDM_FRAME_WIDTH_32_CYCLES << TDM_FRAME_WIDTH_SHIFT);
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} else if (tdm_config->cycles == HAL_TDM_CYCLES_64) {
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val |= (TDM_FRAME_WIDTH_64_CYCLES << TDM_FRAME_WIDTH_SHIFT);
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} else if (tdm_config->cycles == HAL_TDM_CYCLES_128) {
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val |= (TDM_FRAME_WIDTH_128_CYCLES << TDM_FRAME_WIDTH_SHIFT);
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} else {
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val |= (TDM_FRAME_WIDTH_256_CYCLES << TDM_FRAME_WIDTH_SHIFT);
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}
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if (tdm_config->fs_cycles == HAL_TDM_FS_CYCLES_8) {
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val |= (TDM_FS_WIDTH_8_CYCLES << TDM_FS_WIDTH_SHIFT);
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} else if (tdm_config->fs_cycles == HAL_TDM_FS_CYCLES_16) {
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val |= (TDM_FS_WIDTH_16_CYCLES << TDM_FS_WIDTH_SHIFT);
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} else if (tdm_config->fs_cycles == HAL_TDM_FS_CYCLES_32) {
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val |= (TDM_FS_WIDTH_32_CYCLES << TDM_FS_WIDTH_SHIFT);
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} else if (tdm_config->fs_cycles == HAL_TDM_FS_CYCLES_64) {
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val |= (TDM_FS_WIDTH_64_CYCLES << TDM_FS_WIDTH_SHIFT);
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} else if (tdm_config->fs_cycles == HAL_TDM_FS_CYCLES_128) {
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val |= (TDM_FS_WIDTH_128_CYCLES << TDM_FS_WIDTH_SHIFT);
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} else {
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val |= (TDM_FS_WIDTH_FRAME_LENGTH_1_CYCLES << TDM_FS_WIDTH_SHIFT);
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}
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if (tdm_config->slot_cycles == HAL_TDM_SLOT_CYCLES_16) {
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val |= (TDM_SLOT_WIDTH_16_BIT << TDM_SLOT_WIDTH_SHIFT);
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}
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if (tdm_config->data_offset >= TDM_DATA_OFFSET_MIN &&
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tdm_config->data_offset <= TDM_DATA_OFFSET_MAX) {
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val |= (tdm_config->data_offset << TDM_DATA_OFFSET_SHIT);
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}
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*base_addr = val;
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}
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static void tdm_get_default_config(struct HAL_TDM_CONFIG_T *tdm_config) {
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tdm_config->mode = HAL_TDM_MODE_FS_ASSERTED_AT_FIRST;
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tdm_config->edge = HAL_TDM_FS_EDGE_POSEDGE;
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tdm_config->cycles = HAL_TDM_CYCLES_32;
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_1;
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tdm_config->slot_cycles = HAL_TDM_SLOT_CYCLES_32;
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tdm_config->data_offset = 0;
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}
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static void tdm_get_i2s_config(struct HAL_TDM_CONFIG_T *tdm_config) {
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tdm_config->mode = HAL_TDM_MODE_FS_ASSERTED_AT_LAST;
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tdm_config->edge = HAL_TDM_FS_EDGE_NEGEDGE;
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tdm_config->cycles = HAL_TDM_CYCLES_32;
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tdm_config->fs_cycles = HAL_TDM_FS_CYCLES_16;
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tdm_config->slot_cycles = HAL_TDM_SLOT_CYCLES_16;
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tdm_config->data_offset = 0;
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}
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static void tdm_enable(enum HAL_I2S_ID_T i2s_id, bool enable) {
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volatile uint32_t *base_addr;
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uint32_t val = 0;
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base_addr = (uint32_t *)_tdm_get_reg_base(i2s_id);
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val = *base_addr;
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if (enable) {
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val |= (TDM_ENABLE << TDM_ENABLE_SHIFT);
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} else {
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val &= ~(TDM_ENABLE << TDM_ENABLE_SHIFT);
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}
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*base_addr = val;
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}
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static int32_t tdm_open(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream,
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enum HAL_I2S_MODE_T mode) {
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int ret;
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struct HAL_TDM_CONFIG_T tdm_config;
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TDM_TRACE(4, "%s: i2s_id = %d, stream = %d, mode = %d.", __func__, i2s_id,
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stream, mode);
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ret = hal_i2s_open(i2s_id, stream, mode);
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if (ret) {
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TDM_TRACE(2, "%s: hal_i2s_open failed.ret = %d.", __func__, ret);
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}
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tdm_enable(i2s_id, false);
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tdm_get_default_config(&tdm_config);
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tdm_set_config(i2s_id, &tdm_config);
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TDM_TRACE(1, "%s: done.", __func__);
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return ret;
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}
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static int32_t tdm_setup_stream(enum HAL_I2S_ID_T i2s_id,
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enum AUD_STREAM_T stream, uint32_t sample_rate,
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struct HAL_TDM_CONFIG_T *tdm_cfg) {
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struct HAL_I2S_CONFIG_T i2s_cfg;
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uint32_t cycles;
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const uint8_t bits = 16;
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int ret;
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TDM_TRACE(4, "%s: i2s_id = %d, stream = %d, sample_rate = %d", __func__,
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i2s_id, stream, sample_rate);
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TDM_TRACE(5,
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"%s: tdm_cfg: mode = %d,edge = %d,cycles = %d,fs_cycles = %d,"
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"slot_cycles= %d, offs = %d.",
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__func__, tdm_cfg->mode, tdm_cfg->edge, tdm_cfg->cycles,
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tdm_cfg->fs_cycles, tdm_cfg->slot_cycles, tdm_cfg->data_offset);
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cycles = tdm_cfg->cycles;
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ASSERT(tdm_cycles_in_arrays(cycles), "%s: cycles = %d error!", __func__,
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tdm_cfg->cycles);
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memset(&i2s_cfg, 0, sizeof(i2s_cfg));
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i2s_cfg.use_dma = true;
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i2s_cfg.sync_start = tdm_cfg->sync_start;
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i2s_cfg.chan_sep_buf = false;
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i2s_cfg.bits = bits;
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i2s_cfg.channel_num = 2;
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i2s_cfg.channel_map = AUD_CHANNEL_MAP_CH0 | AUD_CHANNEL_MAP_CH1;
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i2s_cfg.sample_rate = sample_rate * (cycles / bits) / 2;
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ret = hal_i2s_setup_stream(i2s_id, stream, &i2s_cfg);
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if (ret) {
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TDM_TRACE(2, "%s: playback failed.ret = %d.", __func__, ret);
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} else {
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tdm_enable(i2s_id, false);
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tdm_set_config(i2s_id, tdm_cfg);
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}
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TDM_TRACE(1, "%s done.", __func__);
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return ret;
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}
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int32_t tdm_as_i2s_setup_stream(enum HAL_I2S_ID_T i2s_id,
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enum AUD_STREAM_T stream,
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uint32_t sample_rate) {
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struct HAL_I2S_CONFIG_T i2s_cfg;
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struct HAL_TDM_CONFIG_T tdm_cfg;
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int ret;
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TDM_TRACE(4, "%s: i2s_id = %d, stream = %d, sample_rate = 0x%x.", __func__,
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i2s_id, stream, sample_rate);
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memset(&i2s_cfg, 0, sizeof(i2s_cfg));
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i2s_cfg.use_dma = true;
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i2s_cfg.sync_start = stream == AUD_STREAM_PLAYBACK ? true : false;
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i2s_cfg.chan_sep_buf = false;
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i2s_cfg.bits = 16;
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i2s_cfg.channel_num = 2;
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i2s_cfg.channel_map = AUD_CHANNEL_MAP_CH0 | AUD_CHANNEL_MAP_CH1;
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i2s_cfg.sample_rate = sample_rate;
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ret = hal_i2s_setup_stream(i2s_id, stream, &i2s_cfg);
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if (ret) {
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TDM_TRACE(2, "%s: playback failed.ret = %d.", __func__, ret);
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} else {
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tdm_enable(i2s_id, false);
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tdm_get_i2s_config(&tdm_cfg);
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tdm_set_config(i2s_id, &tdm_cfg);
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}
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TDM_TRACE(1, "%s: done.", __func__);
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return ret;
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}
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static int32_t tdm_start_stream(enum HAL_I2S_ID_T i2s_id,
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enum AUD_STREAM_T stream) {
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int ret;
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TDM_TRACE(3, "%s: i2s_id = %d, stream = %d.", __func__, i2s_id, stream);
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tdm_enable(i2s_id, true);
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ret = hal_i2s_start_stream(i2s_id, stream);
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TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
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return ret;
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}
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static int32_t tdm_stop_stream(enum HAL_I2S_ID_T i2s_id,
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enum AUD_STREAM_T stream) {
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int ret;
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TDM_TRACE(3, "%s: i2s_id = %d, stream = %d.", __func__, i2s_id, stream);
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tdm_enable(i2s_id, false);
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ret = hal_i2s_stop_stream(i2s_id, stream);
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TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
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return ret;
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}
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static int32_t tdm_close(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream) {
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int ret;
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TDM_TRACE(3, "%s: i2s_id = %d, stream = %d.", __func__, i2s_id, stream);
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tdm_enable(i2s_id, false);
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ret = hal_i2s_close(i2s_id, stream);
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TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
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return ret;
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}
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#endif // CHIP_HAS_TDM
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int32_t hal_tdm_open(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream,
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enum HAL_I2S_MODE_T mode) {
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int ret;
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|
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TDM_TRACE(3, "hal_tdm_open:i2s_id = %d, stream = %d, mode = %d.", i2s_id,
|
|
stream, mode);
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ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
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|
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#ifdef CHIP_HAS_TDM
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ret = tdm_open(i2s_id, stream, mode);
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#else
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ASSERT(stream == AUD_STREAM_CAPTURE, "stream = AUD_STREAM_PLAYBACK!");
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ret = hal_i2s_tdm_open(i2s_id, mode);
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#endif
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|
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TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
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return ret;
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}
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|
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int32_t hal_tdm_setup_stream(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream,
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uint32_t sample_rate,
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struct HAL_TDM_CONFIG_T *tdm_cfg) {
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|
int ret;
|
|
|
|
TDM_TRACE(4, "%s:i2s_id = %d, stream = %d, sample_rate = %d.", __func__,
|
|
i2s_id, stream, sample_rate);
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|
ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
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TDM_TRACE(4, "%s: cycles = %d, fs_cycles = %d,slot_cycles = %d.", __func__,
|
|
tdm_cfg->cycles, tdm_cfg->fs_cycles, tdm_cfg->slot_cycles);
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|
|
|
#ifdef CHIP_HAS_TDM
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|
ret = tdm_setup_stream(i2s_id, stream, sample_rate, tdm_cfg);
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#else
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struct HAL_I2S_TDM_CONFIG_T i2s_tdm_cfg;
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|
|
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i2s_tdm_cfg.cycles = (enum HAL_I2S_TDM_CYCLES_T)tdm_cfg->cycles;
|
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i2s_tdm_cfg.fs_cycles = (enum HAL_I2S_TDM_FS_CYCLES_T)tdm_cfg->fs_cycles;
|
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i2s_tdm_cfg.slot_cycles =
|
|
(enum HAL_I2S_TDM_SLOT_CYCLES_T)tdm_cfg->slot_cycles;
|
|
i2s_tdm_cfg.data_offset = tdm_cfg->data_offset;
|
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ret = hal_i2s_tdm_setup(i2s_id, sample_rate, &i2s_tdm_cfg);
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#endif
|
|
|
|
TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
int32_t hal_tdm_as_i2s_setup_stream(enum HAL_I2S_ID_T i2s_id,
|
|
enum AUD_STREAM_T stream,
|
|
uint32_t sample_rate) {
|
|
int ret;
|
|
|
|
TDM_TRACE(4, "%s: i2s_id = %d, stream = %d, sample_rate = %d.", __func__,
|
|
i2s_id, stream, sample_rate);
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
|
|
|
|
// i2s setup stream playback and capture.
|
|
#ifdef CHIP_HAS_TDM
|
|
ret = tdm_as_i2s_setup_stream(i2s_id, stream, sample_rate);
|
|
#else
|
|
struct HAL_I2S_TDM_CONFIG_T i2s_tdm_cfg = {
|
|
HAL_I2S_TDM_CYCLES_32,
|
|
HAL_I2S_TDM_FS_CYCLES_16,
|
|
HAL_I2S_TDM_SLOT_CYCLES_16,
|
|
};
|
|
ret = hal_i2s_tdm_setup(i2s_id, sample_rate, &i2s_tdm_cfg);
|
|
#endif
|
|
|
|
TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
int32_t hal_tdm_start_stream(enum HAL_I2S_ID_T i2s_id,
|
|
enum AUD_STREAM_T stream) {
|
|
int ret;
|
|
|
|
TDM_TRACE(3, "%s: i2s_id = %d stream = %d.", __func__, i2s_id, stream);
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
|
|
|
|
#ifdef CHIP_HAS_TDM
|
|
ret = tdm_start_stream(i2s_id, stream);
|
|
#else
|
|
ret = hal_i2s_tdm_start_stream(i2s_id);
|
|
#endif
|
|
TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
int32_t hal_tdm_stop_stream(enum HAL_I2S_ID_T i2s_id,
|
|
enum AUD_STREAM_T stream) {
|
|
int32_t ret;
|
|
|
|
TDM_TRACE(3, "%s: i2s_id = %d stream = %d.", __func__, i2s_id, stream);
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
|
|
#ifdef CHIP_HAS_TDM
|
|
ret = tdm_stop_stream(i2s_id, stream);
|
|
#else
|
|
ret = hal_i2s_tdm_stop_stream(i2s_id);
|
|
#endif
|
|
TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
int32_t hal_tdm_close(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream) {
|
|
int32_t ret;
|
|
|
|
TDM_TRACE(3, "%s: i2s_id = %d stream = %d.", __func__, i2s_id, stream);
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
|
|
#ifdef CHIP_HAS_TDM
|
|
ret = tdm_close(i2s_id, stream);
|
|
#else
|
|
ret = hal_i2s_tdm_close(i2s_id);
|
|
#endif
|
|
TDM_TRACE(2, "%s done. ret = %d.", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
void hal_tdm_get_config(enum HAL_I2S_ID_T i2s_id,
|
|
struct HAL_TDM_CONFIG_T *tdm_cfg) {
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
|
|
#ifdef CHIP_HAS_TDM
|
|
tdm_get_config(i2s_id, tdm_cfg);
|
|
#else
|
|
struct HAL_I2S_TDM_CONFIG_T i2s_tdm_cfg;
|
|
hal_i2s_tdm_get_config(i2s_id, &i2s_tdm_cfg);
|
|
tdm_cfg->mode = HAL_TDM_MODE_FS_ASSERTED_AT_FIRST;
|
|
tdm_cfg->edge = HAL_TDM_FS_EDGE_POSEDGE;
|
|
tdm_cfg->cycles = (enum HAL_TDM_CYCLES_T)i2s_tdm_cfg.cycles;
|
|
tdm_cfg->fs_cycles = (enum HAL_TDM_FS_CYCLES)i2s_tdm_cfg.fs_cycles;
|
|
tdm_cfg->slot_cycles = (enum HAL_TDM_SLOT_CYCLES_T)i2s_tdm_cfg.slot_cycles;
|
|
tdm_cfg->data_offset = i2s_tdm_cfg.data_offset;
|
|
#endif
|
|
}
|
|
|
|
void hal_tdm_set_config(enum HAL_I2S_ID_T i2s_id,
|
|
struct HAL_TDM_CONFIG_T *tdm_cfg) {
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY, "%s: i2s_id = %d!", __func__, i2s_id);
|
|
#ifdef CHIP_HAS_TDM
|
|
tdm_set_config(i2s_id, tdm_cfg);
|
|
#else
|
|
struct HAL_I2S_TDM_CONFIG_T i2s_tdm_cfg;
|
|
i2s_tdm_cfg.cycles = HAL_I2S_TDM_CYCLES_32;
|
|
i2s_tdm_cfg.fs_cycles = HAL_I2S_TDM_FS_CYCLES_16;
|
|
i2s_tdm_cfg.slot_cycles = HAL_I2S_TDM_SLOT_CYCLES_16;
|
|
i2s_tdm_cfg.data_offset = 0;
|
|
hal_i2s_tdm_set_config(i2s_id, &i2s_tdm_cfg);
|
|
#endif
|
|
}
|