218 lines
6.5 KiB
C
218 lines
6.5 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __HAL_PSRAMIP_V1_H__
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#define __HAL_PSRAMIP_V1_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "plat_types.h"
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#include "reg_psramip_v1.h"
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#define PSRIP_KEY (0x55000000)
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#define psramip_read8(reg_base,a) \
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(*(volatile unsigned char*)((reg_base)+(a)))
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#define psramip_read32(reg_base,a) \
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(*(volatile unsigned int *)((reg_base)+(a)))
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#define psramip_write32(v,reg_base,a) \
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((*(volatile unsigned int *)((reg_base)+(a))) = v)
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#define PSRAM_STAT_BUSY (0x01)
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#define PSRAM_STAT_TXFIFO_EMPTY (0x02)
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#define PSRAM_STAT_TXFIFO_FULL (0x04)
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#define PSRAM_STAT_RXFIFO_EMPTY (0x08)
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#define PSRAM_STAT_RXFIFO_COUNT (0x1f << 4)
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/* ip ops */
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#if 1
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inline static void psramip_w_cmd_addr(uint32_t reg_base, uint32_t cmd, uint32_t addr)
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{
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psramip_write32(cmd<<PSRIP_CMD_ADDR_CMD_SHIFT | addr<<PSRIP_CMD_ADDR_ADDR_SHIFT, reg_base, PSRIP_CMD_ADDR_REG_OFFSET);
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}
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#endif
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inline static uint32_t psramip_r_busy(uint32_t reg_base)
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{
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return (psramip_read32(reg_base, PSRIP_STAT_REG_OFFSET) & PSRIP_STAT_BUSY_MASK);
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}
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inline static uint32_t psramip_r_sleep_wakeup_state(uint32_t reg_base)
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{
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return (psramip_read32(reg_base, PSRIP_SPWKUPCTRL1_REG_OFFSET) & PSRIP_SPWKUPCTRL1_SLP_WKUP_MASK);
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}
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inline static uint32_t psramip_r_exit_sleep_onprocess(uint32_t reg_base)
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{
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return (psramip_read32(reg_base, PSRIP_SPWKUPCTRL1_REG_OFFSET) & PSRIP_SPWKUPCTRL1_ONPROCESS_MASK);
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}
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inline static uint32_t psramip_r_calibst(uint32_t reg_base)
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{
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return (psramip_read32(reg_base, PSRIP_MODECALIBR_REG_OFFSET) & PSRIP_MODECALIBR_CALIBST_MASK);
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}
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inline static uint32_t psramip_w_exit_sleep(uint32_t reg_base)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_SPWKUPCTRL1_REG_OFFSET);
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val |= (PSRIP_SPWKUPCTRL1_ONPROCESS_MASK);
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psramip_write32(val, reg_base, PSRIP_SPWKUPCTRL1_REG_OFFSET);
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psramip_r_busy(reg_base);
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return 0;
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}
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inline static uint32_t psramip_w_wrap_mode_enable(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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if (v)
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val |= (PSRIP_SPWKUPCTRL2_WRAP_MODE_ENABLE_MASK);
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else
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val &= ~(PSRIP_SPWKUPCTRL2_WRAP_MODE_ENABLE_MASK);
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val |= (PSRIP_KEY);
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psramip_write32(val, reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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return 0;
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}
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inline static uint32_t psramip_w_1kwrap_mode(uint32_t reg_base)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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val |= (PSRIP_SPWKUPCTRL2_1KWRAPTYPE_MODE_MASK);
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val |= (PSRIP_KEY);
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psramip_write32(val, reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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return 0;
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}
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inline static uint32_t psramip_w_32bytewrap_mode(uint32_t reg_base)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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val &= ~(PSRIP_SPWKUPCTRL2_32BYTEWRAPTYPE_MODE_MASK);
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val |= (PSRIP_KEY);
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psramip_write32(val, reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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return 0;
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}
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inline static uint32_t psramip_w_dqs_wr_sel(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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val &= ~(PSRIP_MODECALIBR_DQS_WR_SEL_MASK);
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val |= (PSRIP_KEY | (v<<PSRIP_MODECALIBR_DQS_WR_SEL_SHIFT));
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psramip_write32(val, reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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return 0;
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}
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inline static uint32_t psramip_w_dqs_rd_sel(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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val &= ~(PSRIP_MODECALIBR_DQS_RD_SEL_MASK);
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val |= (PSRIP_KEY | (v<<PSRIP_MODECALIBR_DQS_RD_SEL_SHIFT));
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psramip_write32(val, reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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return 0;
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}
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inline static void psramip_w_enable_and_trigger_calib(uint32_t reg_base)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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val |= (PSRIP_KEY | PSRIP_MODECALIBR_ENABLE_CALIB_MASK | PSRIP_MODECALIBR_TRIGGER_MASK);
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psramip_write32(val, reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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}
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#if 0
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inline static void psramip_w_enable_calib(uint32_t reg_base)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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val |= (PSRIP_KEY | PSRIP_MODECALIBR_ENABLE_CALIB_MASK);
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psramip_write32(val, reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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}
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inline static void psramip_w_trigger_calib(uint32_t reg_base)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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val |= (PSRIP_KEY | PSRIP_MODECALIBR_TRIGGER_MASK);
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psramip_write32(val, reg_base, PSRIP_MODECALIBR_REG_OFFSET);
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}
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#endif
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#if 0
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/* removed */
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inline static void psramip_w_phy_enable(uint32_t reg_base, uint32_t v)
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{
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if (v)
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psramip_write32(1, reg_base, PSRIP_PHYOCTR_REG_OFFSET);
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else
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psramip_write32(0, reg_base, PSRIP_PHYOCTR_REG_OFFSET);
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}
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#endif
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inline static void psramip_w_tx_fifo(uint32_t reg_base, uint32_t v)
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{
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psramip_write32(v, reg_base, PSRIP_TX_DATA_REG_OFFSET);
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}
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inline static void psramip_w_acc_size(uint32_t reg_base, uint32_t v)
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{
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psramip_write32(v<<PSRIP_ACCSIZE_SIZE_SHIFT, reg_base, PSRIP_ACCSIZE_REG_OFFSET);
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}
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inline static uint32_t psramip_r_rx_fifo(uint32_t reg_base)
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{
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return psramip_read32(reg_base, PSRIP_RX_DATA_REG_OFFSET);
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}
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inline static uint32_t psramip_r_status(uint32_t reg_base)
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{
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return psramip_read32(reg_base, PSRIP_STAT_REG_OFFSET);
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}
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inline static void psramip_clear_fifo(uint32_t reg_base)
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{
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psramip_write32(((1<<PSRIP_FIFOCLR_CLR_TX_SHIFT) | (1<<PSRIP_FIFOCLR_CLR_RX_SHIFT)), reg_base, PSRIP_FIFOCLR_REG_OFFSET);
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while((psramip_r_status(reg_base)& PSRAM_STAT_BUSY));
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}
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inline static void psramip_w_high_speed_enable(uint32_t reg_base, uint32_t v)
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{
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uint32_t val = 0;
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val = psramip_read32(reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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if (v)
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val |= PSRIP_SPWKUPCTRL2_HS_MODE_MASK;
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else
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val &= ~PSRIP_SPWKUPCTRL2_HS_MODE_MASK;
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psramip_write32(val, reg_base, PSRIP_SPWKUPCTRL2_REG_OFFSET);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* PSRAMIP_HAL_H */
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