548 lines
15 KiB
C
548 lines
15 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#if defined(CHIP_HAS_PSRAM) && (CHIP_PSRAM_CTRL_VER == 1)
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#include "hal_cmu.h"
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#include "hal_location.h"
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#include "hal_psram.h"
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#include "hal_psramip_v1.h"
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#include "hal_timer.h"
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#include "hal_trace.h"
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#include "hal_uart.h"
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#include "plat_addr_map.h"
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#include "plat_types.h"
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#include "pmu.h"
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#define PSRAM_CALIB 0
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#define HAL_PSRAM_YES 1
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#define HAL_PSRAM_NO 0
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#define HAL_PSRAM_CMD_REG_READ 0x40
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#define HAL_PSRAM_CMD_REG_WRITE 0xc0
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#define HAL_PSRAM_CMD_RAM_READ 0x00
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#define HAL_PSRAM_CMD_RAM_WRITE 0x80
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enum HAL_PSRAM_SPEED {
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HAL_PSRAM_SPEED_13M = 13000000,
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HAL_PSRAM_SPEED_26M = 26000000,
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HAL_PSRAM_SPEED_50M = 50000000,
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HAL_PSRAM_SPEED_52M = 52000000,
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HAL_PSRAM_SPEED_78M = 78000000,
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HAL_PSRAM_SPEED_104M = 104000000,
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HAL_PSRAM_SPEED_130M = 130000000,
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HAL_PSRAM_SPEED_156M = 156000000,
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HAL_PSRAM_SPEED_182M = 182000000,
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HAL_PSRAM_SPEED_208M = 208000000,
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HAL_PSRAM_SPEED_234M = 234000000,
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};
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struct HAL_PSRAM_CONFIG_T {
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uint32_t source_clk;
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uint32_t speed;
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uint32_t dqs_rd_sel;
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uint32_t dqs_wr_sel;
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/* internal use : can be config if need to (useful for rom) */
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uint8_t override_config : 1;
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uint8_t div;
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};
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#define PSRAM_DEVICE_ID_LEN_MAX 8
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struct HAL_Psram_Context {
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uint8_t device_id[PSRAM_DEVICE_ID_LEN_MAX];
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uint32_t total_size;
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uint32_t read_size;
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uint32_t write_size;
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};
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/* hal api */
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#if 0
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uint8_t hal_psram_open(enum HAL_PSRAM_ID_T id, struct HAL_PSRAM_CONFIG_T *cfg);
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uint8_t hal_psram_close(enum HAL_PSRAM_ID_T id);
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void hal_psram_reg_dump(enum HAL_PSRAM_ID_T id);
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#endif
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void hal_psram_suspend(enum HAL_PSRAM_ID_T id);
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void hal_psram_resume(enum HAL_PSRAM_ID_T id);
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void hal_psram_wakeup_init(void);
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struct HAL_Psram_Context psram_ctx[HAL_PSRAM_ID_NUM];
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// static const char * const invalid_drv = "psram drv invalid";
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#define DIGITAL_REG(a) *(volatile uint32_t *)(a)
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FLASH_TEXT_LOC static uint32_t _psram_get_reg_base(enum HAL_PSRAM_ID_T id) {
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switch (id) {
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case HAL_PSRAM_ID_0:
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default:
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return PSRAM_CTRL_BASE;
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break;
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}
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}
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FLASH_TEXT_LOC static void
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_psram_exitsleep_onprocess_wait(enum HAL_PSRAM_ID_T id) {
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uint32_t reg_base = 0;
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reg_base = _psram_get_reg_base(id);
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while (psramip_r_exit_sleep_onprocess(reg_base))
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;
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while (!psramip_r_sleep_wakeup_state(reg_base))
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;
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}
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FLASH_TEXT_LOC static void _psram_busy_wait(enum HAL_PSRAM_ID_T id) {
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uint32_t reg_base = 0;
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reg_base = _psram_get_reg_base(id);
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while (psramip_r_busy(reg_base))
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;
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}
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#if 0
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static void _psram_div(enum HAL_PSRAM_ID_T id)
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{
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/* TODO */
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}
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/* hal api */
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uint8_t hal_psram_open(enum HAL_PSRAM_ID_T id, struct HAL_PSRAM_CONFIG_T *cfg)
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{
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uint32_t div = 0, reg_base = 0;
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//uint32_t psram_id = 0;
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reg_base = _psram_get_reg_base(id);
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/* over write config */
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if (cfg->override_config) {
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/* div */
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_psram_div(cfg->div);
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}
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else {
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div = cfg->source_clk/cfg->speed;
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_psram_div(div);
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}
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/* 0. dqs config */
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psramip_w_dqs_rd_sel(reg_base, cfg->dqs_rd_sel);
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psramip_w_dqs_wr_sel(reg_base, cfg->dqs_wr_sel);
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/* 1. high speed mode */
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if (cfg->speed >= HAL_PSRAM_SPEED_50M)
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psramip_w_high_speed_enable(reg_base, HAL_PSRAM_YES);
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else
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psramip_w_high_speed_enable(reg_base, HAL_PSRAM_NO);
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_psram_busy_wait(id);
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/* 2. wait calib done or FIXME timeout */
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psramip_w_enable_and_trigger_calib(reg_base);
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while (!psramip_r_calibst(reg_base));
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psramip_w_wrap_mode_enable(reg_base, HAL_PSRAM_YES);
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//psramip_w_wrap_mode_enable(reg_base, HAL_PSRAM_NO);
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//psramip_w_32bytewrap_mode(reg_base);
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psramip_w_1kwrap_mode(reg_base);
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#if 0
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/* psram device register read 1 or 2 or 3 */
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psramip_w_acc_size(reg_base, 1);
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psramip_w_cmd_addr(reg_base, HAL_PSRAM_CMD_REG_READ, 2);
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_psram_busy_wait(id);
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psram_id = psramip_r_rx_fifo(reg_base);
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uart_printf("psram id 0x%x\n", psram_id);
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#endif
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return 0;
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}
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uint8_t hal_psram_close(enum HAL_PSRAM_ID_T id)
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{
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return 0;
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}
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void hal_psram_reg_dump(enum HAL_PSRAM_ID_T id)
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{
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uint32_t reg_base = 0;
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uint32_t psram_id = 0;
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reg_base = _psram_get_reg_base(id);
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/* psram device register read 1 or 2 or 3 */
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psramip_w_acc_size(reg_base, 1);
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psramip_w_cmd_addr(reg_base, HAL_PSRAM_CMD_REG_READ, 2);
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_psram_busy_wait(id);
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psram_id = psramip_r_rx_fifo(reg_base);
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uart_printf("psram id 0x%x\n", psram_id);
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}
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#endif
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FLASH_TEXT_LOC uint8_t hal_psramip_read_reg(uint8_t reg) {
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uint32_t mr;
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psramip_clear_fifo(_psram_get_reg_base(HAL_PSRAM_ID_0));
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psramip_w_cmd_addr(0x40150000, HAL_PSRAM_CMD_REG_READ, (uint32_t)reg);
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while ((psramip_r_status(0x40150000) & PSRAM_STAT_BUSY))
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;
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mr = psramip_r_rx_fifo(0x40150000);
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return mr & 0xff;
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}
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FLASH_TEXT_LOC void hal_psramip_write_reg(uint8_t reg, uint8_t val) {
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enum HAL_PSRAM_ID_T id = HAL_PSRAM_ID_0;
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psramip_clear_fifo(_psram_get_reg_base(HAL_PSRAM_ID_0));
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psramip_w_tx_fifo(0x40150000, (uint32_t)val);
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psramip_w_cmd_addr(0x40150000, HAL_PSRAM_CMD_REG_WRITE, (uint32_t)reg);
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_psram_busy_wait(id);
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}
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FLASH_TEXT_LOC void hal_psram_suspend(enum HAL_PSRAM_ID_T id) {
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uint32_t reg_base = 0;
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reg_base = _psram_get_reg_base(id);
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psramip_w_acc_size(reg_base, 1);
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hal_psramip_write_reg(0x6, 0xf0);
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}
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FLASH_TEXT_LOC void hal_psram_resume(enum HAL_PSRAM_ID_T id) {
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uint32_t reg_base = 0;
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reg_base = _psram_get_reg_base(id);
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psramip_w_exit_sleep(reg_base);
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_psram_exitsleep_onprocess_wait(id);
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}
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// uint32_t test_ctrl =0;
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#ifdef CHIP_BEST2000
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void pmu_open_bbpll_for_psram();
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/*psram 120M use bbpll(div 4), 160M use bbpll(dir4), 100M use audio pll*/
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FLASH_TEXT_LOC void hal_psram_init(void) {
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#ifndef PSRAM_LOW_SPEED
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uint8_t mr = 0;
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// enum HAL_PSRAM_ID_T id = HAL_PSRAM_ID_0;
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#if defined(PSRAM_120M) || defined(PSRAM_160M)
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pmu_open_bbpll_for_psram();
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hal_cmu_mem_set_freq(HAL_CMU_FREQ_208M);
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#else /*PSRAM_160M*/
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#ifdef MCU_ULTRAHIGH_PERFORMANCE_MODE
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hal_cmu_mem_set_freq(HAL_CMU_FREQ_104M); // 104*2
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#else
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hal_cmu_mem_set_freq(HAL_CMU_FREQ_208M);
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#endif
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#endif /*PSRAM_160M*/
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pmu_psram_freq_config(HAL_PSRAM_SPEED_208M);
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#else
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hal_cmu_mem_set_freq(HAL_CMU_FREQ_26M);
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pmu_psram_freq_config(HAL_PSRAM_SPEED_26M);
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#endif
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hal_cmu_clock_enable(HAL_CMU_MOD_O_PSRAM);
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hal_cmu_clock_enable(HAL_CMU_MOD_H_PSRAM);
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hal_cmu_reset_clear(HAL_CMU_MOD_O_PSRAM);
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hal_cmu_reset_clear(HAL_CMU_MOD_H_PSRAM);
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DIGITAL_REG(0x4008004c) |= 0x1 << 21;
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#if 0 // for debug
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DIGITAL_REG(0x40150020) = 0x01;
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DIGITAL_REG(0x400000ac) &= ~(0xc0000);
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DIGITAL_REG(0x400000ac) |= (0x80000);
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DIGITAL_REG(0x40087008) = 0xFFFFFFAF;
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DIGITAL_REG(0x4008701c) = 0x2;
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#endif
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#ifndef PSRAM_LOW_SPEED
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DIGITAL_REG(0x40150040) = 0x44712133;
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DIGITAL_REG(0x40150044) = 0x200040b1;
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DIGITAL_REG(0x40150044) |= (1 << 1) | (1 << 30);
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while (((DIGITAL_REG(0x40150044)) & (0x1 << 30)))
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;
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// hal_sys_timer_delay(MS_TO_TICKS(10));
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DIGITAL_REG(0x40150044) &= ~(1 << 0);
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while (!((DIGITAL_REG(0x40150044)) & (0x1 << 0)))
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;
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// hal_sys_timer_delay(MS_TO_TICKS(10));
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DIGITAL_REG(0x40000090) = 0x0001ffff;
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while (!((DIGITAL_REG(0x40000090)) & (0x1 << 20)))
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;
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// hal_sys_timer_delay(MS_TO_TICKS(10));
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// lp delay
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// DIGITAL_REG(0x4015001C)=0xffffffff;//c
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DIGITAL_REG(0x4015001C) =
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((4 * 200) << 0) | ((70 * 200) << 16) |
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((70 * 200 / 1000) << 10); // 208MHZ: tHS 10us, tXHS 100us, tXPHS 100ns
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// ramp=1k select low speed
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DIGITAL_REG(0x4015002C) = 0x0000000d; // c
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// tx/rx Phase
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// #error "6666666666666666"
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// DIGITAL_REG(0x40150024)= 0x55000713;//0x55000373;//223
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// DIGITAL_REG(0x40150024)= 0x55000373;//0x55000373;//223
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#if PSRAM_CALIB
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DIGITAL_REG(0x40150024) = 0x55000373; // 0x55000373;//223
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#else
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#if defined(PSRAM_200M)
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DIGITAL_REG(0x40150024) = 0x55000653; // 0x55000373;//223
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#elif defined(PSRAM_160M)
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DIGITAL_REG(0x40150024) = 0x55000463; //;//0x55000373;//223
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#elif defined(PSRAM_120M)
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DIGITAL_REG(0x40150024) = 0x55000113; // 0x55000373;//223
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#else /*100M*/
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DIGITAL_REG(0x40150024) = 0x55000113; // 0x55000373;//223
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#endif
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#endif
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while (!((DIGITAL_REG(0x40150024)) & (0x1 << 3)))
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;
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#if 1
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// reset psram chip
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psramip_write32(0xff, 0x40150000, 0x00);
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while ((psramip_r_status(0x40150000) & PSRAM_STAT_BUSY))
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;
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// clear fifo
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psramip_write32(0x03, 0x40150000, 0x18);
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while ((psramip_r_status(0x40150000) & PSRAM_STAT_BUSY))
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;
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hal_sys_timer_delay(US_TO_TICKS(10));
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// test_ctrl = 1;
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// while (test_ctrl ==1);
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mr = hal_psramip_read_reg(0x0);
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mr &= ~(0x3 << 6); // MR[7:6] must set 0
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mr &= ~(0x1 << 5); // MR0[5] = 0, latency type 0->variable
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mr &= ~(0x7 << 2);
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mr |= (0x6 << 2); // MR0[4:2] = '110 Latency =6 for 200M (variable latency)
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mr &= ~(0x3 << 0);
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mr |= (0x1 << 0); // driver strength '01 -> half
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hal_psramip_write_reg(0x0, mr);
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mr = hal_psramip_read_reg(0x0);
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// TRACE(2,"PSRAM MODE REG 0 = 0x%x, status = 0x%x", mr,
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// psramip_r_status(0x40150000));
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mr = hal_psramip_read_reg(0x4);
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mr &= ~(0x01 << 7);
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mr |= (0x01 << 7); // MR[7] '1 -> write latency 1 for clk > 166MHz
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// hal_psramip_write_reg(0x4, mr);
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mr = hal_psramip_read_reg(0x4);
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// TRACE(2,"PSRAM MODE REG 4 = 0x%x, status = 0x%x", mr,
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// psramip_r_status(0x40150000));
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#endif
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hal_sys_timer_delay(US_TO_TICKS(10));
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#else /*PSRAM_LOW_SPEED*/
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// open psram phy power
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DIGITAL_REG(0x4008004c) |= (1 << 21);
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// init psram
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// lp delay
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DIGITAL_REG(0x4015001C) = 0x3fff3cff; // c
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// ramp=1k select low speed
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DIGITAL_REG(0x4015002C) = 0x0000000c;
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// tx/rx Phase
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DIGITAL_REG(0x40150024) = 0x55000223;
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#endif /*PSRAM_LOW_SPEED*/
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psramip_w_acc_size(_psram_get_reg_base(HAL_PSRAM_ID_0), 1);
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#ifdef PSRAM_200M
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hal_cmu_mem_set_freq(HAL_CMU_FREQ_208M);
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#endif
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}
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FLASH_TEXT_LOC void hal_psram_wakeup_init(void) {
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#ifndef PSRAM_LOW_SPEED
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DIGITAL_REG(0x40150040) = 0x44712133;
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DIGITAL_REG(0x40150044) = 0x200040b1;
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DIGITAL_REG(0x40150044) |= (1 << 1) | (1 << 30);
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// TRACE(1,"0x40150044 = 0x%x \n",DIGITAL_REG(0x40150044));
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while (((DIGITAL_REG(0x40150044)) & (0x1 << 30)))
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;
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// hal_sys_timer_delay(MS_TO_TICKS(10));
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DIGITAL_REG(0x40150044) &= ~(1 << 0);
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// TRACE(1,"0x40150044 = 0x%x \n", DIGITAL_REG(0x40150044));
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while (!((DIGITAL_REG(0x40150044)) & (0x1 << 0)))
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;
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// hal_sys_timer_delay(MS_TO_TICKS(10));
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DIGITAL_REG(0x40000090) = 0x0001ffff;
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// TRACE(1,"0x40000090 = 0x%x \n", DIGITAL_REG(0x40000090));
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while (!((DIGITAL_REG(0x40000090)) & (0x1 << 20)))
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;
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// hal_sys_timer_delay(MS_TO_TICKS(10));
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#endif
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hal_psram_resume(HAL_PSRAM_ID_0);
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}
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FLASH_TEXT_LOC void hal_psram_sleep(void) {
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#ifndef PSRAM_LOW_SPEED
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hal_psram_suspend(HAL_PSRAM_ID_0);
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/* dll power off */
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DIGITAL_REG(0x40150044) &= ~(1 << 1);
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/* phy power off */
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/* DIGITAL_REG(0x4008004c) &= ~(1 << 21) */
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#endif
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}
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#else
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FLASH_TEXT_LOC void hal_psram_init(void) {
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#ifndef PSRAM_LOW_SPEED
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unsigned int mr = 0;
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enum HAL_PSRAM_ID_T id = HAL_PSRAM_ID_0;
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#endif
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hal_cmu_mem_set_freq(HAL_CMU_FREQ_208M);
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hal_cmu_clock_enable(HAL_CMU_MOD_O_PSRAM);
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hal_cmu_clock_enable(HAL_CMU_MOD_H_PSRAM);
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hal_cmu_reset_clear(HAL_CMU_MOD_O_PSRAM);
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hal_cmu_reset_clear(HAL_CMU_MOD_H_PSRAM);
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#ifndef PSRAM_LOW_SPEED
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DIGITAL_REG(0x4001f038) = 0x77783533;
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DIGITAL_REG(0x4001f03c) = 0x3ffffff4;
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DIGITAL_REG(0x4001f03c) |= (1 << 1) | (1 << 30);
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while (((DIGITAL_REG(0x4001f03c)) & (0x1 << 30)))
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;
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hal_sys_timer_delay(MS_TO_TICKS(10));
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DIGITAL_REG(0x4001f03c) &= ~(1 << 0);
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while (!((DIGITAL_REG(0x4001f03c)) & (0x1 << 0)))
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;
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hal_sys_timer_delay(MS_TO_TICKS(10));
|
|
|
|
DIGITAL_REG(0x40000090) = 0x0001ffff;
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|
while (!((DIGITAL_REG(0x40000090)) & (0x1 << 20)))
|
|
;
|
|
hal_sys_timer_delay(MS_TO_TICKS(10));
|
|
|
|
// lp delay
|
|
DIGITAL_REG(0x4015001C) = 0xffffffff; // c
|
|
// ramp=1k select low speed
|
|
DIGITAL_REG(0x4015002C) = 0x0000000d; // c
|
|
// tx/rx Phase
|
|
DIGITAL_REG(0x40150024) = 0x55000563; // 223
|
|
while (!((DIGITAL_REG(0x40150024)) & (0x1 << 3)))
|
|
;
|
|
#if 1
|
|
// reset psram chip
|
|
psramip_write32(0xff, 0x40150000, 0x00);
|
|
while ((psramip_r_status(0x40150000) & PSRAM_STAT_BUSY))
|
|
;
|
|
// clear fifo
|
|
psramip_write32(0x03, 0x40150000, 0x18);
|
|
while ((psramip_r_status(0x40150000) & PSRAM_STAT_BUSY))
|
|
;
|
|
hal_sys_timer_delay(MS_TO_TICKS(10));
|
|
|
|
// read MR0
|
|
psramip_w_cmd_addr(0x40150000, HAL_PSRAM_CMD_REG_READ, 0);
|
|
while ((psramip_r_status(0x40150000) & PSRAM_STAT_BUSY))
|
|
;
|
|
// need read twice
|
|
mr = psramip_r_rx_fifo(0x40150000);
|
|
mr = psramip_r_rx_fifo(0x40150000);
|
|
// hal_uart_printf("count=0x%x mr0 = 0x%x \n", psramip_r_status(0x40150000),
|
|
// mr);
|
|
|
|
mr &= 0xff;
|
|
mr &= ~(0x03 << 6); // MR[7:6] must set 0
|
|
// driver strength 00:1/16 01:1/2 10:1/4 11:1/8 MR0[1:0]
|
|
mr &= ~0x03;
|
|
mr |= 0x01;
|
|
// for >> 200M MR0[4:2]
|
|
mr &= ~(0x07 << 2);
|
|
mr |= (0x06 << 2);
|
|
psramip_w_tx_fifo(0x40150000, mr);
|
|
psramip_w_cmd_addr(0x40150000, HAL_PSRAM_CMD_REG_WRITE, 0);
|
|
_psram_busy_wait(id);
|
|
|
|
// read MR0 again
|
|
psramip_w_cmd_addr(0x40150000, HAL_PSRAM_CMD_REG_READ, 0);
|
|
while ((psramip_r_status(0x40150000) & PSRAM_STAT_BUSY))
|
|
;
|
|
mr = psramip_r_rx_fifo(0x40150000);
|
|
mr = psramip_r_rx_fifo(0x40150000);
|
|
// hal_uart_printf("count=0x%x mr0 = 0x%x \n", psramip_r_status(0x40150000),
|
|
// mr);
|
|
// read MR4
|
|
psramip_w_cmd_addr(0x40150000, HAL_PSRAM_CMD_REG_READ, 4);
|
|
_psram_busy_wait(id);
|
|
mr = psramip_r_rx_fifo(0x40150000);
|
|
mr = psramip_r_rx_fifo(0x40150000);
|
|
// hal_uart_printf("mr4 = 0x%x\n", mr);
|
|
|
|
_psram_busy_wait(id);
|
|
#endif
|
|
hal_sys_timer_delay(MS_TO_TICKS(10));
|
|
#else
|
|
// open psram phy power
|
|
DIGITAL_REG(0x4001f02c) |= (1 << 16);
|
|
// init psram
|
|
// lp delay
|
|
DIGITAL_REG(0x4015001C) = 0x3fff3cff; // c
|
|
// ramp=1k select low speed
|
|
DIGITAL_REG(0x4015002C) = 0x0000000c;
|
|
// tx/rx Phase
|
|
DIGITAL_REG(0x40150024) = 0x55000223;
|
|
#endif
|
|
}
|
|
|
|
FLASH_TEXT_LOC void hal_psram_wakeup_init(void) {
|
|
#ifndef PSRAM_LOW_SPEED
|
|
// dll
|
|
DIGITAL_REG(0x4001f038) = 0x77783533;
|
|
|
|
DIGITAL_REG(0x4001f03c) = 0x3ffffff4;
|
|
DIGITAL_REG(0x4001f03c) |= (1 << 1) | (1 << 30);
|
|
while (((DIGITAL_REG(0x4001f03c)) & (0x1 << 30)))
|
|
;
|
|
hal_sys_timer_delay(MS_TO_TICKS(10));
|
|
DIGITAL_REG(0x4001f03c) &= ~(1 << 0);
|
|
while (!((DIGITAL_REG(0x4001f03c)) & (0x1 << 0)))
|
|
;
|
|
hal_sys_timer_delay(MS_TO_TICKS(10));
|
|
|
|
DIGITAL_REG(0x40000090) = 0x0001ffff;
|
|
while (!((DIGITAL_REG(0x40000090)) & (0x1 << 20)))
|
|
;
|
|
hal_sys_timer_delay(MS_TO_TICKS(10));
|
|
#endif
|
|
|
|
hal_psram_resume(HAL_PSRAM_ID_0);
|
|
}
|
|
|
|
FLASH_TEXT_LOC void hal_psram_sleep(void) {
|
|
#ifndef PSRAM_LOW_SPEED
|
|
hal_psram_suspend(HAL_PSRAM_ID_0);
|
|
/* dll power off */
|
|
DIGITAL_REG(0x4001f03c) &= ~(1 << 1);
|
|
/* phy power off */
|
|
/* DIGITAL_REG(0x4001f02c) &= ~(1 << 16) */
|
|
#endif
|
|
}
|
|
|
|
#endif
|
|
|
|
FLASH_TEXT_LOC void hal_psram_wakeup(void) {
|
|
#ifndef PSRAM_LOW_SPEED
|
|
hal_psram_wakeup_init();
|
|
#endif
|
|
}
|
|
|
|
#endif
|