495 lines
14 KiB
C
495 lines
14 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "hal_gpio.h"
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#include "cmsis_nvic.h"
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#include "hal_trace.h"
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#include "hal_uart.h"
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#include "plat_addr_map.h"
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#include "plat_types.h"
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#include "reg_gpio.h"
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#include "stdarg.h"
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#include "stdio.h"
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#ifdef PMU_HAS_LED_PIN
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#include "pmu.h"
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#endif
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#define HAL_GPIO_BANK_NUM 1
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#define HAL_GPIO_PORT_NUM 1
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#define HAL_GPIO_PIN_NUM_EACH_PORT (32)
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#define HAL_GPIO_PIN_NUM_EACH_BANK \
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(HAL_GPIO_PORT_NUM * HAL_GPIO_PIN_NUM_EACH_PORT)
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#define HAL_GPIO_PIN_TO_BANK(pin) ((pin) / HAL_GPIO_PIN_NUM_EACH_BANK)
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#define HAL_GPIO_PIN_TO_PORT(pin) \
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(((pin) % HAL_GPIO_PIN_NUM_EACH_BANK) / HAL_GPIO_PIN_NUM_EACH_PORT)
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#ifdef GPIOAUX_BASE
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#define HAL_GPIO_AUX_BANK_NUM 1
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#define HAL_GPIO_AUX_PORT_NUM 1
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#define HAL_GPIO_AUX_PIN_NUM_EACH_PORT (8)
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#define HAL_GPIO_AUX_PIN_NUM_EACH_BANK \
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(HAL_GPIO_AUX_PORT_NUM * HAL_GPIO_AUX_PIN_NUM_EACH_PORT)
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#define HAL_GPIO_AUX_PIN_TO_BANK(pin) \
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(((pin)-HAL_GPIO_PIN_P4_0) / HAL_GPIO_AUX_PIN_NUM_EACH_BANK)
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#define HAL_GPIO_AUX_PIN_TO_PORT(pin) \
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((((pin)-HAL_GPIO_PIN_P4_0) % HAL_GPIO_AUX_PIN_NUM_EACH_BANK) / \
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HAL_GPIO_AUX_PIN_NUM_EACH_PORT)
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#endif
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typedef void (*_HAL_GPIO_IRQ_HANDLER)(void);
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struct GPIO_PORT_T {
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__IO uint32_t GPIO_DR; // 0x00
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__IO uint32_t GPIO_DDR; // 0x04
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__IO uint32_t GPIO_CTL; // 0x08
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};
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struct GPIO_BANK_T {
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struct GPIO_PORT_T port[HAL_GPIO_PORT_NUM];
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struct GPIO_PORT_T _port_reserved[3];
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__IO uint32_t GPIO_INTEN; // 0x30
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__IO uint32_t GPIO_INTMASK; // 0x34
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__IO uint32_t GPIO_INTTYPE_LEVEL; // 0x38
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__IO uint32_t GPIO_INT_POLARITY; // 0x3C
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__I uint32_t GPIO_INTSTATUS; // 0x40
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__I uint32_t GPIO_RAW_INTSTATUS; // 0x44
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__IO uint32_t GPIO_DEBOUNCE; // 0x48
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__IO uint32_t GPIO_PORTA_EOI; // 0x4C
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__I uint32_t GPIO_EXT_PORT[HAL_GPIO_PORT_NUM]; // 0x50
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__I uint32_t GPIO_EXT_PORT_reserved[3];
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__IO uint32_t GPIO_LS_SYNC; // 0x60
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};
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void _hal_gpio_bank0_irq_handler(void);
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static struct GPIO_BANK_T *const gpio_bank[HAL_GPIO_BANK_NUM] = {
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(struct GPIO_BANK_T *)GPIO_BASE,
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};
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static HAL_GPIO_PIN_IRQ_HANDLER gpio_irq_handler[HAL_GPIO_PIN_NUM] = {0};
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static _HAL_GPIO_IRQ_HANDLER _gpio_irq_handler[HAL_GPIO_BANK_NUM] = {
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_hal_gpio_bank0_irq_handler,
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};
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#ifdef GPIOAUX_BASE
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void _hal_gpio_aux_bank0_irq_handler(void);
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static struct GPIO_BANK_T *const gpio_aux_bank[HAL_GPIO_BANK_NUM] = {
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(struct GPIO_BANK_T *)GPIOAUX_BASE,
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};
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#if defined(CHIP_BEST2000) && defined(PMU_HAS_LED_PIN)
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static struct GPIO_BANK_T *const aon_gpio_aux_bank[HAL_GPIO_BANK_NUM] = {
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(struct GPIO_BANK_T *)AON_GPIOAUX_BASE,
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};
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#endif
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static _HAL_GPIO_IRQ_HANDLER _gpio_aux_irq_handler[HAL_GPIO_AUX_BANK_NUM] = {
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_hal_gpio_aux_bank0_irq_handler,
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};
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#endif
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static const char *const err_bad_pin = "Bad GPIO pin %u (should < %u)";
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enum HAL_GPIO_DIR_T hal_gpio_pin_get_dir(enum HAL_GPIO_PIN_T pin) {
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int pin_offset = 0;
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int bank = 0, port = 0;
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enum HAL_GPIO_DIR_T dir = 0;
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enum HAL_GPIO_PIN_T max_pin = HAL_GPIO_PIN_NUM;
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#ifdef PMU_HAS_LED_PIN
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max_pin = HAL_GPIO_PIN_LED_NUM;
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#endif
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ASSERT(pin < max_pin, err_bad_pin, pin, max_pin);
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if (0) {
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}
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#ifdef PMU_HAS_LED_PIN
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else if (pin == HAL_GPIO_PIN_LED1 || pin == HAL_GPIO_PIN_LED2) {
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return pmu_led_get_direction(pin);
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}
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#endif
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#ifdef GPIOAUX_BASE
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else if (pin >= HAL_GPIO_PIN_P4_0) {
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bank = HAL_GPIO_AUX_PIN_TO_BANK(pin);
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port = HAL_GPIO_AUX_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_AUX_PIN_NUM_EACH_PORT;
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if (gpio_aux_bank[bank]->port[port].GPIO_DDR & (0x1 << pin_offset))
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dir = HAL_GPIO_DIR_OUT;
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else
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dir = HAL_GPIO_DIR_IN;
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}
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#endif
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else {
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bank = HAL_GPIO_PIN_TO_BANK(pin);
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port = HAL_GPIO_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_PIN_NUM_EACH_PORT;
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if (gpio_bank[bank]->port[port].GPIO_DDR & (0x1 << pin_offset))
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dir = HAL_GPIO_DIR_OUT;
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else
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dir = HAL_GPIO_DIR_IN;
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}
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return dir;
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}
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void hal_gpio_pin_set_dir(enum HAL_GPIO_PIN_T pin, enum HAL_GPIO_DIR_T dir,
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uint8_t val_for_out) {
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int pin_offset = 0;
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int bank = 0, port = 0;
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enum HAL_GPIO_PIN_T max_pin = HAL_GPIO_PIN_NUM;
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#ifdef PMU_HAS_LED_PIN
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max_pin = HAL_GPIO_PIN_LED_NUM;
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#endif
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ASSERT(pin < max_pin, err_bad_pin, pin, max_pin);
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if (dir == HAL_GPIO_DIR_OUT) {
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if (val_for_out) {
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hal_gpio_pin_set(pin);
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} else {
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hal_gpio_pin_clr(pin);
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}
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}
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if (0) {
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}
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#ifdef PMU_HAS_LED_PIN
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else if (pin == HAL_GPIO_PIN_LED1 || pin == HAL_GPIO_PIN_LED2) {
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pmu_led_set_direction(pin, dir);
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}
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#endif
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#ifdef GPIOAUX_BASE
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else if (pin >= HAL_GPIO_PIN_P4_0) {
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bank = HAL_GPIO_AUX_PIN_TO_BANK(pin);
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port = HAL_GPIO_AUX_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_AUX_PIN_NUM_EACH_PORT;
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if (dir == HAL_GPIO_DIR_OUT)
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gpio_aux_bank[bank]->port[port].GPIO_DDR |= 0x1 << pin_offset;
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else
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gpio_aux_bank[bank]->port[port].GPIO_DDR &= ~(0x1 << pin_offset);
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}
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#endif
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else {
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bank = HAL_GPIO_PIN_TO_BANK(pin);
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port = HAL_GPIO_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_PIN_NUM_EACH_PORT;
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if (dir == HAL_GPIO_DIR_OUT)
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gpio_bank[bank]->port[port].GPIO_DDR |= 0x1 << pin_offset;
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else
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gpio_bank[bank]->port[port].GPIO_DDR &= ~(0x1 << pin_offset);
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}
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}
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void hal_gpio_pin_set(enum HAL_GPIO_PIN_T pin) {
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int pin_offset = 0;
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int bank = 0, port = 0;
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enum HAL_GPIO_PIN_T max_pin = HAL_GPIO_PIN_NUM;
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#ifdef PMU_HAS_LED_PIN
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max_pin = HAL_GPIO_PIN_LED_NUM;
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#endif
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ASSERT(pin < max_pin, err_bad_pin, pin, max_pin);
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if (0) {
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}
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#ifdef PMU_HAS_LED_PIN
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else if (pin == HAL_GPIO_PIN_LED1 || pin == HAL_GPIO_PIN_LED2) {
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#ifdef CHIP_BEST2000
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pin_offset = pin - HAL_GPIO_PIN_LED1 + 6;
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aon_gpio_aux_bank[0]->port[0].GPIO_DR |= 0x1 << pin_offset;
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#else
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pmu_led_set_value(pin, 1);
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#endif
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}
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#endif
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#ifdef GPIOAUX_BASE
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else if (pin >= HAL_GPIO_PIN_P4_0) {
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bank = HAL_GPIO_AUX_PIN_TO_BANK(pin);
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port = HAL_GPIO_AUX_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_AUX_PIN_NUM_EACH_PORT;
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gpio_aux_bank[bank]->port[port].GPIO_DR |= 0x1 << pin_offset;
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}
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#endif
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else {
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bank = HAL_GPIO_PIN_TO_BANK(pin);
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port = HAL_GPIO_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_PIN_NUM_EACH_PORT;
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gpio_bank[bank]->port[port].GPIO_DR |= 0x1 << pin_offset;
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}
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}
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void hal_gpio_pin_clr(enum HAL_GPIO_PIN_T pin) {
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int pin_offset = 0;
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int bank = 0, port = 0;
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enum HAL_GPIO_PIN_T max_pin = HAL_GPIO_PIN_NUM;
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#ifdef PMU_HAS_LED_PIN
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max_pin = HAL_GPIO_PIN_LED_NUM;
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#endif
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ASSERT(pin < max_pin, err_bad_pin, pin, max_pin);
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if (0) {
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}
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#ifdef PMU_HAS_LED_PIN
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else if (pin == HAL_GPIO_PIN_LED1 || pin == HAL_GPIO_PIN_LED2) {
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#ifdef CHIP_BEST2000
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pin_offset = pin - HAL_GPIO_PIN_LED1 + 6;
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aon_gpio_aux_bank[0]->port[0].GPIO_DR &= ~(0x1 << pin_offset);
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#else
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pmu_led_set_value(pin, 0);
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#endif
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}
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#endif
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#ifdef GPIOAUX_BASE
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else if (pin >= HAL_GPIO_PIN_P4_0) {
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bank = HAL_GPIO_AUX_PIN_TO_BANK(pin);
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port = HAL_GPIO_AUX_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_AUX_PIN_NUM_EACH_PORT;
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gpio_aux_bank[bank]->port[port].GPIO_DR &= ~(0x1 << pin_offset);
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}
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#endif
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else {
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bank = HAL_GPIO_PIN_TO_BANK(pin);
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port = HAL_GPIO_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_PIN_NUM_EACH_PORT;
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gpio_bank[bank]->port[port].GPIO_DR &= ~(0x1 << pin_offset);
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}
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}
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uint8_t hal_gpio_pin_get_val(enum HAL_GPIO_PIN_T pin) {
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int pin_offset = 0;
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int bank = 0, port = 0;
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enum HAL_GPIO_PIN_T max_pin = HAL_GPIO_PIN_NUM;
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#ifdef PMU_HAS_LED_PIN
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max_pin = HAL_GPIO_PIN_LED_NUM;
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#endif
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ASSERT(pin < max_pin, err_bad_pin, pin, max_pin);
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if (0) {
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}
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#ifdef PMU_HAS_LED_PIN
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else if (pin == HAL_GPIO_PIN_LED1 || pin == HAL_GPIO_PIN_LED2) {
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#ifdef CHIP_BEST2000
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pin_offset = pin - HAL_GPIO_PIN_LED1 + 6;
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return (((aon_gpio_aux_bank[0]->GPIO_EXT_PORT[0]) & (0x1 << pin_offset)) >>
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pin_offset);
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#else
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return pmu_led_get_value(pin);
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#endif
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}
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#endif
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#ifdef GPIOAUX_BASE
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else if (pin >= HAL_GPIO_PIN_P4_0) {
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bank = HAL_GPIO_AUX_PIN_TO_BANK(pin);
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port = HAL_GPIO_AUX_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_AUX_PIN_NUM_EACH_PORT;
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/* when as input : read back outside signal value */
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/* when as output: read back DR register value ,same as read back DR
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* register */
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return (
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((gpio_aux_bank[bank]->GPIO_EXT_PORT[port]) & (0x1 << pin_offset)) >>
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pin_offset);
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}
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#endif
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else {
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bank = HAL_GPIO_PIN_TO_BANK(pin);
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port = HAL_GPIO_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_PIN_NUM_EACH_PORT;
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/* when as input : read back outside signal value */
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/* when as output: read back DR register value ,same as read back DR
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* register */
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return (((gpio_bank[bank]->GPIO_EXT_PORT[port]) & (0x1 << pin_offset)) >>
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pin_offset);
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}
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}
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void _hal_gpio_bank0_irq_handler(void) {
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uint32_t raw_status = 0, bank = 0, pin_offset = 0;
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raw_status = gpio_bank[bank]->GPIO_RAW_INTSTATUS;
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if (raw_status == 0) {
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return;
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}
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/* clear irq */
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gpio_bank[bank]->GPIO_PORTA_EOI = raw_status;
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while (raw_status) {
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if (raw_status & 0x1) {
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if (gpio_irq_handler[pin_offset]) {
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gpio_irq_handler[pin_offset](pin_offset +
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bank * HAL_GPIO_PIN_NUM_EACH_BANK);
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}
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}
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raw_status >>= 1;
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++pin_offset;
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}
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}
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#ifdef GPIOAUX_BASE
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void _hal_gpio_aux_bank0_irq_handler(void) {
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uint32_t raw_status = 0, bank = 0, pin_offset = 0;
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raw_status = 0;
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bank = 0;
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pin_offset = 0;
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raw_status = gpio_aux_bank[bank]->GPIO_RAW_INTSTATUS;
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if (raw_status == 0)
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return;
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/* clear irq */
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gpio_aux_bank[bank]->GPIO_PORTA_EOI = raw_status;
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while (raw_status) {
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if (raw_status & 0x1) {
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if (gpio_irq_handler[pin_offset + HAL_GPIO_PIN_P4_0]) {
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gpio_irq_handler[pin_offset + HAL_GPIO_PIN_P4_0](
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pin_offset + HAL_GPIO_PIN_P4_0 + bank * HAL_GPIO_PIN_NUM_EACH_BANK);
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}
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}
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raw_status >>= 1;
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++pin_offset;
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}
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}
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#endif
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uint8_t hal_gpio_setup_irq(enum HAL_GPIO_PIN_T pin,
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const struct HAL_GPIO_IRQ_CFG_T *cfg) {
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int pin_offset = 0;
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int bank = 0, port = 0;
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enum HAL_GPIO_PIN_T max_pin = HAL_GPIO_PIN_NUM;
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#if defined(PMU_HAS_LED_PIN) && defined(PMU_HAS_LED_IRQ)
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max_pin = HAL_GPIO_PIN_LED_NUM;
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#endif
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ASSERT(pin < max_pin, err_bad_pin, pin, max_pin);
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if (0) {
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}
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#if defined(PMU_HAS_LED_PIN) && defined(PMU_HAS_LED_IRQ)
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else if (pin == HAL_GPIO_PIN_LED1 || pin == HAL_GPIO_PIN_LED2) {
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return pmu_gpio_setup_irq(pin, cfg);
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}
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#endif
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#ifdef GPIOAUX_BASE
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else if (pin >= HAL_GPIO_PIN_P4_0) {
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bank = HAL_GPIO_AUX_PIN_TO_BANK(pin);
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port = HAL_GPIO_AUX_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_AUX_PIN_NUM_EACH_PORT;
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/* only port A support irq */
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if (port != 0)
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return 0;
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if (cfg->irq_enable) {
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gpio_aux_bank[bank]->GPIO_INTMASK |= (0x1 << pin_offset);
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if (cfg->irq_debounce)
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gpio_aux_bank[bank]->GPIO_DEBOUNCE |= 0x1 << pin_offset;
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else
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gpio_aux_bank[bank]->GPIO_DEBOUNCE &= ~(0x1 << pin_offset);
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if (cfg->irq_type == HAL_GPIO_IRQ_TYPE_EDGE_SENSITIVE)
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gpio_aux_bank[bank]->GPIO_INTTYPE_LEVEL |= 0x1 << pin_offset;
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else
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gpio_aux_bank[bank]->GPIO_INTTYPE_LEVEL &= ~(0x1 << pin_offset);
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if (cfg->irq_polarity == HAL_GPIO_IRQ_POLARITY_HIGH_RISING)
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gpio_aux_bank[bank]->GPIO_INT_POLARITY |= 0x1 << pin_offset;
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else
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gpio_aux_bank[bank]->GPIO_INT_POLARITY &= ~(0x1 << pin_offset);
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gpio_irq_handler[pin] = cfg->irq_handler;
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NVIC_SetVector(GPIOAUX_IRQn, (uint32_t)_gpio_aux_irq_handler[bank]);
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NVIC_SetPriority(GPIOAUX_IRQn, IRQ_PRIORITY_NORMAL);
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NVIC_EnableIRQ(GPIOAUX_IRQn);
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gpio_aux_bank[bank]->GPIO_INTMASK &= ~(0x1 << pin_offset);
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gpio_aux_bank[bank]->GPIO_INTEN |= 0x1 << pin_offset;
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} else {
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gpio_aux_bank[bank]->GPIO_INTMASK |= (0x1 << pin_offset);
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gpio_aux_bank[bank]->GPIO_INTEN &= ~(0x1 << pin_offset);
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gpio_irq_handler[pin] = 0;
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}
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}
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#endif
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else {
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bank = HAL_GPIO_PIN_TO_BANK(pin);
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port = HAL_GPIO_PIN_TO_PORT(pin);
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pin_offset = pin % HAL_GPIO_PIN_NUM_EACH_PORT;
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/* only port A support irq */
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if (port != 0)
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return 0;
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if (cfg->irq_enable) {
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gpio_bank[bank]->GPIO_INTMASK |= (0x1 << pin_offset);
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|
|
|
if (cfg->irq_debounce)
|
|
gpio_bank[bank]->GPIO_DEBOUNCE |= 0x1 << pin_offset;
|
|
else
|
|
gpio_bank[bank]->GPIO_DEBOUNCE &= ~(0x1 << pin_offset);
|
|
|
|
if (cfg->irq_type == HAL_GPIO_IRQ_TYPE_EDGE_SENSITIVE)
|
|
gpio_bank[bank]->GPIO_INTTYPE_LEVEL |= 0x1 << pin_offset;
|
|
else
|
|
gpio_bank[bank]->GPIO_INTTYPE_LEVEL &= ~(0x1 << pin_offset);
|
|
|
|
if (cfg->irq_polarity == HAL_GPIO_IRQ_POLARITY_HIGH_RISING)
|
|
gpio_bank[bank]->GPIO_INT_POLARITY |= 0x1 << pin_offset;
|
|
else
|
|
gpio_bank[bank]->GPIO_INT_POLARITY &= ~(0x1 << pin_offset);
|
|
|
|
gpio_irq_handler[pin] = cfg->irq_handler;
|
|
|
|
NVIC_SetVector(GPIO_IRQn, (uint32_t)_gpio_irq_handler[bank]);
|
|
NVIC_SetPriority(GPIO_IRQn, IRQ_PRIORITY_NORMAL);
|
|
NVIC_EnableIRQ(GPIO_IRQn);
|
|
|
|
gpio_bank[bank]->GPIO_INTMASK &= ~(0x1 << pin_offset);
|
|
gpio_bank[bank]->GPIO_INTEN |= 0x1 << pin_offset;
|
|
} else {
|
|
gpio_bank[bank]->GPIO_INTMASK |= (0x1 << pin_offset);
|
|
gpio_bank[bank]->GPIO_INTEN &= ~(0x1 << pin_offset);
|
|
gpio_irq_handler[pin] = 0;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|