393 lines
15 KiB
C
393 lines
15 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __BT_DRV_INTERFACE_H__
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#define __BT_DRV_INTERFACE_H__
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#include "stdint.h"
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#include "stdbool.h"
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//LMP Opcodes
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#define LMP_NAME_REQ_OPCODE 1
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#define LMP_NAME_RES_OPCODE 2
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#define LMP_ACCEPTED_OPCODE 3
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#define LMP_NOT_ACCEPTED_OPCODE 4
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#define LMP_CLK_OFF_REQ_OPCODE 5
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#define LMP_CLK_OFF_RES_OPCODE 6
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#define LMP_DETACH_OPCODE 7
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#define LMP_INRAND_OPCODE 8
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#define LMP_COMBKEY_OPCODE 9
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#define LMP_UNITKEY_OPCODE 10
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#define LMP_AURAND_OPCODE 11
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#define LMP_SRES_OPCODE 12
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#define LMP_TEMPRAND_OPCODE 13
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#define LMP_TEMPKEY_OPCODE 14
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#define LMP_ENC_MODE_REQ_OPCODE 15
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#define LMP_ENC_KEY_SIZE_REQ_OPCODE 16
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#define LMP_START_ENC_REQ_OPCODE 17
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#define LMP_STOP_ENC_REQ_OPCODE 18
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#define LMP_SWITCH_REQ_OPCODE 19
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#define LMP_HOLD_OPCODE 20
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#define LMP_HOLD_REQ_OPCODE 21
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#define LMP_SNIFF_REQ_OPCODE 23
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#define LMP_UNSNIFF_REQ_OPCODE 24
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#define LMP_PARK_REQ_OPCODE 25
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#define LMP_SET_BSWIN_OPCODE 27
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#define LMP_MODIF_BEACON_OPCODE 28
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#define LMP_UNPARK_BD_REQ_OPCODE 29
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#define LMP_UNPARK_PM_REQ_OPCODE 30
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#define LMP_INCR_PWR_REQ_OPCODE 31
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#define LMP_DECR_PWR_REQ_OPCODE 32
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#define LMP_MAX_PWR_OPCODE 33
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#define LMP_MIN_PWR_OPCODE 34
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#define LMP_AUTO_RATE_OPCODE 35
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#define LMP_PREF_RATE_OPCODE 36
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#define LMP_VER_REQ_OPCODE 37
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#define LMP_VER_RES_OPCODE 38
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#define LMP_FEATS_REQ_OPCODE 39
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#define LMP_FEATS_RES_OPCODE 40
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#define LMP_QOS_OPCODE 41
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#define LMP_QOS_REQ_OPCODE 42
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#define LMP_SCO_LINK_REQ_OPCODE 43
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#define LMP_RMV_SCO_LINK_REQ_OPCODE 44
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#define LMP_MAX_SLOT_OPCODE 45
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#define LMP_MAX_SLOT_REQ_OPCODE 46
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#define LMP_TIMING_ACCU_REQ_OPCODE 47
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#define LMP_TIMING_ACCU_RES_OPCODE 48
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#define LMP_SETUP_CMP_OPCODE 49
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#define LMP_USE_SEMI_PERM_KEY_OPCODE 50
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#define LMP_HOST_CON_REQ_OPCODE 51
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#define LMP_SLOT_OFF_OPCODE 52
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#define LMP_PAGE_MODE_REQ_OPCODE 53
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#define LMP_PAGE_SCAN_MODE_REQ_OPCODE 54
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#define LMP_SUPV_TO_OPCODE 55
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#define LMP_TEST_ACTIVATE_OPCODE 56
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#define LMP_TEST_CTRL_OPCODE 57
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#define LMP_ENC_KEY_SIZE_MASK_REQ_OPCODE 58
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#define LMP_ENC_KEY_SIZE_MASK_RES_OPCODE 59
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#define LMP_SET_AFH_OPCODE 60
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#define LMP_ENCAPS_HDR_OPCODE 61
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#define LMP_ENCAPS_PAYL_OPCODE 62
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#define LMP_SP_CFM_OPCODE 63
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#define LMP_SP_NB_OPCODE 64
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#define LMP_DHKEY_CHK_OPCODE 65
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#define LMP_PAUSE_ENC_AES_REQ_OPCODE 66
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///LMP Escape 4 Extended Opcodes
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#define LMP_ACCEPTED_EXT_EXTOPCODE 1
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#define LMP_NOT_ACCEPTED_EXT_EXTOPCODE 2
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#define LMP_FEATS_REQ_EXT_EXTOPCODE 3
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#define LMP_FEATS_RES_EXT_EXTOPCODE 4
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#define LMP_CLK_ADJ_EXTOPCODE 5
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#define LMP_CLK_ADJ_ACK_EXTOPCODE 6
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#define LMP_CLK_ADJ_REQ_EXTOPCODE 7
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#define LMP_PKT_TYPE_TBL_REQ_EXTOPCODE 11
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#define LMP_ESCO_LINK_REQ_EXTOPCODE 12
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#define LMP_RMV_ESCO_LINK_REQ_EXTOPCODE 13
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#define LMP_CH_CLASS_REQ_EXTOPCODE 16
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#define LMP_CH_CLASS_EXTOPCODE 17
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#define LMP_SSR_REQ_EXTOPCODE 21
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#define LMP_SSR_RES_EXTOPCODE 22
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#define LMP_PAUSE_ENC_REQ_EXTOPCODE 23
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#define LMP_RESUME_ENC_REQ_EXTOPCODE 24
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#define LMP_IO_CAP_REQ_EXTOPCODE 25
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#define LMP_IO_CAP_RES_EXTOPCODE 26
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#define LMP_NUM_COMPARISON_FAIL_EXTOPCODE 27
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#define LMP_PASSKEY_FAIL_EXTOPCODE 28
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#define LMP_OOB_FAIL_EXTOPCODE 29
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#define LMP_KEYPRESS_NOTIF_EXTOPCODE 30
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#define LMP_PWR_CTRL_REQ_EXTOPCODE 31
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#define LMP_PWR_CTRL_RES_EXTOPCODE 32
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#define LMP_PING_REQ_EXTOPCODE 33
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#define LMP_PING_RES_EXTOPCODE 34
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// CARE: round-off error
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#define BT_CLK_UNIT 312.5 //us
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#define BT_CLK_UNIT_2X 625 //us
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#define BT_CLK_UNIT_10X 3125 //us
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#define US_TO_BTCLKS(us) ((uint64_t)(us) * 2 / BT_CLK_UNIT_2X)
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#define BTCLKS_TO_US(n) ((uint64_t)(n) * BT_CLK_UNIT_2X / 2)
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#define DUT_CONNECT_STATUS_CONNECTED (1)
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#define DUT_CONNECT_STATUS_DISCONNECTED (2)
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#define BT_TRIG_NONE_ROLE (0)
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#define BT_TRIG_MASTER_ROLE (1)
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#define BT_TRIG_SLAVE_ROLE (2)
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enum BT_WORK_MODE_T{
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BT_A2DP_WORK_MODE = 0,
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BT_HFP_WORK_MODE,
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BT_IDLE_MODE,
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BT_NONE_MODE,
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};
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enum BT_AGC_MODE_T{
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BT_AGC_MODE_SW = 0,
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BT_AGC_MODE_HW,
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BT_AGC_MODE_NONE,
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};
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//add bt magic call back function here
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struct bt_cb_tag
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{
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///switch various agc call back function
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void (*bt_switch_agc)(enum BT_WORK_MODE_T);
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};
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#define btdrv_set_intersys_trace_enable() beshci_set_intersys_trace_enable()
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#define btdrv_set_spuv_hci_buff_trace_enable() beshci_set_supv_hci_buff_trace_enable()
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#define btdrv_set_a2dp_stream_trace_disable() beshci_set_a2dp_stream_trace_enable(false)
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#define btdrv_enable_sleep_checker(isEnable) beshci_enable_sleep_checker(isEnable)
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#define HCI_HANDLE_MIN (0x80)
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#define HCI_HANDLE_MAX (0x83)
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#define HCI_LINK_INDEX_INVALID (0xFF)
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#define btdrv_is_link_index_valid(index) (index != HCI_LINK_INDEX_INVALID)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void btdrv_hciopen(void);
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void btdrv_hcioff(void);
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void btdrv_start_bt(void);
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void btdrv_SendData(const uint8_t *buff,uint8_t len);
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void bt_drv_extra_config_after_init(void);
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void btdrv_rf_init_ext(void);
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void btdrv_stop_bt(void);
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void btdrv_testmode_start(void);
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void btdrv_enable_dut(void);
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void btdrv_hci_reset(void);
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void btdrv_enable_nonsig_tx(uint8_t index);
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void btdrv_enable_nonsig_rx(uint8_t index);
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void btdrv_vco_test_start(uint8_t chnl);
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void btdrv_vco_test_stop(void);
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void bt_drv_calib_open(void);
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void bt_drv_check_calib(void);
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void bt_drv_calib_close(void);
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int bt_drv_calib_result_porc(uint32_t *capval);
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void bt_drv_calib_rxonly_porc(void);
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void btdrv_write_localinfo(const char *name, uint8_t len, const uint8_t *addr);
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void btdrv_disable_scan(void);
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void bt_drv_bt_tport_type_config(void);
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void bt_drv_rf_reset(void);
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void btdrv_sleep_config(uint8_t sleep_en);
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void btdrv_feature_default(void);
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void btdrv_test_mode_addr_set(void);
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int btdrv_meinit_param_init(void);
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int btdrv_meinit_param_remain_size_get(void);
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int btdrv_meinit_param_next_entry_get(uint32_t *addr, uint32_t *val);
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uint32_t btdrv_rf_get_max_xtal_tune_ppb(void);
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uint32_t btdrv_rf_get_xtal_tune_factor(void);
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void btdrv_rf_init_xtal_fcap(uint32_t fcap);
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uint32_t btdrv_rf_get_init_xtal_fcap(void);
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uint32_t btdrv_rf_get_xtal_fcap(void);
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void btdrv_rf_set_xtal_fcap(uint32_t fcap, uint8_t is_direct);
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int btdrv_rf_xtal_fcap_busy(uint8_t is_direct);
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void btdrv_rf_bit_offset_track_enable(bool enable);
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uint32_t btdrv_rf_bit_offset_get(void);
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void btdrv_uart_bridge_loop(void);
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void btdrv_testmode_data_overide(void);
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void btdrv_set_bt_pcm_triggler_delay(uint8_t delay);
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void btdrv_set_bt_pcm_en(uint8_t en);
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uint16_t btdrv_rf_bitoffset_get(uint8_t conidx);
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void btdrv_syn_clr_trigger(void);
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uint32_t btdrv_rf_bit_offset_get(void);
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uint32_t btdrv_syn_get_curr_ticks(void);
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uint32_t bt_syn_get_curr_ticks(uint16_t conhdl);
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int32_t bt_syn_get_offset_ticks(uint16_t conhdl);
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void bt_syn_set_tg_ticks(uint32_t val,uint16_t conhdl, uint8_t mode);
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void bt_syn_trig_checker(uint16_t conhdl);
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void btdrv_syn_trigger_codec_en(uint32_t v);
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uint32_t btdrv_get_syn_trigger_codec_en(void);
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uint32_t btdrv_get_trigger_ticks(void);
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#define ACL_TRIGGLE_MODE 1
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#define SCO_TRIGGLE_MODE 2
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void btdrv_enable_playback_triggler(uint8_t triggle_mode);
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void btdrv_disable_playback_triggler(void);
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void btdrv_set_bt_pcm_triggler_en(uint8_t en);
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void btdrv_set_bt_pcm_triggler_delay(uint8_t delay);
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void btdrv_set_bt_pcm_triggler_delay_reset(uint8_t delay);
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void btdrv_set_pcm_data_ignore_crc(void);
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uint8_t btdrv_conhdl_to_linkid(uint16_t connect_hdl);
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void btdrv_set_tws_role_triggler(uint8_t tws_mode);
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void btdrv_enable_dual_slave_configurable_slot_mode(bool isEnable,
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uint16_t activeDevHandle, uint8_t activeDevRole,
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uint16_t idleDevHandle, uint8_t idleDevRole);
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void btdrv_ins_patch_test_init(void);
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void btdrv_dynamic_patch_moble_disconnect_reason_hacker(uint16_t hciHandle);
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void btdrv_dynamic_patch_sco_status_clear(void);
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uint32_t btdrv_dut_get_connect_status(void);
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void btdrv_set_powerctrl_rssi_low(uint16_t rssi);
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void btdrv_seq_bak_mode(uint8_t mode,uint8_t linkid);
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void btdrv_enable_one_packet_more_head(bool enable);
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#if defined(CHIP_BEST2300) || defined(CHIP_BEST1400) || defined(CHIP_BEST1402) || \
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defined(CHIP_BEST2300P) || defined(CHIP_BEST2001) || defined(CHIP_BEST2300A)
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void btdrv_linear_format_16bit_set(void);
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void btdrv_pcm_enable(void);
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void btdrv_pcm_disable(void);
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void btdrv_spi_trig_data_change(uint8_t spi_sel, uint8_t index, uint32_t value);
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void btdrv_spi_trig_data_set(uint8_t spi_sel);
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uint8_t btdrv_get_spi_trig_enable(uint8_t spi_sel);
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void btdrv_set_spi_trig_enable(uint8_t spi_sel);
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void btdrv_clear_spi_trig_enable(uint8_t spi_sel);
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void btdrv_spi_trig_init(void);
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void btdrv_spi_trig_select(uint8_t link_id, bool spi_set);
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void bt_drv_reg_op_cs_monitor(void);
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void btdrv_set_controller_trace_enable(uint8_t trace_level);
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uint8_t btdrv_get_controller_trace_level(void);
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bool btdrv_get_lmp_trace_enable(void);
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void btdrv_set_lmp_trace_enable(void);
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#endif
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void bt_drv_hwspi_select(uint8_t link_id, uint8_t spi_idx);
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void bt_drv_enable_hw_spi(uint8_t elt_idx, bool hwspien);
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bool btdrv_get_controller_trace_dump_enable(void);
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void btdrv_set_controller_trace_dump_enable(void);
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void beshci_enable_sleep_checker(bool isEnable);
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void beshci_set_intersys_trace_enable(void);
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void beshci_set_supv_hci_buff_trace_enable(void);
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void beshci_set_a2dp_stream_trace_enable(bool enable);
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void btdrv_send_cmd(uint16_t opcode,uint8_t cmdlen,const uint8_t *param);
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void btdrv_write_memory(uint8_t wr_type,uint32_t address,const uint8_t *value,uint8_t length);
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void bt_drv_patch_force_disconnect_ack(void);
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void bt_drv_reg_op_music_link_config(uint16_t active_link,uint8_t active_role,uint16_t inactive_link,uint8_t inactive_role);
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struct bt_cb_tag* bt_drv_get_func_cb_ptr(void);
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void btdrv_memory_copy(uint32_t *dest,const uint32_t *src,uint16_t length);
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#if defined(TX_RX_PCM_MASK)
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uint8_t btdrv_is_pcm_mask_enable(void);
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#endif
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void btdrv_set_lpo_times(void);
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#if defined(PCM_FAST_MODE)
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void btdrv_open_pcm_fast_mode_enable(void);
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void btdrv_open_pcm_fast_mode_disable(void);
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#endif
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#if defined(CVSD_BYPASS)
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void btdrv_cvsd_bypass_enable(uint8_t is_msbc);
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#endif
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void bt_drv_reg_op_write_private_public_key(uint8_t* private_key,uint8_t* public_key);
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#define BTCLK_STATUS_PRINT() do{ \
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TRACE("[%s] %d: curr bt time= %d", __func__, __LINE__, bt_syn_get_curr_ticks(app_tws_get_tws_conhdl())); \
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}while(0)
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#define IS_ENABLE_BT_DRIVER_REG_DEBUG_READING 0
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void bt_drv_reg_op_acl_tx_silence(uint16_t connHandle, uint8_t on);
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int btdrv_slave2master_clkcnt_convert(uint32_t local_clk, uint16_t local_cnt,
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int32_t clk_offset, uint16_t bit_offset,
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uint32_t *master_clk, uint16_t *master_cnt);
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int btdrv_clkcnt_diff(int32_t clk1, int16_t cnt1,
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int32_t clk2, int16_t cnt2,
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int32_t *diff_clk, uint16_t *diff_bit);
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bool bt_drv_reg_op_set_ble_conn_latency(uint16_t ble_conhdl, uint16_t conn_latency);
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uint16_t bt_drv_reg_op_get_ble_conn_latency(uint16_t ble_conhdl);
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void bt_drv_reg_op_set_reconnecting_flag();
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uint32_t bt_drv_reg_op_get_reconnecting_flag();
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void bt_drv_reg_op_clear_reconnecting_flag();
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bool bt_drv_is_enhanced_ibrt_rom(void);
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bool bt_drv_is_bes_fa_mode_en(void);
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bool bt_drv_is_support_multipoint_ibrt(void);
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uint16_t bt_drv_reg_op_get_ibrt_sco_hdl(uint16_t acl_hdl);
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void bt_drv_reg_op_get_ibrt_address(uint8_t *addr);
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void btdrv_enable_rf_sw(int rx_on, int tx_on);
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void btdrv_trigger_coredump(void);
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bool btdrv_is_ecc_enable(void);
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void bt_drv_adaptive_fa_rx_gain(int8_t rssi);
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void* bt_drv_get_btstack_chip_config(void);
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void btdrv_spi_sel_ble_setf(int elt_idx, uint8_t spiselble);
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bool bt_drv_is_esco_auto_accept_support(void);
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void bt_drv_reg_op_set_hwagc_read_en(uint8_t en);
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#if defined(IBRT)
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bool btdrv_is_acl_ecc_softbit_support(void);
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void btdrv_softbit_enable(uint16_t connhdl, uint8_t type1,uint8_t type2,uint8_t type3, uint8_t num);
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#endif
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void btdrv_play_trig_mode_set(uint8_t mode);
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#ifdef __SW_TRIG__
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void btdrv_sw_trig_master_set(uint32_t Tclk_M, int16_t Tbit_M_h_ori);
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void btdrv_sw_trig_slave_calculate_and_set(uint16_t conhdl, uint32_t Tclk_M, int16_t Tbit_M_h_ori);
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void btdrv_sync_sw_trig_store_tws_role(uint8_t role);
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uint8_t btdrv_sync_sw_trig_get_tws_role(void);
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void btdrv_sync_sw_trig_store_conhdl(uint16_t conhdl);
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uint16_t btdrv_sync_sw_trig_get_conhdl(void);
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void btdrv_sync_sw_trig_store_tws_conhdl(uint16_t conhdl);
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uint16_t btdrv_sync_sw_trig_get_tws_conhdl(void);
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uint16_t btdrv_sw_trig_tg_finecnt_get(void);
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int32_t bt_syn_get_clkoffset(uint16_t conhdl);
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void btdrv_sync_sw_trig_store_tg_clkoffset(int32_t clkoffset);
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int32_t btdrv_sync_sw_trig_get_tg_clkoffset(void);
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void btdrv_sync_sw_trig_store_tg_finecnt(uint16_t finecnt);
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uint16_t btdrv_sync_sw_trig_get_tg_finecnt(void);
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#endif
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#if defined(PCM_FAST_MODE) && defined(PCM_PRIVATE_DATA_FLAG)
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void bt_drv_reg_op_set_pcm_flag();
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#endif
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#ifdef __SELF_TRIG__
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void btdrv_self_trig_gen_set(uint8_t en);
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void btdrv_trig_playtime_stamp_en(uint8_t en);
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#endif
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void bt_drv_productiontest_settings_checker(void);
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#if (defined(SOFTBIT_EN))
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void btdrv_softbit_config(uint16_t connhdl, uint8_t type1,uint8_t type2,uint8_t type3, uint8_t num);
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#endif
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#ifdef __IBRT_IBRT_TESTMODE__
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void btdrv_enable_ibrt_test(void);
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void btdrv_connect_ibrt_device(uint8_t *addr);
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#endif
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void bt_drv_select_agc_mode(enum BT_WORK_MODE_T mode);
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bool bt_drv_error_check_handler(void);
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void bt_drv_rssi_dump_handler(void);
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#ifdef VCO_TEST_TOOL
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//vco test callback
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bool btdrv_vco_test_bridge_intsys_callback(const unsigned char *data);
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void btdrv_vco_test_process(uint8_t op);
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unsigned short btdrv_get_vco_test_process_flag(void);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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