102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __ARM_ARCH_ISA_ARM
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#include "system_ARMCM.h"
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#include "cmsis.h"
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#include "hal_location.h"
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void BOOT_TEXT_FLASH_LOC SystemInit(void) {
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#if (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
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(3UL << 11 * 2)); /* set CP11 Full Access */
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#endif
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SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
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#ifdef __ARM_ARCH_8M_MAIN__
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// Disable stack limit check on hard fault, NMI and reset
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// (The check will generate STKOF usage fault)
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SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
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#endif
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#ifdef UNALIGNED_ACCESS
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SCB->CCR &= ~SCB_CCR_UNALIGN_TRP_Msk;
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#else
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SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
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#endif
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#ifdef USAGE_FAULT
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
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NVIC_SetPriority(UsageFault_IRQn, IRQ_PRIORITY_REALTIME);
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#else
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SCB->SHCSR &= ~SCB_SHCSR_USGFAULTENA_Msk;
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#endif
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#ifdef BUS_FAULT
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SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
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NVIC_SetPriority(BusFault_IRQn, IRQ_PRIORITY_REALTIME);
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#else
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SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTENA_Msk;
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#endif
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#ifdef MEM_FAULT
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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NVIC_SetPriority(MemoryManagement_IRQn, IRQ_PRIORITY_REALTIME);
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#else
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SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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TZ_SAU_Setup();
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#endif
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}
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#ifndef UNALIGNED_ACCESS
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bool get_unaligned_access_status(void) {
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return !(SCB->CCR & SCB_CCR_UNALIGN_TRP_Msk);
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}
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bool config_unaligned_access(bool enable) {
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bool en;
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en = !(SCB->CCR & SCB_CCR_UNALIGN_TRP_Msk);
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if (enable) {
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SCB->CCR &= ~SCB_CCR_UNALIGN_TRP_Msk;
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} else {
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SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
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}
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return en;
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}
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#endif
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// -----------------------------------------------------------
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// CPU ID
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// -----------------------------------------------------------
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uint32_t BOOT_TEXT_SRAM_DEF(get_cpu_id)(void) {
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#ifdef CHIP_HAS_CP
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#ifdef __ARM_ARCH_8M_MAIN__
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return (SCB->ID_ADR & 3);
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#else /*__ARM_ARCH_8M_MAIN__*/
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return (SCB->ADR & 3);
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#endif /*__ARM_ARCH_8M_MAIN__*/
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#else
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return 0;
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#endif
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}
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#endif
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