202 lines
10 KiB
C
202 lines
10 KiB
C
/**************************************************************************//**
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* @file best2300.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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* ARMCM4 Device Series
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* @version V2.02
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* @date 10. September 2014
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*
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* @note configured for CM4 with FPU
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*
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******************************************************************************/
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/* Copyright (c) 2011 - 2014 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef __BEST2300_H__
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#define __BEST2300_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __ASSEMBLER__
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
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/* ---------------------- BEST1000 Specific Interrupt Numbers --------------------- */
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FPU_IRQn = 0, /*!< FPU Interrupt */
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SENSOR_WKUP_IRQn = 1, /*!< SENSOR Wakeup Interrupt */
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SDMMC_IRQn = 2, /*!< SDMMC Interrupt */
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AUDMA_IRQn = 3, /*!< Audio DMA Interrupt */
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GPDMA_IRQn = 4, /*!< General Purpose DMA Interrupt */
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AON_WDT_IRQn = 5, /*!< AON Watchdog Timer Interrupt */
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USB_PHY_IRQn = 6, /*!< USB PHY Interrupt */
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USB_IRQn = 7, /*!< USB Interrupt */
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WAKEUP_IRQn = 8, /*!< Wakeup Interrupt */
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AON_GPIO_IRQn = 9, /*!< AON GPIO Interrupt */
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MCU_WDT_IRQn = 10, /*!< Watchdog Timer Interrupt */
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RESERVED11_IRQn = 11, /*!< Reserved Interrupt */
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MCU_TIMER00_IRQn = 12, /*!< Timer00 Interrupt */
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MCU_TIMER01_IRQn = 13, /*!< Timer01 Interrupt */
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I2C0_IRQn = 14, /*!< I2C0 Interrupt */
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SPI0_IRQn = 15, /*!< SPI0 Interrupt */
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SPILCD_IRQn = 16, /*!< SPILCD Interrupt */
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UART0_IRQn = 17, /*!< UART0 Interrupt */
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UART1_IRQn = 18, /*!< UART1 Interrupt */
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CODEC_IRQn = 19, /*!< CODEC Interrupt */
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BTPCM_IRQn = 20, /*!< BTPCM Interrupt */
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I2S0_IRQn = 21, /*!< I2S0 Interrupt */
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SPDIF0_IRQn = 22, /*!< SPDIF0 Interrupt */
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ITNSPI_IRQn = 23, /*!< Internal SPI Interrupt */
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BT_IRQn = 24, /*!< BT to MCU Interrupt */
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RESERVED25_IRQn = 25, /*!< Reserved Interrupt */
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UART2_IRQn = 26, /*!< UART2 Interrupt */
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MCU_TIMER10_IRQn = 27, /*!< Timer10 Interrupt */
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MCU_TIMER11_IRQn = 28, /*!< Timer11 Interrupt */
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I2C1_IRQn = 29, /*!< I2C1 Interrupt */
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DUMP_IRQn = 30, /*!< DUMP Interrupt */
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SPIPHY_IRQn = 31, /*!< SPIPHY Interrupt */
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ISDONE_IRQn = 32, /*!< Intersys MCU2BT Data Done Interrupt */
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ISDONE1_IRQn = 33, /*!< Intersys MCU2BT Data1 Done Interrupt */
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ISDATA_IRQn = 34, /*!< Intersys BT2MCU Data Indication Interrupt */
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ISDATA1_IRQn = 35, /*!< Intersys BT2MCU Data1 Indication Interrupt */
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SENSOR0_IRQn = 36, /*!< SENSOR0 Interrupt */
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SENSOR1_IRQn = 37, /*!< SENSOR1 Interrupt */
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SENSOR2_IRQn = 38, /*!< SENSOR2 Interrupt */
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SENSOR3_IRQn = 39, /*!< SENSOR3 Interrupt */
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USB_CAL_IRQn = 40, /*!< USB Calibration Interrupt */
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USB_PIN_IRQn = 41, /*!< USB Pin Interrupt */
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PMU_IRQn = 42, /*!< PMU Interrupt */
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RESERVED43_IRQn = 43, /*!< Reserved Interrupt */
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AON_IRQn = 44, /*!< AON Interrupt */
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AON_TIMER00_IRQn = 45, /*!< AON Timer00 Interrupt */
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AON_TIMER01_IRQn = 46, /*!< AON Timer01 Interrupt */
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RESERVED47_IRQn = 47, /*!< Reserved Interrupt */
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USER_IRQn_QTY,
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INVALID_IRQn = USER_IRQn_QTY,
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} IRQn_Type;
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#define GPIO_IRQn AON_GPIO_IRQn
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#define GPADC_IRQn INVALID_IRQn
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#define PWRKEY_IRQn INVALID_IRQn
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#ifdef MCU_SLEEP_POWER_DOWN
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#define TIMER00_IRQn AON_TIMER00_IRQn
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#define TIMER01_IRQn AON_TIMER01_IRQn
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#else
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#define TIMER00_IRQn MCU_TIMER00_IRQn
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#define TIMER01_IRQn MCU_TIMER01_IRQn
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#endif
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#define WDT_IRQn AON_WDT_IRQn
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#endif
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
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#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __VTOR_PRESENT 1U /* VTOR present */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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#define __NUM_CODE_PATCH 56
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#define __NUM_LIT_PATCH 8
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#include "core_cm4.h" /* Processor and core peripherals */
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#ifndef __ASSEMBLER__
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#include "system_ARMCM.h" /* System Header */
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#endif
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/* ------------------- Start of section using anonymous unions ------------------ */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* -------------------- End of section using anonymous unions ------------------- */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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