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Merge pull request #39 from pine64/cleanups-remove-FPGA-buildconfig 

Removing FPGA dev support
This commit is contained in:
Ben V. Brown 2023-02-03 13:36:01 +11:00 committed by GitHub
parent 8a7e040fc7 b319051c35
commit 05b139e61f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
62 changed files with 2179 additions and 5057 deletions
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10
apps/audioplayers/a2dpplay.cpp
View File

@ -52,7 +52,7 @@ extern "C" {
extern "C" {
#if defined(A2DP_LDAC_ON)
#include "hal_sysfreq.h"
//#include "speech_memory.h"
// #include "speech_memory.h"
#include "ldacBT.h"
#define MED_MEM_HEAP_SIZE (1024 * 20)
HANDLE_LDAC_BT hLdacData = NULL;
@ -80,7 +80,7 @@ HANDLE_LDAC_BT hLdacData = NULL;
#define TEXT_LDAC_LOC TEXT_A2DP_LOC(.overlay_a2dp_ldac, __LINE__)
#define TEXT_LHDC_LOC TEXT_A2DP_LOC(.overlay_a2dp_lhdc, __LINE__)
//#define A2DP_AUDIO_SYNC_WITH_LOCAL (1)
// #define A2DP_AUDIO_SYNC_WITH_LOCAL (1)
#define A2DP_AUDIO_SYNC_TRACE(s, ...)
// TRACE(s, ##__VA_ARGS__)
@ -186,7 +186,7 @@ extern int a2dp_timestamp_parser_needsync(void);
} \
} while (0)
//#define A2DP_SYNC_WITH_PUT_MUTUX (1)
// #define A2DP_SYNC_WITH_PUT_MUTUX (1)
#define A2DP_SYNC_WITH_PUT_MUTUX_TIMEROUT_CNT (1)
#define A2DP_SYNC_WITH_PUT_MUTUX_TIMEROUT_MS (3)
static osThreadId a2dp_get_thread_tid = NULL;
@ -770,7 +770,7 @@ int get_ldac_data(unsigned char *frame, unsigned int len) {
/**
* Decode LDAC data...
*/
//#include "os_tcb.h"
// #include "os_tcb.h"
extern const char *get_error_code_string(int error_code);
extern int app_audio_mempool_force_set_buff_used(uint32_t size);
extern uint32_t ldac_buffer_used;
@ -3061,10 +3061,8 @@ uint32_t a2dp_audio_more_data(uint8_t overlay_type, uint8_t *buf,
#endif
if (a2dp_cache_status == APP_AUDIO_CACHE_CACHEING) {
#if FPGA == 0
TRACE(1, "a2dp_audio_more_data cache not ready skip frame %d\n",
overlay_type);
#endif
} else {
#if defined(__AUDIO_RESAMPLE__) && defined(SW_PLAYBACK_RESAMPLE)
if (allow_resample) {

2
apps/audioplayers/app_audio.cpp
View File

@ -293,9 +293,7 @@ static void app_audio_switch_flash_proc(void) {
int_unlock(lock);
if (need_flush_flash) {
#ifndef FPGA
nv_record_flash_flush();
#endif
}
}

18
apps/audioplayers/fmradio.cpp
View File

@ -33,7 +33,7 @@
#include "pmu.h"
#include "string.h"
//#define FM_DEBUG 1
// #define FM_DEBUG 1
#define FM_DIGITAL_REG(a) *(volatile uint32_t *)(a)
#define fm_read_rf_reg(reg, val) hal_analogif_reg_read(reg, val)
@ -145,7 +145,7 @@ void fm_radio_digit_init(void) {
#endif
#ifdef SINGLECHANLE
// 0x4000a010 bit2 写0 单channel dac
// 0x4000a010 bit2 д0 <20><>channel dac
FM_DIGITAL_REG(0x4000a010) = (1 << 5) | (1 << 4);
#else
@ -196,7 +196,7 @@ void fm_radio_digit_init(void) {
0x18000; // for dual channel adc/dac
#ifdef SINGLECHANLE
// 0x4000a050 bit16 写0 单channel dac for codec
// 0x4000a050 bit16 д0 <20><>channel dac for codec
FM_DIGITAL_REG(0x4000a050) = (FM_DIGITAL_REG(0x4000a050) & ~(1 << 16));
#endif
@ -295,10 +295,10 @@ int fm_radio_analog_init(void) {
// frf/(4*reg_bt_vco_fm_div_ctrl)
fm_write_rf_reg(0x17, 0b1000000000000000); // reg_bt_vco_calen
// adc也要开的话，需要配 cmu
// 0x40000060[29] = 1 最好先读再写，否则把别的bit冲掉了。
// adcҲҪ<EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD> cmu
// 0x40000060[29] = 1 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѱ<EFBFBD><EFBFBD>bit<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˡ<EFBFBD>
//需要配置的spi寄存器：ana interface:
// <20><>Ҫ<EFBFBD><D2AA><EFBFBD>õ<EFBFBD>spi<70>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ana interface:
// 0x05 = 0xFCB1 // Audio Pll
// 0x06 = 0x881C
@ -423,9 +423,7 @@ int fm_radio_player(bool on) {
app_audio_pcmbuff_init(buff, FM_AUDIO_BUFFER_SIZE * 2);
fm_sample_buffer_p =
(int32_t *)fm_radio_get_ext_buff(FM_SAMPLE_BUFFER_SIZE);
#if FPGA == 0
app_overlay_select(APP_OVERLAY_FM);
#endif
memset(&stream_cfg, 0, sizeof(stream_cfg));
stream_cfg.vol = app_bt_stream_local_volume_get();
stream_cfg.handler = fm_capture_more_data;
@ -440,11 +438,7 @@ int fm_radio_player(bool on) {
stream_cfg.bits = AUD_BITS_16;
stream_cfg.channel_num = AUD_CHANNEL_NUM_1;
stream_cfg.sample_rate = AUD_SAMPRATE_48000;
#if FPGA == 0
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#else
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#endif
stream_cfg.io_path = AUD_OUTPUT_PATH_SPEAKER;
stream_cfg.vol = app_bt_stream_local_volume_get();
stream_cfg.handler = fm_pcm_more_data;

14
apps/audioplayers/voicebtpcmplay.cpp
View File

@ -87,7 +87,7 @@ static bool echo_buf_q_full;
static void *speech_plc;
}
//#define PENDING_MSBC_DECODER_ALG
// #define PENDING_MSBC_DECODER_ALG
// #define SPEECH_RX_PLC_DUMP_DATA
@ -146,11 +146,6 @@ extern bool bt_sco_codec_is_msbc(void);
#define MSBC_FRAME_SIZE (60)
#if defined(HFP_1_6_ENABLE)
static btif_sbc_decoder_t msbc_decoder;
#if FPGA == 1
#define CFG_HW_AUD_EQ_NUM_BANDS (8)
const int8_t cfg_hw_aud_eq_band_settings[CFG_HW_AUD_EQ_NUM_BANDS] = {
0, 0, 0, 0, 0, 0, 0, 0};
#endif
static float msbc_eq_band_gain[CFG_HW_AUD_EQ_NUM_BANDS] = {0, 0, 0, 0,
0, 0, 0, 0};
@ -1789,11 +1784,8 @@ uint32_t voicebtpcm_pcm_audio_more_data(uint8_t *buf, uint32_t len) {
uint32_t l = 0;
// TRACE(3,"[%s]: pcm_len = %d, %d", __FUNCTION__, len / 2,
// FAST_TICKS_TO_US(hal_fast_sys_timer_get()));
if ((voicebtpcm_cache_m2p_status == APP_AUDIO_CACHE_CACHEING)
#ifndef FPGA
|| (app_get_current_overlay() != APP_OVERLAY_HFP)
#endif
) {
if ((voicebtpcm_cache_m2p_status == APP_AUDIO_CACHE_CACHEING) ||
(app_get_current_overlay() != APP_OVERLAY_HFP)) {
app_audio_memset_16bit((short *)buf, 0, len / 2);
l = len;
} else {

4
apps/factory/app_factory_audio.cpp
View File

@ -93,11 +93,7 @@ int app_factorymode_audioloop(bool on, enum APP_SYSFREQ_FREQ_T freq) {
#else
stream_cfg.sample_rate = AUD_SAMPRATE_8000;
#endif
#if FPGA == 0
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#else
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#endif
stream_cfg.vol = TGT_VOLUME_LEVEL_15;
stream_cfg.io_path = AUD_INPUT_PATH_MAINMIC;
stream_cfg.handler = app_factorymode_data_come;

6
apps/main/apps.cpp
View File

@ -161,10 +161,6 @@ extern "C" void ota_flash_init(void);
#define APP_BATTERY_LEVEL_LOWPOWERTHRESHOLD (1)
#define POWERON_PRESSMAXTIME_THRESHOLD_MS (5000)
#ifdef FPGA
uint32_t __ota_upgrade_log_start[100];
#endif
enum APP_POWERON_CASE_T {
APP_POWERON_CASE_NORMAL = 0,
APP_POWERON_CASE_DITHERING,
@ -2095,12 +2091,10 @@ int app_deinit(int deinit_case) {
app_thirdparty_specific_lib_event_handle(THIRDPARTY_FUNC_NO1,
THIRDPARTY_DEINIT);
#endif
#if FPGA == 0
nv_record_flash_flush();
norflash_api_flush_all();
#if defined(DUMP_LOG_ENABLE)
log_dump_flush_all();
#endif
#endif
osDelay(1000);
af_close();

2
config/bak_open/target.mk
View File

@ -2,8 +2,6 @@ CHIP ?= best2300p
DEBUG ?= 1
FPGA ?= 0
MBED ?= 0
RTOS ?= 1

2
config/best2300p_ibrt/target.mk
View File

@ -2,8 +2,6 @@ CHIP ?= best2300p
DEBUG ?= 1
FPGA ?= 0
MBED ?= 0
RTOS ?= 1

2
config/best2300p_ibrt_anc/target.mk
View File

@ -2,8 +2,6 @@ CHIP ?= best2300p
DEBUG ?= 1
FPGA ?= 0
MBED ?= 0
RTOS ?= 1

44
config/common.mk
View File

@ -195,11 +195,7 @@ endif
# ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ifeq ($(OTA_ENABLE),1)
ifeq ($(FPGA),1)
OTA_CODE_OFFSET := 0
else
OTA_CODE_OFFSET := 0x18000
endif
OTA_UPGRADE_LOG_SIZE := 0x1000
OTA_SUPPORT_SLAVE_BIN := 0
@ -515,34 +511,6 @@ export CHIP_FLASH_CTRL_VER := 2
export CHIP_SPI_VER := 4
export CHIP_HAS_DCO ?= 1
export NO_LPU_26M ?= 1
else ifeq ($(CHIP),fpga1000)
KBUILD_CPPFLAGS += -DCHIP_FPGA1000
KBUILD_CPPFLAGS += -DCHIP_BEST1000
CPU := m4
export CHIP_HAS_FPU := 1
export CHIP_HAS_USB := 1
export CHIP_HAS_USBPHY := 0
export CHIP_HAS_SDMMC := 1
export CHIP_HAS_SDIO := 1
export CHIP_HAS_PSRAM := 1
export CHIP_HAS_SPI := 1
export CHIP_HAS_SPILCD := 1
export CHIP_HAS_SPIPHY := 0
export CHIP_HAS_I2C := 1
export CHIP_HAS_UART := 2
export CHIP_HAS_DMA := 2
export CHIP_INTERSYS_VER := 2
export CHIP_HAS_SPDIF := 1
export CHIP_HAS_TRANSQ := 0
export CHIP_HAS_EXT_PMU := 0
export CHIP_HAS_AUDIO_CONST_ROM := 1
export CHIP_FLASH_CTRL_VER := 1
export CHIP_PSRAM_CTRL_VER := 1
export CHIP_SPI_VER := 1
export CHIP_HAS_EC_CODEC_REF := 0
export CHIP_HAS_SCO_DMA_SNAPSHOT := 0
export CHIP_ROM_UTILS_VER := 1
export NO_LPU_26M ?= 1
else
$(error Invalid CHIP: $(CHIP))
endif
@ -1005,18 +973,6 @@ KBUILD_CPPFLAGS += -DSIMU
endif
# -------------------------------------------
# FPGA functions
# -------------------------------------------
export FPGA
ifeq ($(FPGA),1)
KBUILD_CPPFLAGS += -DFPGA
endif
# -------------------------------------------
# ROM_BUILD functions
# -------------------------------------------

2
config/mic_alg/target.mk
View File

@ -2,8 +2,6 @@ CHIP ?= best2300p
DEBUG ?= 1
FPGA ?= 0
MBED ?= 0
RTOS ?= 1

2
config/open_source/target.mk
View File

@ -2,8 +2,6 @@ CHIP ?= best2300p
DEBUG ?= 1
FPGA ?= 0
MBED ?= 0
RTOS ?= 1

175
platform/cmsis/inc/fpga1000.h
View File

@ -1,175 +0,0 @@
/**************************************************************************//**
* @file best1000.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM4 Device Series
* @version V2.02
* @date 10. September 2014
*
* @note configured for CM4 with FPU
*
******************************************************************************/
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __FPGA1000_H__
#define __FPGA1000_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __ASSEMBLER__
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/* ---------------------- BEST1000 Specific Interrupt Numbers --------------------- */
FPU_IRQn = 0, /*!< FPU Interrupt */
SDIO_IRQn = 1, /*!< SDIO Interrupt */
SDMMC_IRQn = 2, /*!< SDMMC Interrupt */
AUDMA_IRQn = 3, /*!< Audio DMA Interrupt */
GPDMA_IRQn = 4, /*!< General Purpose DMA Interrupt */
DPDRX_IRQn = 5, /*!< DPD RX Interrupt */
DPDTX_IRQn = 6, /*!< DPD TX Interrupt */
USB_IRQn = 7, /*!< USB Interrupt */
WAKEUP_IRQn = 8, /*!< Reserved Interrupt */
GPIO_IRQn = 9, /*!< GPIO Interrupt */
WDT_IRQn = 10, /*!< Watchdog Timer Interrupt */
RTC_IRQn = 11, /*!< RTC Interrupt */
TIMER00_IRQn = 12, /*!< Timer00 Interrupt */
TIMER01_IRQn = 13, /*!< Timer01 Interrupt */
I2C0_IRQn = 14, /*!< I2C0 Interrupt */
SPI0_IRQn = 15, /*!< SPI0 Interrupt */
SPILCD_IRQn = 16, /*!< SPILCD Interrupt */
UART0_IRQn = 17, /*!< UART0 Interrupt */
UART1_IRQn = 18, /*!< UART1 Interrupt */
CODEC_IRQn = 19, /*!< CODEC Interrupt */
BTPCM_IRQn = 20, /*!< BTPCM Interrupt */
I2S0_IRQn = 21, /*!< I2S0 Interrupt */
SPDIF_IRQn = 22, /*!< SPDIF Interrupt */
ITNSPI_IRQn = 23, /*!< Reserved Interrupt */
BT_IRQn = 24, /*!< Reserved Interrupt */
GPADC_IRQn = 25, /*!< Reserved Interrupt */
NONE4_IRQn = 26, /*!< Reserved Interrupt */
USB_PIN_IRQn = 27, /*!< Reserved Interrupt */
ISDONE_IRQn = 28, /*!< Intersys MCU2BT Data Done Interrupt */
ISDONE1_IRQn = 29, /*!< Intersys MCU2BT Data1 Done Interrupt */
ISDATA_IRQn = 30, /*!< Intersys BT2MCU Data Indication Interrupt */
ISDATA1_IRQn = 31, /*!< Intersys BT2MCU Data1 Indication Interrupt */
CHARGER_IRQn = 32, /*!< Charger IRQ */
PWRKEY_IRQn = 33, /*!< Power key IRQ */
USER_IRQn_QTY,
INVALID_IRQn = USER_IRQn_QTY,
} IRQn_Type;
#endif
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __NUM_CODE_PATCH 32
#define __NUM_LIT_PATCH 32
#include "core_cm4.h" /* Processor and core peripherals */
#ifndef __ASSEMBLER__
#include "system_ARMCM.h" /* System Header */
#endif
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------------------- End of section using anonymous unions ------------------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
#endif

4
platform/cmsis/system_utils.c
View File

@ -88,11 +88,7 @@ void BOOT_TEXT_FLASH_LOC BootInit(void) {
*dst = 0;
}
#ifdef FPGA
hal_cmu_fpga_setup();
#else
hal_cmu_setup();
#endif
for (dst = __sram_text_data_start__, src = __sram_text_data_start_flash__;
src < __sram_text_data_end_flash__; dst++, src++) {

29
platform/drivers/ana/best2300p/pmu_best2300p.c
View File

@ -892,7 +892,7 @@
#define POWER_ON_PRESS (1 << 10)
#define POWER_ON (1 << 9)
#define DEEPSLEEP_MODE (1 << 8)
//#define PMU_LDO_ON (1 << 7)
// #define PMU_LDO_ON (1 << 7)
#define PU_OSC_OUT (1 << 6)
#define UVLO_LV (1 << 5)
#define AC_ON_DET_OUT_MASKED (1 << 4)
@ -1248,7 +1248,7 @@ void pmu_wdt_restore_context(void);
void pmu_charger_save_context(void);
void pmu_charger_shutdown_config(void);
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
static void pmu_hppa_dcdc_to_ldo(void);
#endif
@ -1471,7 +1471,7 @@ uint32_t BOOT_TEXT_FLASH_LOC read_hw_metal_id(void) {
pmu_write(PMU_REG_METAL_ID, 0x5FEE);
hal_sys_timer_delay(US_TO_TICKS(500));
#if defined(PMU_FULL_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_FULL_INIT) || (!defined(PROGRAMMER))
// Reset RF
pmu_write(PMU_REG_RF_80, 0xCAFE);
pmu_write(PMU_REG_RF_80, 0x5FEE);
@ -1513,8 +1513,7 @@ uint32_t BOOT_TEXT_FLASH_LOC read_hw_metal_id(void) {
SAFE_PROGRAM_STOP();
}
#if !defined(FPGA) && !defined(PROGRAMMER) && \
!defined(MCU_HIGH_PERFORMANCE_MODE)
#if !defined(PROGRAMMER) && !defined(MCU_HIGH_PERFORMANCE_MODE)
if (hal_cmu_get_crystal_freq() != hal_cmu_get_default_crystal_freq()) {
// Update bbpll freq after resetting RF and getting crystal freq
bbpll_freq_pll_config(384000000);
@ -1700,7 +1699,7 @@ int BOOT_TEXT_SRAM_LOC pmu_get_efuse(enum PMU_EFUSE_PAGE_T page,
unsigned short *efuse) {
int ret;
//#if defined(USE_CYBERON)
// #if defined(USE_CYBERON)
#if 0
if (cyb_efuse_check_status()) {
PMU_DEBUG_TRACE(2,"page %x, efuse %x", page, efuse);
@ -1762,7 +1761,7 @@ static void pmu_sys_ctrl(bool shutdown) {
PMU_INFO_TRACE_IMM(0, "Start pmu %s", shutdown ? "shutdown" : "reboot");
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
#if defined(MCU_HIGH_PERFORMANCE_MODE)
// Default vcore might not be high enough to support high performance mode
pmu_high_performance_mode_enable(false);
@ -1794,7 +1793,7 @@ static void pmu_sys_ctrl(bool shutdown) {
}
#endif
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
pmu_wdt_config(3 * 1000, 3 * 1000);
pmu_wdt_start();
pmu_charger_shutdown_config();
@ -1814,7 +1813,7 @@ static void pmu_sys_ctrl(bool shutdown) {
PMU_INFO_TRACE_IMM(0, "\nError: pmu shutdown failed!\n");
hal_sys_timer_delay(MS_TO_TICKS(5));
} else {
#if defined(PMU_FULL_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_FULL_INIT) || (!defined(PROGRAMMER))
// CAUTION:
// 1) Never reset RF because system or flash might be using X2/X4, which are
// off by default 2) Never reset RF/ANA because system or flash might be
@ -2401,7 +2400,7 @@ void pmu_sleep_en(unsigned char sleep_en) {
pmu_write(PMU_REG_SLEEP_CFG, val);
}
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
static uint32_t pmu_vcodec_mv_to_val(uint16_t mv) {
uint32_t val;
@ -2709,7 +2708,7 @@ int pmu_codec_volt_ramp_down(void) {
#endif
int BOOT_TEXT_FLASH_LOC pmu_open(void) {
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
uint16_t val;
enum PMU_POWER_MODE_T mode;
@ -2919,7 +2918,7 @@ int BOOT_TEXT_FLASH_LOC pmu_open(void) {
pmu_write(PMU_REG_DCDC_HPPA_CFG_1A, 0x8E1F);
pmu_write(PMU_REG_DCDC_DIG_CFG_33, 0x8E1F);
}
#endif // PMU_INIT || (!FPGA && !PROGRAMMER)
#endif // PMU_INIT || (!PROGRAMMER)
return 0;
}
@ -3158,7 +3157,7 @@ SRAM_TEXT_LOC void pmu_flash_read_config(void) {
}
void BOOT_TEXT_FLASH_LOC pmu_flash_freq_config(uint32_t freq) {
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
uint32_t lock;
lock = int_lock();
@ -3181,7 +3180,7 @@ void BOOT_TEXT_FLASH_LOC pmu_flash_freq_config(uint32_t freq) {
}
void BOOT_TEXT_FLASH_LOC pmu_psram_freq_config(uint32_t freq) {
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
uint32_t lock;
lock = int_lock();
@ -3223,7 +3222,7 @@ void pmu_rs_freq_config(uint32_t freq) {
}
void BOOT_TEXT_SRAM_LOC pmu_sys_freq_config(enum HAL_CMU_FREQ_T freq) {
#if defined(PMU_INIT) || (!defined(FPGA) && !defined(PROGRAMMER))
#if defined(PMU_INIT) || (!defined(PROGRAMMER))
#if defined(MCU_HIGH_PERFORMANCE_MODE) || defined(ULTRA_LOW_POWER) || \
!defined(OSC_26M_X4_AUD2BB)
uint32_t lock;

609
platform/drivers/bt/bt_drv.h
View File

@ -14,7 +14,7 @@
*
****************************************************************************/
#ifndef __BT_DRV_H__
#define __BT_DRV_H__
#define __BT_DRV_H__
#ifdef __cplusplus
extern "C" {
@ -29,445 +29,419 @@ extern "C" {
#include "hal_analogif.h"
#include "hal_trace.h"
#define BT_DRV_REG_OP_ENTER() do{ uint32_t stime, spent_time; stime= hal_sys_timer_get();
#define BT_DRV_REG_OP_EXIT() spent_time = TICKS_TO_US(hal_sys_timer_get()-stime);if (spent_time>300)TRACE(2,"%s exit, %dus",__func__, spent_time);}while(0);
#define BT_DRV_REG_OP_ENTER() \
do { \
uint32_t stime, spent_time; \
stime = hal_sys_timer_get();
#define BT_DRV_REG_OP_EXIT() \
spent_time = TICKS_TO_US(hal_sys_timer_get() - stime); \
if (spent_time > 300) \
TRACE(2, "%s exit, %dus", __func__, spent_time); \
} \
while (0) \
;
#define SBC_PKT_TYPE_DM1 0x3
#define SBC_PKT_TYPE_2EV3 0x6
#define SBC_PKT_TYPE_2DH5 0xe
#define SBC_PKT_TYPE_DM1 0x3
#define SBC_PKT_TYPE_2EV3 0x6
#define SBC_PKT_TYPE_2DH5 0xe
#define BT_ACL_CONHDL_BIT (0x80)
#define BT_ACL_CONHDL_BIT (0x80)
#if defined(CHIP_BEST1400) || defined(CHIP_BEST1402) || defined(CHIP_BEST2001)
#define BTDRV_ISPI_RF_REG(reg) (((reg) & 0xFFF) | 0x2000)
#define BTDRV_ISPI_RF_REG(reg) (((reg)&0xFFF) | 0x2000)
#else
#define BTDRV_ISPI_RF_REG(reg) (reg)
#define BTDRV_ISPI_RF_REG(reg) (reg)
#endif
#define btdrv_read_rf_reg(reg,val) hal_analogif_reg_read(BTDRV_ISPI_RF_REG(reg),val)
#define btdrv_write_rf_reg(reg,val) hal_analogif_reg_write(BTDRV_ISPI_RF_REG(reg),val)
#define btdrv_read_rf_reg(reg, val) \
hal_analogif_reg_read(BTDRV_ISPI_RF_REG(reg), val)
#define btdrv_write_rf_reg(reg, val) \
hal_analogif_reg_write(BTDRV_ISPI_RF_REG(reg), val)
#define btdrv_delay(ms) hal_sys_timer_delay(MS_TO_TICKS(ms))
#define btdrv_delay(ms) hal_sys_timer_delay(MS_TO_TICKS(ms))
#define BTDIGITAL_REG(a) (*(volatile uint32_t *)(uintptr_t)(a))
#define BTDIGITAL_REG_WR(addr, value) \
(*(volatile uint32_t *)(uintptr_t)(addr)) = (value)
#define BTDIGITAL_REG(a) (*(volatile uint32_t *)(uintptr_t)(a))
#define BTDIGITAL_REG_WR(addr, value) (*(volatile uint32_t *)(uintptr_t)(addr)) = (value)
#define BTDIGITAL_BT_EM(a) (*(volatile uint16_t *)(uintptr_t)(a))
#define BTDIGITAL_BT_EM(a) (*(volatile uint16_t *)(uintptr_t)(a))
/// Macro to write a BT control structure field (16-bit wide)
#define BTDIGITAL_EM_BT_WR(addr, value) (*(volatile uint16_t *)(uintptr_t)(addr)) = (value)
#define BTDIGITAL_EM_BT_WR(addr, value) \
(*(volatile uint16_t *)(uintptr_t)(addr)) = (value)
#define BTDIGITAL_REG_SET_FIELD(reg, mask, shift, v)\
do{ \
volatile unsigned int tmp = *(volatile unsigned int *)(reg); \
tmp &= ~(mask<<shift); \
tmp |= (v<<shift); \
*(volatile unsigned int *)(reg) = tmp; \
}while(0)
#define BTDIGITAL_REG_SET_FIELD(reg, mask, shift, v) \
do { \
volatile unsigned int tmp = *(volatile unsigned int *)(reg); \
tmp &= ~(mask << shift); \
tmp |= (v << shift); \
*(volatile unsigned int *)(reg) = tmp; \
} while (0)
#define BTDIGITAL_REG_GET_FIELD(reg, mask, shift, v)\
do{ \
volatile unsigned int tmp = *(volatile unsigned int *)(reg); \
v = (tmp>>shift)&mask; \
}while(0)
#define BTDIGITAL_REG_GET_FIELD(reg, mask, shift, v) \
do { \
volatile unsigned int tmp = *(volatile unsigned int *)(reg); \
v = (tmp >> shift) & mask; \
} while (0)
#define BT_DRV_DEBUG 0
#define BT_DRV_DEBUG 0
#if BT_DRV_DEBUG
#define BT_DRV_TRACE(n, fmt, ...) TRACE(n, fmt, ##__VA_ARGS__)
#define BT_DRV_DUMP(s,buff,len) DUMP8(s,buff,len)
#define BT_DRV_DUMP(s, buff, len) DUMP8(s, buff, len)
#else
#define BT_DRV_TRACE(n, fmt, ...) hal_trace_dummy(fmt, ##__VA_ARGS__)
#define BT_DRV_DUMP(s,buff,len) hal_dump_dummy(s, buff, len)
#define BT_DRV_DUMP(s, buff, len) hal_dump_dummy(s, buff, len)
#endif
#define HCI_HOST_NB_CMP_PKTS_CMD_OPCODE 0x0C35
#define HCI_NB_CMP_PKTS_EVT_CODE 0x13
#define HCI_HOST_NB_CMP_PKTS_CMD_OPCODE 0x0C35
#define HCI_NB_CMP_PKTS_EVT_CODE 0x13
#if defined(CHIP_BEST2300) || defined(__FPGA_BT_2300__)
#if defined(CHIP_BEST2300)
#define BT_EM_ADDR_BASE (0xD021114A)
#define BT_EM_SIZE (110)
#define BLE_EM_CS_SIZE (90)
#define BLE_EM_CS_SIZE (90)
#define EM_BT_PWRCNTL_ADDR (BT_EM_ADDR_BASE + 0x16)
#define EM_BT_BT_EXT1_ADDR (BT_EM_ADDR_BASE + 0x66)
#define EM_BT_BITOFF_ADDR (BT_EM_ADDR_BASE + 0x02)
#define EM_BT_CLKOFF0_ADDR (BT_EM_ADDR_BASE + 0x04)
#define EM_BT_CLKOFF1_ADDR (BT_EM_ADDR_BASE + 0x06)
#define EM_BT_WINCNTL_ADDR (BT_EM_ADDR_BASE + 0x1A)
#define EM_BT_RXBIT_ADDR (BT_EM_ADDR_BASE + 0x56)
#define EM_BT_BTADDR1_ADDR (BT_EM_ADDR_BASE + 0xC)
#define EM_BT_LINKCNTL_ADDR (BT_EM_ADDR_BASE + 0x8)
#define EM_BT_RXDESCCNT_ADDR (BT_EM_ADDR_BASE + 0x5A)
#define EM_BT_BITOFF_ADDR (BT_EM_ADDR_BASE + 0x02)
#define EM_BT_CLKOFF0_ADDR (BT_EM_ADDR_BASE + 0x04)
#define EM_BT_CLKOFF1_ADDR (BT_EM_ADDR_BASE + 0x06)
#define EM_BT_WINCNTL_ADDR (BT_EM_ADDR_BASE + 0x1A)
#define EM_BT_RXBIT_ADDR (BT_EM_ADDR_BASE + 0x56)
#define EM_BT_BTADDR1_ADDR (BT_EM_ADDR_BASE + 0xC)
#define EM_BT_LINKCNTL_ADDR (BT_EM_ADDR_BASE + 0x8)
#define EM_BT_RXDESCCNT_ADDR (BT_EM_ADDR_BASE + 0x5A)
#define EM_BT_AUDIOBUF_OFF 0xd021449c
#define EM_BT_RXACLBUFPTR_ADDR 0xd02115a0
#define EM_BT_AUDIOBUF_OFF 0xd021449c
#define EM_BT_RXACLBUFPTR_ADDR 0xd02115a0
#define REG_EM_BT_RXDESC_SIZE 14
#define LBRT_TX_PWR_FIX (3)
#define BT_CONTROLLER_CRASH_DUMP_ADDR_BASE (0xc0000050)
#define DEFAULT_XTAL_FCAP 0x8080
#define LBRT_TX_PWR_FIX (3)
#define BT_CONTROLLER_CRASH_DUMP_ADDR_BASE (0xc0000050)
#define DEFAULT_XTAL_FCAP 0x8080
#define BT_ERRORTYPESTAT_ADDR (0xd0220060)
#define MAX_NB_ACTIVE_ACL (3)
#define BT_ERRORTYPESTAT_ADDR (0xd0220060)
#define MAX_NB_ACTIVE_ACL (3)
#elif defined(CHIP_BEST2300P) || defined(CHIP_BEST2300A) || defined(CHIP_BEST1400) || defined(CHIP_BEST1402) || defined(__FPGA_BT_1400__) || defined(CHIP_BEST2001)
#elif defined(CHIP_BEST2300P) || defined(CHIP_BEST2300A) || \
defined(CHIP_BEST1400) || defined(CHIP_BEST1402) || defined(CHIP_BEST2001)
#define BT_EM_ADDR_BASE (0xD02111A2)
#define BT_EM_SIZE (110)
#define BLE_EM_CS_SIZE (90)
#define BLE_EM_CS_SIZE (90)
#define EM_BT_PWRCNTL_ADDR (BT_EM_ADDR_BASE + 0x16)
#define EM_BT_BT_EXT1_ADDR (BT_EM_ADDR_BASE + 0x66)
#define EM_BT_BT_EXT2_ADDR (BT_EM_ADDR_BASE + 0x68)
#define EM_BT_BITOFF_ADDR (BT_EM_ADDR_BASE + 0x02)
#define EM_BT_CLKOFF0_ADDR (BT_EM_ADDR_BASE + 0x04)
#define EM_BT_CLKOFF1_ADDR (BT_EM_ADDR_BASE + 0x06)
#define EM_BT_WINCNTL_ADDR (BT_EM_ADDR_BASE + 0x1A)
#define EM_BT_RXBIT_ADDR (BT_EM_ADDR_BASE + 0x56)
#define EM_BT_BTADDR1_ADDR (BT_EM_ADDR_BASE + 0xC)
#define EM_BT_LINKCNTL_ADDR (BT_EM_ADDR_BASE + 0x8)
#define EM_BT_BITOFF_ADDR (BT_EM_ADDR_BASE + 0x02)
#define EM_BT_CLKOFF0_ADDR (BT_EM_ADDR_BASE + 0x04)
#define EM_BT_CLKOFF1_ADDR (BT_EM_ADDR_BASE + 0x06)
#define EM_BT_WINCNTL_ADDR (BT_EM_ADDR_BASE + 0x1A)
#define EM_BT_RXBIT_ADDR (BT_EM_ADDR_BASE + 0x56)
#define EM_BT_BTADDR1_ADDR (BT_EM_ADDR_BASE + 0xC)
#define EM_BT_LINKCNTL_ADDR (BT_EM_ADDR_BASE + 0x8)
#define BLE_CRCINIT1_ADDR (0xd02100c2)
#define EM_BT_RXDESCCNT_ADDR (BT_EM_ADDR_BASE + 0x5A)
#define EM_BT_RXDESCCNT_ADDR (BT_EM_ADDR_BASE + 0x5A)
#define BLE_MAXEVTIME_ADDR (0xd02100d0)
#define BLE_MAXEVTIME_ADDR (0xd02100d0)
#define EM_BT_AUDIOBUF_OFF 0xd02144fc
#define EM_BT_RXACLBUFPTR_ADDR 0xd02115f8
#define EM_BT_AUDIOBUF_OFF 0xd02144fc
#define EM_BT_RXACLBUFPTR_ADDR 0xd02115f8
#define REG_EM_BT_RXDESC_SIZE 16
#define LBRT_TX_PWR_FIX (3)
#define BT_CONTROLLER_CRASH_DUMP_ADDR_BASE (0xc0000050)
#define BT_ERRORTYPESTAT_ADDR (0xd0220060)
#define MAX_NB_ACTIVE_ACL (3)
#define LBRT_TX_PWR_FIX (3)
#define BT_CONTROLLER_CRASH_DUMP_ADDR_BASE (0xc0000050)
#define BT_ERRORTYPESTAT_ADDR (0xd0220060)
#define MAX_NB_ACTIVE_ACL (3)
#ifdef CHIP_BEST2300A
#define DEFAULT_XTAL_FCAP 0x80ad //8pf crstal No cap by luobin
#define DEFAULT_XTAL_FCAP 0x80ad // 8pf crstal No cap by luobin
#else
#define DEFAULT_XTAL_FCAP 0x8080
#define DEFAULT_XTAL_FCAP 0x8080
#endif
#elif defined(__FPGA_BT_1500__)
#define BT_EM_ADDR_BASE (0xD0215000)
#define BT_EM_SIZE (104)
#define BLE_EM_CS_SIZE (112)
#define EM_BT_PWRCNTL_ADDR (BT_EM_ADDR_BASE + 0x14)
#define EM_BT_BT_EXT1_ADDR (BT_EM_ADDR_BASE + 0x60)
#define EM_BT_BITOFF_ADDR //(BT_EM_ADDR_BASE + 0x02)
#define EM_BT_CLKOFF0_ADDR (BT_EM_ADDR_BASE + 0x02)
#define EM_BT_CLKOFF1_ADDR (BT_EM_ADDR_BASE + 0x04)
#define EM_BT_WINCNTL_ADDR (BT_EM_ADDR_BASE + 0x18)
#define EM_BT_RXCLKN0_ADDR (BT_EM_ADDR_BASE + 0x52)
#define EM_BT_RXCLKN1_ADDR (BT_EM_ADDR_BASE + 0x54)
#define EM_BT_RXBIT_ADDR (BT_EM_ADDR_BASE + 0x56)
#define EM_BT_BTADDR1_ADDR (BT_EM_ADDR_BASE + 0x8)
#define EM_BT_LINKCNTL_ADDR (BT_EM_ADDR_BASE + 0x6)
#define EM_BT_RXDESCCNT_ADDR (BT_EM_ADDR_BASE + 0x5A)
#define EM_BT_AUDIOBUF_OFF 0xd02144fc
#define EM_BT_RXACLBUFPTR_ADDR 0xd02115f8
#define REG_EM_BT_RXDESC_SIZE 16
#define LBRT_TX_PWR_FIX (3)
#define BT_CONTROLLER_CRASH_DUMP_ADDR_BASE (0xc0000050)
#define BT_ERRORTYPESTAT_ADDR (0xd0220460)
#define DEFAULT_XTAL_FCAP 0x8080
#define MAX_NB_ACTIVE_ACL (4)
#else
#define BT_EM_ADDR_BASE (0xd0210190)
#define BT_EM_SIZE (96)
#define BT_CONTROLLER_CRASH_DUMP_ADDR_BASE (0xc00064cc)
#define BT_CONTROLLER_CRASH_DUMP_ADDR_BASE (0xc00064cc)
#endif
#ifndef __FPGA_BT_1500__
//#define FPGA_1303
#endif
// bt max slot clock
#define MAX_SLOT_CLOCK ((1L << 27) - 1)
// A slot is 625 us
#define SLOT_SIZE 625
#define XTAL_OFFSET 50
//bt max slot clock
#define MAX_SLOT_CLOCK ((1L<<27) - 1)
// A slot is 625 us
#define SLOT_SIZE 625
#define XTAL_OFFSET 50
//#define __PASS_CI_TEST_SETTING__
#define BT_LOW_POWER_MODE 1
#define BT_HIGH_PERFORMANCE_MODE 2
//#define __ENABLE_LINK_POWER_CONTROL__
// #define __PASS_CI_TEST_SETTING__
#define BT_LOW_POWER_MODE 1
#define BT_HIGH_PERFORMANCE_MODE 2
// #define __ENABLE_LINK_POWER_CONTROL__
#define BT_RFMODE BT_LOW_POWER_MODE
//#define BT_RFMODE BT_HIGH_PERFORMANCE_MODE
//#define BT_50_FUNCTION
// #define BT_RFMODE BT_HIGH_PERFORMANCE_MODE
// #define BT_50_FUNCTION
#define BT_POWERON 1
#define BT_POWEROFF 0
#define BT_POWERON 1
#define BT_POWEROFF 0
/// 8 bit access types
#define _8_Bit 8
#define _8_Bit 8
/// 16 bit access types
#define _16_Bit 16
#define _16_Bit 16
/// 32 bit access types
#define _32_Bit 32
#define _32_Bit 32
#define BTDRV_PATCH_WRITING 0x0
#define BTDRV_PATCH_DONE 0x1
#define BTDRV_PATCH_WRITING 0x0
#define BTDRV_PATCH_DONE 0x1
#define BTDRV_CFG_WRITING 0x0
#define BTDRV_CFG_DONE 0x1
#define BTDRV_CFG_WRITING 0x0
#define BTDRV_CFG_DONE 0x1
#define HCI_DBG_RD_MEM_CMD_OPCODE 0xFC01
#define HCI_DBG_WR_MEM_CMD_OPCODE 0xFC02
#define HCI_DBG_DEL_PAR_CMD_OPCODE 0xFC03
#define HCI_DBG_FLASH_ID_CMD_OPCODE 0xFC05
#define HCI_DBG_FLASH_ER_CMD_OPCODE 0xFC06
#define HCI_DBG_FLASH_WR_CMD_OPCODE 0xFC07
#define HCI_DBG_FLASH_RD_CMD_OPCODE 0xFC08
#define HCI_DBG_RD_PAR_CMD_OPCODE 0xFC09
#define HCI_DBG_WR_PAR_CMD_OPCODE 0xFC0A
#define HCI_DBG_WLAN_COEX_CMD_OPCODE 0xFC0B
#define HCI_DBG_ENTER_TEST_MODE_CMD_OPCODE 0xFC0C
#define HCI_DBG_WLAN_COEXTST_SCEN_CMD_OPCODE 0xFC0D
#define HCI_DBG_SEND_LMP_CMD_OPCODE 0xFC0E
#define HCI_DBG_WR_SYNC_DATA_CFG_CMD_OPCODE 0xFC0F
#define HCI_DBG_RD_KE_STATS_CMD_OPCODE 0xFC10
#define HCI_DBG_PLF_RESET_CMD_OPCODE 0xFC11
#define HCI_DBG_RD_MEM_INFO_CMD_OPCODE 0xFC12
#define HCI_DBG_EMUL_TESTER_CMD_OPCODE 0xFC2D
#define HCI_DBG_SCATT_IMPROV_CMD_OPCODE 0xFC2E
#define HCI_DBG_RF_REG_RD_CMD_OPCODE 0xFC39
#define HCI_DBG_RF_REG_WR_CMD_OPCODE 0xFC3A
#define HCI_DBG_HW_REG_RD_CMD_OPCODE 0xFC30
#define HCI_DBG_HW_REG_WR_CMD_OPCODE 0xFC31
#define HCI_DBG_SET_BD_ADDR_CMD_OPCODE 0xFC32
#define HCI_DBG_SET_TYPE_PUB_CMD_OPCODE 0xFC33
#define HCI_DBG_SET_TYPE_RAND_CMD_OPCODE 0xFC34
#define HCI_DBG_SET_CRC_CMD_OPCODE 0xFC35
#define HCI_DBG_LLCP_DISCARD_CMD_OPCODE 0xFC36
#define HCI_DBG_RESET_RX_CNT_CMD_OPCODE 0xFC37
#define HCI_DBG_RESET_TX_CNT_CMD_OPCODE 0xFC38
#define HCI_DBG_SET_TX_PW_CMD_OPCODE 0xFC3B
#define HCI_DBG_SET_SYNCWORD_CMD_OPCODE 0xFC3C
#define HCI_DBG_RD_MEM_CMD_OPCODE 0xFC01
#define HCI_DBG_WR_MEM_CMD_OPCODE 0xFC02
#define HCI_DBG_DEL_PAR_CMD_OPCODE 0xFC03
#define HCI_DBG_FLASH_ID_CMD_OPCODE 0xFC05
#define HCI_DBG_FLASH_ER_CMD_OPCODE 0xFC06
#define HCI_DBG_FLASH_WR_CMD_OPCODE 0xFC07
#define HCI_DBG_FLASH_RD_CMD_OPCODE 0xFC08
#define HCI_DBG_RD_PAR_CMD_OPCODE 0xFC09
#define HCI_DBG_WR_PAR_CMD_OPCODE 0xFC0A
#define HCI_DBG_WLAN_COEX_CMD_OPCODE 0xFC0B
#define HCI_DBG_ENTER_TEST_MODE_CMD_OPCODE 0xFC0C
#define HCI_DBG_WLAN_COEXTST_SCEN_CMD_OPCODE 0xFC0D
#define HCI_DBG_SEND_LMP_CMD_OPCODE 0xFC0E
#define HCI_DBG_WR_SYNC_DATA_CFG_CMD_OPCODE 0xFC0F
#define HCI_DBG_RD_KE_STATS_CMD_OPCODE 0xFC10
#define HCI_DBG_PLF_RESET_CMD_OPCODE 0xFC11
#define HCI_DBG_RD_MEM_INFO_CMD_OPCODE 0xFC12
#define HCI_DBG_EMUL_TESTER_CMD_OPCODE 0xFC2D
#define HCI_DBG_SCATT_IMPROV_CMD_OPCODE 0xFC2E
#define HCI_DBG_RF_REG_RD_CMD_OPCODE 0xFC39
#define HCI_DBG_RF_REG_WR_CMD_OPCODE 0xFC3A
#define HCI_DBG_HW_REG_RD_CMD_OPCODE 0xFC30
#define HCI_DBG_HW_REG_WR_CMD_OPCODE 0xFC31
#define HCI_DBG_SET_BD_ADDR_CMD_OPCODE 0xFC32
#define HCI_DBG_SET_TYPE_PUB_CMD_OPCODE 0xFC33
#define HCI_DBG_SET_TYPE_RAND_CMD_OPCODE 0xFC34
#define HCI_DBG_SET_CRC_CMD_OPCODE 0xFC35
#define HCI_DBG_LLCP_DISCARD_CMD_OPCODE 0xFC36
#define HCI_DBG_RESET_RX_CNT_CMD_OPCODE 0xFC37
#define HCI_DBG_RESET_TX_CNT_CMD_OPCODE 0xFC38
#define HCI_DBG_SET_TX_PW_CMD_OPCODE 0xFC3B
#define HCI_DBG_SET_SYNCWORD_CMD_OPCODE 0xFC3C
// encrytion min and max key size
#define HCI_DBG_SET_ENCRYPTION_KEY_SIZE_CMD_OPCODE 0xFC41
// preferred key type default :combine key
#define HCI_DBG_SET_PREFERRED_KEY_TYPE_CMD_OPCODE 0xFC42
// creat unit key
#define HCI_DBG_CREAT_UNIT_KEY_CMD_OPCODE 0xFC43
// set clk drift and jitter
#define HCI_DBG_SET_LPCLK_DRIFT_JITTER_CMD_OPCODE 0xFC44
//encrytion min and max key size
#define HCI_DBG_SET_ENCRYPTION_KEY_SIZE_CMD_OPCODE 0xFC41
//preferred key type default :combine key
#define HCI_DBG_SET_PREFERRED_KEY_TYPE_CMD_OPCODE 0xFC42
//creat unit key
#define HCI_DBG_CREAT_UNIT_KEY_CMD_OPCODE 0xFC43
//set clk drift and jitter
#define HCI_DBG_SET_LPCLK_DRIFT_JITTER_CMD_OPCODE 0xFC44
// change uart buadrate
#define HCI_DBG_CHANGE_UART_BAUDRATE_CMD_OPCODE 0xFC46
//change uart buadrate
#define HCI_DBG_CHANGE_UART_BAUDRATE_CMD_OPCODE 0xFC46
// set sleep enable and external wakeup enable
#define HCI_DBG_SET_SLEEP_EXWAKEUP_EN_CMD_OPCODE 0xFC47
//set sleep enable and external wakeup enable
#define HCI_DBG_SET_SLEEP_EXWAKEUP_EN_CMD_OPCODE 0xFC47
// set private key
#define HCI_DBG_SET_SP_PRIVATE_KEY_CMD_OPCODE 0xFC48
//set private key
#define HCI_DBG_SET_SP_PRIVATE_KEY_CMD_OPCODE 0xFC48
// set public key
#define HCI_DBG_SET_SP_PUBLIC_KEY_CMD_OPCODE 0xFC49
//set public key
#define HCI_DBG_SET_SP_PUBLIC_KEY_CMD_OPCODE 0xFC49
// set errdata adopted
#define HCI_DBG_SET_ERRDATA_ADOPTED_CMD_OPCODE 0xFC4A
//set errdata adopted
#define HCI_DBG_SET_ERRDATA_ADOPTED_CMD_OPCODE 0xFC4A
// set basic threshold
#define HCI_DBG_SET_BASIC_THRESHOLD_CMD_OPCODE 0xFC4B
//set basic threshold
#define HCI_DBG_SET_BASIC_THRESHOLD_CMD_OPCODE 0xFC4B
// set edr threshold
#define HCI_DBG_SET_EDR_THRESHOLD_CMD_OPCODE 0xFC4C
//set edr threshold
#define HCI_DBG_SET_EDR_THRESHOLD_CMD_OPCODE 0xFC4C
// set basic algorithm
#define HCI_DBG_SET_BASIC_ALGORITHM_CMD_OPCODE 0xFC4D
//set basic algorithm
#define HCI_DBG_SET_BASIC_ALGORITHM_CMD_OPCODE 0xFC4D
// set edr alorithm
#define HCI_DBG_SET_EDR_ALGORITHM_CMD_OPCODE 0xFC4E
//set edr alorithm
#define HCI_DBG_SET_EDR_ALGORITHM_CMD_OPCODE 0xFC4E
// set basic packet lut
#define HCI_DBG_SET_BASIC_PKT_LUT_CMD_OPCODE 0xFC4F
//set basic packet lut
#define HCI_DBG_SET_BASIC_PKT_LUT_CMD_OPCODE 0xFC4F
// set edr packet lut
#define HCI_DBG_SET_EDR_PKT_LUT_CMD_OPCODE 0xFC50
//set edr packet lut
#define HCI_DBG_SET_EDR_PKT_LUT_CMD_OPCODE 0xFC50
// set diag_bt_hw
#define HCI_DBG_SET_DIAG_BT_HW_CMD_OPCODE 0xFC54
// set diag ble hw
#define HCI_DBG_SET_DIAG_BLE_HW_CMD_OPCODE 0xFC55
// set diag sw
#define HCI_DBG_SET_DIAG_SW_CMD_OPCODE 0xFC56
//set diag_bt_hw
#define HCI_DBG_SET_DIAG_BT_HW_CMD_OPCODE 0xFC54
//set diag ble hw
#define HCI_DBG_SET_DIAG_BLE_HW_CMD_OPCODE 0xFC55
//set diag sw
#define HCI_DBG_SET_DIAG_SW_CMD_OPCODE 0xFC56
// set ble channel assessment parameter
#define HCI_DBG_SET_BLE_CA_PARA_CMD_OPCODE 0xFC57
//set ble channel assessment parameter
#define HCI_DBG_SET_BLE_CA_PARA_CMD_OPCODE 0xFC57
// set ble rf timing
//set ble rf timing
// set ble rf timig
//set ble rf timig
// set ble rl size
#define HCI_DBG_SET_RL_SIZE_CMD_OPCODE 0xFC5D
//set ble rl size
#define HCI_DBG_SET_RL_SIZE_CMD_OPCODE 0xFC5D
/// set hostwake
#define HCI_DBG_SET_HOSTWAKE_CMD_OPCODE 0xFC5E
// reserved for VCO test
#define HCI_DBG_BT_VCO_TEST_CMD_OPCODE 0xFCAA
///set hostwake
#define HCI_DBG_SET_HOSTWAKE_CMD_OPCODE 0xFC5E
//reserved for VCO test
#define HCI_DBG_BT_VCO_TEST_CMD_OPCODE 0xFCAA
#if defined(CHIP_BEST2300) || defined(CHIP_BEST2300P) || \
defined(CHIP_BEST2300A) || defined(CHIP_BEST2001) || \
defined(CHIP_BEST1400) || defined(CHIP_BEST1402)
#if defined(CHIP_BEST2300) || defined(CHIP_BEST2300P) || \
defined(CHIP_BEST2300A) || defined(CHIP_BEST2001) || \
defined(CHIP_BEST1400) || defined(CHIP_BEST1402) || \
defined(__FPGA_BT_2300__) ||defined(__FPGA_BT_1400__) || \
defined(__FPGA_BT_1500__)
/// set dle dft value
#define HCI_DBG_WR_DLE_DFT_VALUE_CMD_OPCODE 0xFC41
///set dle dft value
#define HCI_DBG_WR_DLE_DFT_VALUE_CMD_OPCODE 0xFC41
// set exernal wake up time oscillater wakeup time and radio wakeup time
#define HCI_DBG_SET_WAKEUP_TIME_CMD_OPCODE 0xFC71
//set exernal wake up time oscillater wakeup time and radio wakeup time
#define HCI_DBG_SET_WAKEUP_TIME_CMD_OPCODE 0xFC71
#define HCI_DBG_SET_SLEEP_SETTING_CMD_OPCODE 0xFC77
#define HCI_DBG_SET_SLEEP_SETTING_CMD_OPCODE 0xFC77
// bt address not ble address
#define HCI_DBG_SET_BT_ADDR_CMD_OPCODE 0xFC72
// set pcm setting
#define HCI_DBG_SET_PCM_SETTING_CMD_OPCODE 0xFC74
//bt address not ble address
#define HCI_DBG_SET_BT_ADDR_CMD_OPCODE 0xFC72
//set pcm setting
#define HCI_DBG_SET_PCM_SETTING_CMD_OPCODE 0xFC74
#define HCI_DBG_SET_RSSI_THRHLD_CMD_OPCODE 0xFC76
#define HCI_DBG_SET_RSSI_THRHLD_CMD_OPCODE 0xFC76
// set sync buff size
#define HCI_DBG_SET_SYNC_BUF_SIZE_CMD_OPCODE 0xFC7F
// set afh algorithm
#define HCI_DBG_SET_AFH_ALGORITHM_CMD_OPCODE 0xFC80
// set local feature
#define HCI_DBG_SET_LOCAL_FEATURE_CMD_OPCODE 0xFC81
#define HCI_DBG_SET_BT_RF_TIMING_CMD_OPCODE 0xFC83
//set sync buff size
#define HCI_DBG_SET_SYNC_BUF_SIZE_CMD_OPCODE 0xFC7F
//set afh algorithm
#define HCI_DBG_SET_AFH_ALGORITHM_CMD_OPCODE 0xFC80
//set local feature
#define HCI_DBG_SET_LOCAL_FEATURE_CMD_OPCODE 0xFC81
// set local extend feature
#define HCI_DBG_SET_LOCAL_EX_FEATURE_CMD_OPCODE 0xFC82
#define HCI_DBG_SET_BT_RF_TIMING_CMD_OPCODE 0xFC83
#define HCI_DBG_SET_2300_BT_RF_TIMING_CMD_OPCODE 0xFC83
//set local extend feature
#define HCI_DBG_SET_LOCAL_EX_FEATURE_CMD_OPCODE 0xFC82
#define HCI_DBG_SET_BLE_RF_TIMING_CMD_OPCODE 0xfc84
#define HCI_DBG_SET_2300_BT_RF_TIMING_CMD_OPCODE 0xFC83
#define HCI_DBG_SET_BLE_RF_TIMING_CMD_OPCODE 0xfc84
//bt setting interface
#define HCI_DBG_SET_BT_SETTING_CMD_OPCODE 0xFC86
// bt setting interface
#define HCI_DBG_SET_BT_SETTING_CMD_OPCODE 0xFC86
// xiao add for nonsignaling test mode
#define HCI_DBG_NONSIG_TESTER_SETUP_CMD_OPCODE 0xFC87
#define HCI_DBG_NONSIG_TESTER_SETUP_CMD_OPCODE 0xFC87
/* xiao add for custom set param*/
#define HCI_DBG_SET_CUSTOM_PARAM_CMD_OPCODE 0xFC88
#define HCI_DBG_SET_CUSTOM_PARAM_CMD_OPCODE 0xFC88
#define HCI_DBG_SET_SCO_SWITCH_CMD_OPCODE 0xFC89
#define HCI_DBG_SET_SCO_SWITCH_CMD_OPCODE 0xFC89
#define HCI_DBG_SET_SNIFFER_ENV_CMD_OPCODE 0xFC8E
//set sco path
#define HCI_DBG_SET_SYNC_CONFIG_CMD_OPCODE 0xFC8F
#define HCI_DBG_SET_SNIFFER_ENV_CMD_OPCODE 0xFC8E
// set sco path
#define HCI_DBG_SET_SYNC_CONFIG_CMD_OPCODE 0xFC8F
#define HCI_DBG_START_TWS_EXCHANGE_CMD_OPCODE 0xFC91
#define HCI_DBG_START_TWS_EXCHANGE_CMD_OPCODE 0xFC91
#define HCI_DBG_BTADDR_EXCHANGE_CMD_OPCODE 0xFC92
#define HCI_DBG_BTADDR_EXCHANGE_CMD_OPCODE 0xFC92
#define HCI_DBG_SEND_DATA_TO_PEER_DEV_CMD_OPCODE 0xFC93
#define HCI_DBG_SEND_DATA_TO_PEER_DEV_CMD_OPCODE 0xFC93
#define HCI_DBG_SCO_TX_SILENCE_CMD_OPCODE 0xFC94
#define HCI_DBG_SCO_TX_SILENCE_CMD_OPCODE 0xFC94
#define HCI_DBG_SNIFFER_CMD_OPCODE 0xFC95
#define HCI_DBG_SNIFFER_CMD_OPCODE 0xFC95
#define HCI_DBG_CSB_UPDATE_LINK_PARAM_CMD_OPCODE 0xFC96
#define HCI_DBG_CSB_UPDATE_LINK_PARAM_CMD_OPCODE 0xFC96
#define HCI_DBG_SET_LINK_LBRT_CMD_OPCODE 0xFC97
#define HCI_DBG_SET_LINK_LBRT_CMD_OPCODE 0xFC97
#define HCI_DBG_SET_CON_SLV_BCST_DATA_CMD_OPCODE 0xFC98
#define HCI_DBG_SET_ROLE_SWITCH_INSTANT_CMD_OPCODE 0xFC99
#define HCI_DBG_LOW_LAYER_METRICS_CMD_OPCODE 0xFC9B
#define HCI_DBG_LMP_MESSAGE_RECORD_CMD_OPCODE 0xFC9C
#define HCI_DBG_SET_CON_SLV_BCST_DATA_CMD_OPCODE 0xFC98
#define HCI_DBG_SET_ROLE_SWITCH_INSTANT_CMD_OPCODE 0xFC99
#define HCI_DBG_LOW_LAYER_METRICS_CMD_OPCODE 0xFC9B
#define HCI_DBG_LMP_MESSAGE_RECORD_CMD_OPCODE 0xFC9C
#define HCI_DBG_SET_LOCAL_FEATURE_50_CMD_OPCODE 0xFC72
#define HCI_DBG_SET_SLEEP_SETTING_50_CMD_OPCODE 0xFC70
#define HCI_DBG_SET_BT_SETTING_50_CMD_OPCODE 0xFC71
#define HCI_DBG_SET_LOCAL_FEATURE_50_CMD_OPCODE 0xFC72
#define HCI_DBG_SET_SLEEP_SETTING_50_CMD_OPCODE 0xFC70
#define HCI_DBG_SET_BT_SETTING_50_CMD_OPCODE 0xFC71
#define HCI_DBG_SET_CUSTOM_PARAM_50_CMD_OPCODE 0xFC73
#define HCI_DBG_SET_BT_SETTING_EXT1_CMD_OPCODE 0xFCAE
#define HCI_DBG_SET_BT_TWS_LINK_CMD_OPCODE 0xFCAF
#define HCI_DBG_SET_AFH_FOLLOW_CMD_OPCODE 0xFCB0
#define HCI_DBG_SET_RF_RX_GAIN_THS_TBL_CMD_OPCODE 0xFCB1
#define HCI_DBG_SET_RF_RX_GAIN_FIXED_CMD_OPCODE 0xFCB2
#define HCI_DBG_SET_CUSTOM_PARAM_50_CMD_OPCODE 0xFC73
#define HCI_DBG_SET_BT_SETTING_EXT1_CMD_OPCODE 0xFCAE
#define HCI_DBG_SET_BT_TWS_LINK_CMD_OPCODE 0xFCAF
#define HCI_DBG_SET_AFH_FOLLOW_CMD_OPCODE 0xFCB0
#define HCI_DBG_SET_RF_RX_GAIN_THS_TBL_CMD_OPCODE 0xFCB1
#define HCI_DBG_SET_RF_RX_GAIN_FIXED_CMD_OPCODE 0xFCB2
#define HCI_DBG_SET_BT_SETTING_EXT2_CMD_OPCODE 0xFCB3
#define HCI_DBG_SET_IBRT_TEST_MODE_CMD_OPCODE 0xFCB4
#define HCI_DBG_SET_BT_LOCAL_CLK_CMD_OPCODE 0xFCB5
#define HCI_DBG_SET_FUNC_PATCH_CMD_OPCODE 0xFCB8
#define HCI_DBG_SET_TXPWR_MODE_CMD_OPCODE 0xFCB9
#define HCI_DBG_SET_SW_RSSI_CMD_OPCODE 0xFCBA
#define HCI_DBG_SET_ECC_DATA_TEST_CMD_OPCODE 0xFCBB
#define HCI_DBG_SET_IBRT_DATA_TEST_CMD_OPCODE 0xFCBC
#define HCI_DBG_SET_NWINSZ_RXGRN_TO_CMD_OPCODE 0xFCBD
#define HCI_DBG_ENABLE_SOFTBIT_CMD_OPCODE 0xFCBE
#define HCI_DBG_SET_BT_SETTING_EXT2_CMD_OPCODE 0xFCB3
#define HCI_DBG_SET_IBRT_TEST_MODE_CMD_OPCODE 0xFCB4
#define HCI_DBG_SET_BT_LOCAL_CLK_CMD_OPCODE 0xFCB5
#define HCI_DBG_SET_FUNC_PATCH_CMD_OPCODE 0xFCB8
#define HCI_DBG_SET_TXPWR_MODE_CMD_OPCODE 0xFCB9
#define HCI_DBG_SET_SW_RSSI_CMD_OPCODE 0xFCBA
#define HCI_DBG_SET_ECC_DATA_TEST_CMD_OPCODE 0xFCBB
#define HCI_DBG_SET_IBRT_DATA_TEST_CMD_OPCODE 0xFCBC
#define HCI_DBG_SET_NWINSZ_RXGRN_TO_CMD_OPCODE 0xFCBD
#define HCI_DBG_ENABLE_SOFTBIT_CMD_OPCODE 0xFCBE
#else
//bt address not ble address
#define HCI_DBG_SET_BT_ADDR_CMD_OPCODE 0xFC40
//set exernal wake up time oscillater wakeup time and radio wakeup time
#define HCI_DBG_SET_WAKEUP_TIME_CMD_OPCODE 0xFC45
//set sco path
#define HCI_DBG_SET_SYNC_CONFIG_CMD_OPCODE 0xFC51
//set pcm setting
#define HCI_DBG_SET_PCM_SETTING_CMD_OPCODE 0xFC52
//set sync buff size
#define HCI_DBG_SET_SYNC_BUF_SIZE_CMD_OPCODE 0xFC53
//set local feature
#define HCI_DBG_SET_LOCAL_FEATURE_CMD_OPCODE 0xFC59
//bt setting interface
#define HCI_DBG_SET_BT_SETTING_CMD_OPCODE 0xFC5F
//set afh algorithm
#define HCI_DBG_SET_AFH_ALGORITHM_CMD_OPCODE 0xFC58
//set local extend feature
#define HCI_DBG_SET_LOCAL_EX_FEATURE_CMD_OPCODE 0xFC5A
// bt address not ble address
#define HCI_DBG_SET_BT_ADDR_CMD_OPCODE 0xFC40
// set exernal wake up time oscillater wakeup time and radio wakeup time
#define HCI_DBG_SET_WAKEUP_TIME_CMD_OPCODE 0xFC45
// set sco path
#define HCI_DBG_SET_SYNC_CONFIG_CMD_OPCODE 0xFC51
// set pcm setting
#define HCI_DBG_SET_PCM_SETTING_CMD_OPCODE 0xFC52
// set sync buff size
#define HCI_DBG_SET_SYNC_BUF_SIZE_CMD_OPCODE 0xFC53
// set local feature
#define HCI_DBG_SET_LOCAL_FEATURE_CMD_OPCODE 0xFC59
// bt setting interface
#define HCI_DBG_SET_BT_SETTING_CMD_OPCODE 0xFC5F
// set afh algorithm
#define HCI_DBG_SET_AFH_ALGORITHM_CMD_OPCODE 0xFC58
// set local extend feature
#define HCI_DBG_SET_LOCAL_EX_FEATURE_CMD_OPCODE 0xFC5A
#define HCI_DBG_SET_BT_RF_TIMING_CMD_OPCODE 0xFC5B
#define HCI_DBG_SET_BLE_RF_TIMING_CMD_OPCODE 0xFC5C
#define HCI_DBG_SET_BT_RF_TIMING_CMD_OPCODE 0xFC5B
#define HCI_DBG_SET_BLE_RF_TIMING_CMD_OPCODE 0xFC5C
// xiao add for nonsignaling test mode
#define HCI_DBG_NONSIG_TESTER_SETUP_CMD_OPCODE 0xFC60
#define HCI_DBG_NONSIG_TESTER_SETUP_CMD_OPCODE 0xFC60
/* xiao add for custom set param*/
#define HCI_DBG_SET_CUSTOM_PARAM_CMD_OPCODE 0xFC61
#define HCI_DBG_SET_CUSTOM_PARAM_CMD_OPCODE 0xFC61
#define HCI_DBG_SET_SCO_SWITCH_CMD_OPCODE 0xFC62
#define HCI_DBG_SET_SCO_SWITCH_CMD_OPCODE 0xFC62
#define HCI_DBG_SET_SNIFFER_ENV_CMD_OPCODE 0xFC67
#define HCI_DBG_SET_SNIFFER_ENV_CMD_OPCODE 0xFC67
#define HCI_DBG_START_TWS_EXCHANGE_CMD_OPCODE 0xFC69
#define HCI_DBG_START_TWS_EXCHANGE_CMD_OPCODE 0xFC69
#define HCI_DBG_BTADDR_EXCHANGE_CMD_OPCODE 0xFC6A
#define HCI_DBG_BTADDR_EXCHANGE_CMD_OPCODE 0xFC6A
#define HCI_DBG_SEND_DATA_TO_PEER_DEV_CMD_OPCODE 0xFC6B
#define HCI_DBG_SEND_DATA_TO_PEER_DEV_CMD_OPCODE 0xFC6B
#define HCI_DBG_SCO_TX_SILENCE_CMD_OPCODE 0xFC6C
#define HCI_DBG_SCO_TX_SILENCE_CMD_OPCODE 0xFC6C
#define HCI_DBG_SNIFFER_CMD_OPCODE 0xFC6D
#define HCI_DBG_SNIFFER_CMD_OPCODE 0xFC6D
#define HCI_DBG_BT_VCO_TEST_CMD_OPCODE 0xFCAA
#define HCI_DBG_BT_VCO_TEST_CMD_OPCODE 0xFCAA
// Only new controller IP has this funciton,it is a error opcode
#define HCI_DBG_SET_ROLE_SWITCH_INSTANT_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_LINK_LBRT_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_SETTING_EXT1_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_TWS_LINK_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_AFH_FOLLOW_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_RF_RX_GAIN_THS_TBL_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_RF_RX_GAIN_FIXED_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_SETTING_EXT2_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_IBRT_TEST_MODE_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_LOCAL_CLK_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_FUNC_PATCH_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_TXPWR_MODE_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_SW_RSSI_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_ECC_DATA_TEST_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_IBRT_DATA_TEST_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_NWINSZ_RXGRN_TO_CMD_OPCODE 0xFCFF
#define HCI_DBG_ENABLE_SOFTBIT_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_ROLE_SWITCH_INSTANT_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_LINK_LBRT_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_SETTING_EXT1_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_TWS_LINK_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_AFH_FOLLOW_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_RF_RX_GAIN_THS_TBL_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_RF_RX_GAIN_FIXED_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_SETTING_EXT2_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_IBRT_TEST_MODE_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_BT_LOCAL_CLK_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_FUNC_PATCH_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_TXPWR_MODE_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_SW_RSSI_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_ECC_DATA_TEST_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_IBRT_DATA_TEST_CMD_OPCODE 0xFCFF
#define HCI_DBG_SET_NWINSZ_RXGRN_TO_CMD_OPCODE 0xFCFF
#define HCI_DBG_ENABLE_SOFTBIT_CMD_OPCODE 0xFCFF
#endif // 2300, 2300p, 1400,1402,1501
@ -479,4 +453,3 @@ extern void btdrv_hciopen(void);
#endif
#endif

9
platform/drivers/bt/bt_drv_common.c
View File

@ -33,9 +33,7 @@
((uint32_t)(((clock_a) + (clock_b)) & MAX_SLOT_CLOCK))
struct bt_cb_tag bt_drv_func_cb = {NULL};
struct bt_cb_tag *bt_drv_get_func_cb_ptr(void) {
return &bt_drv_func_cb;
}
struct bt_cb_tag *bt_drv_get_func_cb_ptr(void) { return &bt_drv_func_cb; }
/// only used for bt chip write patch data for speed up
void btdrv_memory_copy(uint32_t *dest, const uint32_t *src, uint16_t length) {
@ -326,8 +324,6 @@ bool bt_drv_is_enhanced_ibrt_rom(void) {
ret = true;
#elif CHIP_BEST2300A
ret = true;
#elif FPGA
ret = true;
#elif CHIP_BEST2300
ret = true;
#endif
@ -393,9 +389,6 @@ bool bt_drv_is_bes_fa_mode_en(void) {
bool bt_drv_is_support_multipoint_ibrt(void) {
bool ret = false;
#ifdef __FPGA_BT_1500__
ret = true;
#endif
return ret;
}

4
platform/hal/hal_chipid.c
View File

@ -27,11 +27,7 @@ void BOOT_TEXT_FLASH_LOC hal_chipid_init(void) {
}
enum HAL_CHIP_METAL_ID_T BOOT_TEXT_SRAM_LOC hal_get_chip_metal_id(void) {
#ifdef FPGA
return HAL_CHIP_METAL_ID_15;
#else
return metal_id;
#endif
}
enum HAL_BT_CHIP_SERIES_T hal_get_bt_chip_series(void) {

120
platform/hal/hal_cmu.h
View File

@ -20,128 +20,128 @@
extern "C" {
#endif
#include "stdint.h"
#include "plat_addr_map.h"
#include "stdint.h"
#include CHIP_SPECIFIC_HDR(hal_cmu)
#ifndef HAL_CMU_DEFAULT_CRYSTAL_FREQ
#define HAL_CMU_DEFAULT_CRYSTAL_FREQ 26000000
#define HAL_CMU_DEFAULT_CRYSTAL_FREQ 26000000
#endif
#define LPU_TIMER_US(us) (((us) * 32 + 1000 - 1) / 1000)
#define LPU_TIMER_US(us) (((us)*32 + 1000 - 1) / 1000)
enum HAL_CMU_CLK_STATUS_T {
HAL_CMU_CLK_DISABLED,
HAL_CMU_CLK_ENABLED,
HAL_CMU_CLK_DISABLED,
HAL_CMU_CLK_ENABLED,
};
enum HAL_CMU_CLK_MODE_T {
HAL_CMU_CLK_AUTO,
HAL_CMU_CLK_MANUAL,
HAL_CMU_CLK_AUTO,
HAL_CMU_CLK_MANUAL,
};
enum HAL_CMU_RST_STATUS_T {
HAL_CMU_RST_SET,
HAL_CMU_RST_CLR,
HAL_CMU_RST_SET,
HAL_CMU_RST_CLR,
};
enum HAL_CMU_TIMER_ID_T {
HAL_CMU_TIMER_ID_00,
HAL_CMU_TIMER_ID_01,
HAL_CMU_TIMER_ID_10,
HAL_CMU_TIMER_ID_11,
HAL_CMU_TIMER_ID_20,
HAL_CMU_TIMER_ID_21,
HAL_CMU_TIMER_ID_00,
HAL_CMU_TIMER_ID_01,
HAL_CMU_TIMER_ID_10,
HAL_CMU_TIMER_ID_11,
HAL_CMU_TIMER_ID_20,
HAL_CMU_TIMER_ID_21,
};
#ifndef HAL_CMU_FREQ_T
enum HAL_CMU_FREQ_T {
HAL_CMU_FREQ_32K,
HAL_CMU_FREQ_26M,
HAL_CMU_FREQ_52M,
HAL_CMU_FREQ_78M,
HAL_CMU_FREQ_104M,
HAL_CMU_FREQ_208M,
HAL_CMU_FREQ_32K,
HAL_CMU_FREQ_26M,
HAL_CMU_FREQ_52M,
HAL_CMU_FREQ_78M,
HAL_CMU_FREQ_104M,
HAL_CMU_FREQ_208M,
HAL_CMU_FREQ_QTY
HAL_CMU_FREQ_QTY
};
#endif
#ifndef HAL_CMU_PLL_T
enum HAL_CMU_PLL_T {
HAL_CMU_PLL_AUD,
HAL_CMU_PLL_USB,
HAL_CMU_PLL_AUD,
HAL_CMU_PLL_USB,
HAL_CMU_PLL_QTY
HAL_CMU_PLL_QTY
};
#endif
#ifndef HAL_CMU_PLL_USER_T
enum HAL_CMU_PLL_USER_T {
HAL_CMU_PLL_USER_SYS,
HAL_CMU_PLL_USER_AUD,
HAL_CMU_PLL_USER_USB,
HAL_CMU_PLL_USER_SYS,
HAL_CMU_PLL_USER_AUD,
HAL_CMU_PLL_USER_USB,
HAL_CMU_PLL_USER_QTY,
HAL_CMU_PLL_USER_ALL = HAL_CMU_PLL_USER_QTY,
HAL_CMU_PLL_USER_QTY,
HAL_CMU_PLL_USER_ALL = HAL_CMU_PLL_USER_QTY,
};
#endif
enum HAL_CMU_PERIPH_FREQ_T {
HAL_CMU_PERIPH_FREQ_26M,
HAL_CMU_PERIPH_FREQ_52M,
HAL_CMU_PERIPH_FREQ_26M,
HAL_CMU_PERIPH_FREQ_52M,
HAL_CMU_PERIPH_FREQ_QTY
HAL_CMU_PERIPH_FREQ_QTY
};
enum HAL_CMU_LPU_CLK_CFG_T {
HAL_CMU_LPU_CLK_NONE,
HAL_CMU_LPU_CLK_26M,
HAL_CMU_LPU_CLK_PLL,
HAL_CMU_LPU_CLK_NONE,
HAL_CMU_LPU_CLK_26M,
HAL_CMU_LPU_CLK_PLL,
HAL_CMU_LPU_CLK_QTY
HAL_CMU_LPU_CLK_QTY
};
enum HAL_CMU_LPU_SLEEP_MODE_T {
HAL_CMU_LPU_SLEEP_MODE_SYS,
HAL_CMU_LPU_SLEEP_MODE_CHIP,
HAL_CMU_LPU_SLEEP_MODE_SYS,
HAL_CMU_LPU_SLEEP_MODE_CHIP,
HAL_CMU_LPU_SLEEP_MODE_QTY
HAL_CMU_LPU_SLEEP_MODE_QTY
};
#ifndef HAL_PWM_ID_T
enum HAL_PWM_ID_T {
HAL_PWM_ID_0,
HAL_PWM_ID_1,
HAL_PWM_ID_2,
HAL_PWM_ID_3,
HAL_PWM_ID_0,
HAL_PWM_ID_1,
HAL_PWM_ID_2,
HAL_PWM_ID_3,
HAL_PWM_ID_QTY
HAL_PWM_ID_QTY
};
#endif
#ifndef HAL_I2S_ID_T
enum HAL_I2S_ID_T {
HAL_I2S_ID_0 = 0,
HAL_I2S_ID_0 = 0,
HAL_I2S_ID_QTY,
HAL_I2S_ID_QTY,
};
#endif
#ifndef HAL_SPDIF_ID_T
enum HAL_SPDIF_ID_T {
HAL_SPDIF_ID_0 = 0,
HAL_SPDIF_ID_0 = 0,
HAL_SPDIF_ID_QTY,
HAL_SPDIF_ID_QTY,
};
#endif
enum HAL_CMU_USB_CLOCK_SEL_T {
HAL_CMU_USB_CLOCK_SEL_PLL,
HAL_CMU_USB_CLOCK_SEL_24M_X2,
HAL_CMU_USB_CLOCK_SEL_48M,
HAL_CMU_USB_CLOCK_SEL_26M_X2,
HAL_CMU_USB_CLOCK_SEL_26M_X4,
HAL_CMU_USB_CLOCK_SEL_PLL,
HAL_CMU_USB_CLOCK_SEL_24M_X2,
HAL_CMU_USB_CLOCK_SEL_48M,
HAL_CMU_USB_CLOCK_SEL_26M_X2,
HAL_CMU_USB_CLOCK_SEL_26M_X4,
};
void hal_cmu_set_crystal_freq_index(uint32_t index);
@ -156,7 +156,8 @@ int hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id);
enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id);
int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mode);
int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id,
enum HAL_CMU_CLK_MODE_T mode);
enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id);
@ -406,9 +407,11 @@ uint32_t hal_cmu_simu_get_val(void);
void hal_cmu_low_freq_mode_init(void);
void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq);
void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq,
enum HAL_CMU_FREQ_T new_freq);
void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq);
void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq,
enum HAL_CMU_FREQ_T new_freq);
void hal_cmu_rom_enable_pll(void);
@ -420,8 +423,6 @@ void hal_cmu_rom_setup(void);
void hal_cmu_programmer_setup(void);
void hal_cmu_fpga_setup(void);
void hal_cmu_setup(void);
// Some internal functions
@ -459,4 +460,3 @@ volatile uint32_t *hal_cmu_get_memsc_addr(void);
#endif
#endif

26
platform/hal/hal_cmu_common.c
View File

@ -294,7 +294,6 @@ void hal_cmu_programmer_setup(void) {
hal_cmu_jtag_clock_enable();
#endif
#ifndef FPGA
int ret;
// Open analogif (ISPI)
ret = hal_analogif_open();
@ -314,31 +313,8 @@ void hal_cmu_programmer_setup(void) {
// Enable OSC X2/X4 in cmu after enabling their source in hal_chipid_init()
hal_cmu_osc_x2_enable();
hal_cmu_osc_x4_enable();
#endif
}
#ifdef FPGA
void BOOT_TEXT_FLASH_LOC hal_cmu_fpga_setup(void) {
hal_cmu_timer0_select_slow();
hal_sys_timer_open();
hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, HAL_CMU_FREQ_52M);
hal_cmu_apb_init_div();
hal_cmu_ispi_set_freq(HAL_CMU_PERIPH_FREQ_26M);
// Init peripheral clocks
hal_cmu_init_periph_clock();
hal_norflash_init();
#if defined(CHIP_HAS_PSRAM) && defined(PSRAM_ENABLE)
hal_psram_init();
#endif
}
#else // !FPGA
void BOOT_TEXT_FLASH_LOC hal_cmu_setup(void) {
int ret;
enum HAL_CMU_FREQ_T freq;
@ -420,5 +396,3 @@ void BOOT_TEXT_FLASH_LOC hal_cmu_setup(void) {
// Init flash
hal_norflash_init();
}
#endif // !FPGA

13
platform/hal/hal_i2s.c
View File

@ -66,7 +66,6 @@ struct HAL_I2S_MOD_NAME_T {
enum HAL_CMU_MOD_ID_T apb;
};
#ifndef FPGA
static const struct I2S_SAMPLE_RATE_T i2s_sample_rate[] = {
{AUD_SAMPRATE_8000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, I2S_CMU_DIV},
{AUD_SAMPRATE_16000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, I2S_CMU_DIV},
@ -86,7 +85,6 @@ static const struct I2S_SAMPLE_RATE_T i2s_sample_rate[] = {
{AUD_SAMPRATE_768000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, I2S_CMU_DIV},
{AUD_SAMPRATE_1024000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, I2S_CMU_DIV},
};
#endif
static const char *const invalid_id = "Invalid I2S ID: %d\n";
// static const char * const invalid_ch = "Invalid I2S CH: %d\n";
@ -504,17 +502,7 @@ int hal_i2s_setup_stream(enum HAL_I2S_ID_T id, enum AUD_STREAM_T stream,
cfg->channel_num);
if (i2s_mode[id] == HAL_I2S_MODE_MASTER) {
#ifdef FPGA
uint32_t sclk;
sclk = cfg->sample_rate * cycles * AUD_CHANNEL_NUM_2;
#define I2S_CLOCK_SOURCE 22579200 // 44100*512
div = I2S_CLOCK_SOURCE / sclk - 1;
#undef I2S_CLOCK_SOURCE
TRACE(1, "div = %x", div);
#else
uint32_t i2s_clock;
uint32_t bit_rate;
@ -565,7 +553,6 @@ int hal_i2s_setup_stream(enum HAL_I2S_ID_T id, enum AUD_STREAM_T stream,
// By default MCLK is half of (CODEC_FREQ_24P576M or CODEC_FREQ_22P5792M)
hal_spdif_clock_out_enable(HAL_SPDIF_ID_0,
i2s_sample_rate[i].cmu_div * I2S_MCLK_DIV);
#endif
#endif
hal_cmu_i2s_set_div(id, div);

5
platform/hal/hal_norflash.c
View File

@ -89,10 +89,7 @@ static const struct HAL_NORFLASH_CONFIG_T norflash_cfg = {
.source_clk = HAL_NORFLASH_SPEED_52M,
.speed = HAL_NORFLASH_SPEED_52M,
#else
#ifdef FPGA
.source_clk = HAL_NORFLASH_SPEED_13M * 2,
.speed = HAL_NORFLASH_SPEED_13M,
#elif defined(FLASH_LOW_SPEED)
#if defined(FLASH_LOW_SPEED)
.source_clk = HAL_NORFLASH_SPEED_26M * 2,
.speed = HAL_NORFLASH_SPEED_26M,
#elif defined(OSC_26M_X4_AUD2BB)

31
platform/hal/hal_psramuhs.c
View File

@ -26,15 +26,15 @@
#include "psramuhsphy.h"
#include "reg_psramuhs_mc.h"
//#define PSRAMUHS_DUAL_8BIT
//#define PSRAMUHS_BURST_REFRESH
//#define PSRAMUHS_DUMMY_CYCLE
//#define PSRAMUHS_PRA_ENABLE
//#define PSRAMUHS_DUAL_SWITCH
//#define PSRAMUHS_DIG_LOOPBACK
//#define PSRAMUHS_ANA_LOOPBACK
//#define PSRAMUHS_AUTO_PRECHARGE
//#define PSRAMUHS_WRAP_ENABLE
// #define PSRAMUHS_DUAL_8BIT
// #define PSRAMUHS_BURST_REFRESH
// #define PSRAMUHS_DUMMY_CYCLE
// #define PSRAMUHS_PRA_ENABLE
// #define PSRAMUHS_DUAL_SWITCH
// #define PSRAMUHS_DIG_LOOPBACK
// #define PSRAMUHS_ANA_LOOPBACK
// #define PSRAMUHS_AUTO_PRECHARGE
// #define PSRAMUHS_WRAP_ENABLE
#if defined(CHIP_BEST2001) && !defined(PSRAMUHS_DUMMY_CYCLE)
#define PSRAMUHS_DUMMY_CYCLE
@ -71,15 +71,11 @@ enum MEMIF_CMD_T {
static struct PSRAMUHS_MC_T *const psramuhs_mc =
(struct PSRAMUHS_MC_T *)PSRAMUHS_CTRL_BASE;
#ifdef FPGA
static const uint32_t psramuhs_run_clk = 26000000;
#else
#if (PSRAMUHS_SPEED != 0)
static const uint32_t psramuhs_run_clk = PSRAMUHS_SPEED * 1000 * 1000;
#else
#error "invalid PSRAMUHS_SPEED"
#endif
#endif
static int hal_psramuhsip_mc_busy(void) {
return !!(psramuhs_mc->REG_404 & PSRAM_UHS_MC_BUSY);
@ -356,9 +352,6 @@ static void hal_psramuhs_mc_set_timing(uint32_t clk) {
psramuhs_mc->REG_04C =
PSRAM_UHS_MC_T_REFI(val) | PSRAM_UHS_MC_NUM_OF_BURST_RFS(0x1000);
#ifdef FPGA
clk = 800 * 1000 * 1000;
#endif
// tRC >= 60 ns
val = ((clk / 1000000) * 60 + (1000 - 1)) / 1000;
psramuhs_mc->REG_050 = PSRAM_UHS_MC_T_RC(val);
@ -539,11 +532,9 @@ static void hal_psramuhs_mc_init(uint32_t clk) {
psramuhs_mc->REG_840 |= PSRAM_UHS_MC_ANA_LOOPBACK_EN;
#endif
#ifndef FPGA
#if !defined(PSRAMUHS_DIG_LOOPBACK) && !defined(PSRAMUHS_ANA_LOOPBACK)
psramuhsphy_init_calib();
#endif
#endif
}
void hal_psramuhs_mc_entry_auto_lp() {
@ -579,9 +570,7 @@ void hal_psramuhs_init(void) {
hal_cmu_reset_clear(HAL_CMU_MOD_O_PSRAMUHS);
hal_cmu_reset_clear(HAL_CMU_MOD_H_PSRAMUHS);
#ifndef FPGA
psramuhsphy_open(psramuhs_run_clk);
#endif
hal_psramuhs_mc_init(psramuhs_run_clk);
psramuhs_start_clock();
hal_sys_timer_delay_us(3);
@ -589,12 +578,10 @@ void hal_psramuhs_init(void) {
psramuhs_stop_clock();
psramuhs_set_timing(psramuhs_run_clk);
hal_psramuhs_refresh_enable();
#ifndef FPGA
#if !defined(PSRAMUHS_DIG_LOOPBACK) && !defined(PSRAMUHS_ANA_LOOPBACK)
hal_psramuhs_snoop_disable();
psramuhsphy_calib(psramuhs_run_clk);
hal_psramuhs_snoop_enable();
#endif
#endif
// hal_psramuhs_mc_entry_auto_lp();
}

22
platform/hal/hal_sdmmc.c
View File

@ -34,12 +34,12 @@
#endif
#define HAL_SDMMC_USE_DMA 1
//#define __BUS_WIDTH_SUPPORT_4BIT__ 1
// #define __BUS_WIDTH_SUPPORT_4BIT__ 1
#define HAL_SDMMC_TRACE(...)
//#define HAL_SDMMC_TRACE TRACE
// #define HAL_SDMMC_TRACE TRACE
#define HAL_SDMMC_ASSERT(...)
//#define HAL_SDMMC_ASSERT ASSERT
// #define HAL_SDMMC_ASSERT ASSERT
#define _SDMMC_CLOCK 52000000
@ -1194,9 +1194,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len) {
return mmc_send_cmd(mmc, &cmd, NULL);
}
struct mmc *find_mmc_device(int dev_num) {
return &sdmmc_devices[dev_num];
}
struct mmc *find_mmc_device(int dev_num) { return &sdmmc_devices[dev_num]; }
static int mmc_read_blocks(struct mmc *mmc, void *dst, uint32_t start,
uint32_t blkcnt) {
@ -2572,25 +2570,13 @@ int32_t hal_sdmmc_open(enum HAL_SDMMC_ID_T id) {
struct sdmmcip_host *host = NULL;
HAL_SDMMC_ASSERT(id < HAL_SDMMC_ID_NUM, invalid_id, id);
#ifdef FPGA
hal_cmu_sdmmc_set_freq(HAL_CMU_PERIPH_FREQ_26M);
#else
hal_cmu_sdmmc_set_freq(HAL_CMU_PERIPH_FREQ_52M);
#endif
hal_cmu_clock_enable(HAL_CMU_MOD_O_SDMMC);
hal_cmu_clock_enable(HAL_CMU_MOD_H_SDMMC);
hal_cmu_reset_clear(HAL_CMU_MOD_O_SDMMC);
hal_cmu_reset_clear(HAL_CMU_MOD_H_SDMMC);
#ifdef FPGA
#ifdef CHIP_BEST1000
/* iomux */
*((volatile uint32_t *)0x4001f004) |= 0x1 << 16;
*((volatile uint32_t *)0x4001f004) |= 0x1 << 17;
#endif
#endif
host = &sdmmc_host[id];
host->ioaddr = (void *)sdmmc_ip_base[id];

14
platform/hal/hal_spdif.c
View File

@ -26,13 +26,13 @@
#include "plat_types.h"
#include "reg_spdifip.h"
//#define SPDIF_CLOCK_SOURCE 240000000
//#define SPDIF_CLOCK_SOURCE 22579200
//#define SPDIF_CLOCK_SOURCE 48000000
// #define SPDIF_CLOCK_SOURCE 240000000
// #define SPDIF_CLOCK_SOURCE 22579200
// #define SPDIF_CLOCK_SOURCE 48000000
#define SPDIF_CLOCK_SOURCE 3072000
//#define SPDIF_CLOCK_SOURCE 76800000
//#define SPDIF_CLOCK_SOURCE 84672000
// #define SPDIF_CLOCK_SOURCE 76800000
// #define SPDIF_CLOCK_SOURCE 84672000
// Trigger DMA request when TX-FIFO count <= threshold
#define HAL_SPDIF_TX_FIFO_TRIGGER_LEVEL (SPDIFIP_FIFO_DEPTH / 2)
@ -324,9 +324,6 @@ int hal_spdif_setup_stream(enum HAL_SPDIF_ID_T id, enum AUD_STREAM_T stream,
TRACE(3, "[%s] stream=%d sample_rate=%d", __func__, stream, cfg->sample_rate);
#ifdef FPGA
hal_cmu_spdif_set_div(id, 2);
#else
#ifndef SIMU
analog_aud_freq_pll_config(spdif_sample_rate[i].codec_freq,
spdif_sample_rate[i].codec_div);
@ -337,7 +334,6 @@ int hal_spdif_setup_stream(enum HAL_SPDIF_ID_T id, enum AUD_STREAM_T stream,
#endif
// SPDIF module is working on 24.576M or 22.5792M
hal_cmu_spdif_set_div(id, spdif_sample_rate[i].pcm_div);
#endif
if ((stream == AUD_STREAM_PLAYBACK &&
spdif_status[id][AUD_STREAM_CAPTURE] == HAL_SPDIF_STATUS_NULL) ||

75
platform/hal/hal_timer.h
View File

@ -20,45 +20,42 @@
extern "C" {
#endif
#include "plat_types.h"
#include "hal_cmu.h"
#include "plat_types.h"
//=============================================================================
// Slow Timer (Default Timer)
#ifdef FPGA
#define CONFIG_SYSTICK_HZ_NOMINAL (32000)
#else
#define CONFIG_SYSTICK_HZ_NOMINAL (16000)
#endif
#define CONFIG_SYSTICK_HZ_NOMINAL (16000)
//#if (CONFIG_SYSTICK_HZ_NOMINAL % 1000)
//#error "Bad CONFIG_SYSTICK_HZ_NOMINAL configuration"
//#endif
// #if (CONFIG_SYSTICK_HZ_NOMINAL % 1000)
// #error "Bad CONFIG_SYSTICK_HZ_NOMINAL configuration"
// #endif
#ifdef CALIB_SLOW_TIMER
#define CONFIG_SYSTICK_HZ hal_sys_timer_systick_hz()
#define CONFIG_SYSTICK_HZ hal_sys_timer_systick_hz()
#define __MS_TO_TICKS(ms) hal_sys_timer_ms_to_ticks(ms)
#define __MS_TO_TICKS(ms) hal_sys_timer_ms_to_ticks(ms)
#define __US_TO_TICKS(us) hal_sys_timer_us_to_ticks(us)
#define __US_TO_TICKS(us) hal_sys_timer_us_to_ticks(us)
#define __TICKS_TO_MS(tick) hal_sys_timer_ticks_to_ms(tick)
#define __TICKS_TO_MS(tick) hal_sys_timer_ticks_to_ms(tick)
#define __TICKS_TO_US(tick) hal_sys_timer_ticks_to_us(tick)
#define __TICKS_TO_US(tick) hal_sys_timer_ticks_to_us(tick)
#else
#define CONFIG_SYSTICK_HZ CONFIG_SYSTICK_HZ_NOMINAL
#define CONFIG_SYSTICK_HZ CONFIG_SYSTICK_HZ_NOMINAL
#define __MS_TO_TICKS(ms) ((ms) * ((uint32_t)CONFIG_SYSTICK_HZ / 1000))
#define __MS_TO_TICKS(ms) ((ms) * ((uint32_t)CONFIG_SYSTICK_HZ / 1000))
#define __US_TO_TICKS(us) (((us) * ((uint32_t)CONFIG_SYSTICK_HZ / 1000) + 1000 - 1) / 1000 + 1)
#define __US_TO_TICKS(us) \
(((us) * ((uint32_t)CONFIG_SYSTICK_HZ / 1000) + 1000 - 1) / 1000 + 1)
#define __TICKS_TO_MS(tick) ((tick) / ((uint32_t)CONFIG_SYSTICK_HZ / 1000))
#define __TICKS_TO_MS(tick) ((tick) / ((uint32_t)CONFIG_SYSTICK_HZ / 1000))
#define __TICKS_TO_US(tick) ((tick) * 1000 / ((uint32_t)CONFIG_SYSTICK_HZ / 1000))
#define __TICKS_TO_US(tick) ((tick)*1000 / ((uint32_t)CONFIG_SYSTICK_HZ / 1000))
#endif
@ -75,25 +72,25 @@ extern "C" {
* Note, don't use these macros, use MS_TO_HWTICKS/US_TO_HWTICKS/HWTICKS_TO_MS
* alternately
*/
#define MS_TO_TICKS(ms) __MS_TO_TICKS(ms)
#define MS_TO_TICKS(ms) __MS_TO_TICKS(ms)
#define US_TO_TICKS(us) __US_TO_TICKS(us)
#define US_TO_TICKS(us) __US_TO_TICKS(us)
#define TICKS_TO_MS(tick) __TICKS_TO_MS(tick)
#define TICKS_TO_MS(tick) __TICKS_TO_MS(tick)
#define TICKS_TO_US(tick) __TICKS_TO_US(tick)
#define TICKS_TO_US(tick) __TICKS_TO_US(tick)
#define MS_TO_HWTICKS(ms) __MS_TO_TICKS(ms)
#define MS_TO_HWTICKS(ms) __MS_TO_TICKS(ms)
#define US_TO_HWTICKS(us) __US_TO_TICKS(us)
#define US_TO_HWTICKS(us) __US_TO_TICKS(us)
#define HWTICKS_TO_MS(tick) __TICKS_TO_MS(tick)
#define HWTICKS_TO_MS(tick) __TICKS_TO_MS(tick)
#define HWTICKS_TO_US(tick) __TICKS_TO_US(tick)
#define HWTICKS_TO_US(tick) __TICKS_TO_US(tick)
#define GET_CURRENT_TICKS() hal_sys_timer_get()
#define GET_CURRENT_TICKS() hal_sys_timer_get()
#define GET_CURRENT_MS() TICKS_TO_MS(GET_CURRENT_TICKS())
#define GET_CURRENT_MS() TICKS_TO_MS(GET_CURRENT_TICKS())
void hal_sys_timer_open(void);
@ -138,19 +135,24 @@ uint32_t hal_timer_get_passed_ticks(uint32_t curr_ticks, uint32_t prev_ticks);
//=============================================================================
// Fast Timer
#define CONFIG_FAST_SYSTICK_HZ (hal_cmu_get_crystal_freq() / 4)
#define CONFIG_FAST_SYSTICK_HZ (hal_cmu_get_crystal_freq() / 4)
#define MS_TO_FAST_TICKS(ms) ((uint32_t)(ms) * (CONFIG_FAST_SYSTICK_HZ / 1000))
#define MS_TO_FAST_TICKS(ms) ((uint32_t)(ms) * (CONFIG_FAST_SYSTICK_HZ / 1000))
#define US_TO_FAST_TICKS(us) ((uint32_t)(us) * (CONFIG_FAST_SYSTICK_HZ / 1000 / 100) / 10)
#define US_TO_FAST_TICKS(us) \
((uint32_t)(us) * (CONFIG_FAST_SYSTICK_HZ / 1000 / 100) / 10)
#define NS_TO_FAST_TICKS(ns) ((uint32_t)(ns) * (CONFIG_FAST_SYSTICK_HZ / 1000 / 100) / 10 / 1000)
#define NS_TO_FAST_TICKS(ns) \
((uint32_t)(ns) * (CONFIG_FAST_SYSTICK_HZ / 1000 / 100) / 10 / 1000)
#define FAST_TICKS_TO_MS(tick) ((uint32_t)(tick) / (CONFIG_FAST_SYSTICK_HZ / 1000))
#define FAST_TICKS_TO_MS(tick) \
((uint32_t)(tick) / (CONFIG_FAST_SYSTICK_HZ / 1000))
#define FAST_TICKS_TO_US(tick) ((uint32_t)(tick) * 10 / (CONFIG_FAST_SYSTICK_HZ / 1000 / 100))
#define FAST_TICKS_TO_US(tick) \
((uint32_t)(tick)*10 / (CONFIG_FAST_SYSTICK_HZ / 1000 / 100))
#define FAST_TICKS_TO_NS(tick) ((uint32_t)(tick) * 10 * 1000 / (CONFIG_FAST_SYSTICK_HZ / 1000 / 100))
#define FAST_TICKS_TO_NS(tick) \
((uint32_t)(tick)*10 * 1000 / (CONFIG_FAST_SYSTICK_HZ / 1000 / 100))
uint32_t hal_fast_sys_timer_get(void);
@ -163,4 +165,3 @@ int osDelay(uint32_t ms);
#endif
#endif

474
platform/hal/hal_trace.h
View File

@ -20,8 +20,8 @@
extern "C" {
#endif
#include "plat_types.h"
#include "hal_trace_mod.h"
#include "plat_types.h"
#if 0
#define AUDIO_DEBUG
@ -29,15 +29,15 @@ extern "C" {
#define INTERSYS_RAW_DATA_ONLY
#ifdef AUDIO_DEBUG
#undef TRACE_BAUD_RATE
#define TRACE_BAUD_RATE 2000000
#define TRACE_BAUD_RATE 2000000
#endif
#endif
#if (defined(AUDIO_DEBUG) && !defined(AUDIO_DEBUG_V0_1_0))
#define NO_REL_TRACE
#endif
#if (defined(AUDIO_DEBUG) && !defined(AUDIO_DEBUG_V0_1_0)) || \
defined(INTERSYS_RAW_DATA_ONLY)
#if (defined(AUDIO_DEBUG) && !defined(AUDIO_DEBUG_V0_1_0)) || \
defined(INTERSYS_RAW_DATA_ONLY)
#define NO_TRACE
#endif
@ -55,235 +55,313 @@ extern "C" {
/*
* Total number of core registers stored
*/
#define CRASH_DUMP_REGISTERS_NUM 17
#define CRASH_DUMP_REGISTERS_NUM_BYTES ((CRASH_DUMP_REGISTERS_NUM)*4)
#define CRASH_DUMP_REGISTERS_NUM 17
#define CRASH_DUMP_REGISTERS_NUM_BYTES ((CRASH_DUMP_REGISTERS_NUM)*4)
/*
* Number bytes to store from stack
* - this is total, not per PSP/MSP
*/
#define CRASH_DUMP_STACK_NUM_BYTES 384
#define CRASH_DUMP_STACK_NUM_BYTES 384
// Log Attributes
#define LOG_ATTR_ARG_NUM_SHIFT 0
#define LOG_ATTR_ARG_NUM_MASK (0xF << LOG_ATTR_ARG_NUM_SHIFT)
#define LOG_ATTR_ARG_NUM(n) BITFIELD_VAL(LOG_ATTR_ARG_NUM, n)
#define LOG_ATTR_LEVEL_SHIFT 4
#define LOG_ATTR_LEVEL_MASK (0x7 << LOG_ATTR_LEVEL_SHIFT)
#define LOG_ATTR_LEVEL(n) BITFIELD_VAL(LOG_ATTR_LEVEL, n)
#define LOG_ATTR_MOD_SHIFT 7
#define LOG_ATTR_MOD_MASK (0x7F << LOG_ATTR_MOD_SHIFT)
#define LOG_ATTR_MOD(n) BITFIELD_VAL(LOG_ATTR_MOD, n)
#define LOG_ATTR_IMM (1 << 14)
#define LOG_ATTR_NO_LF (1 << 15)
#define LOG_ATTR_NO_TS (1 << 16)
#define LOG_ATTR_NO_ID (1 << 17)
#define LOG_ATTR_ARG_NUM_SHIFT 0
#define LOG_ATTR_ARG_NUM_MASK (0xF << LOG_ATTR_ARG_NUM_SHIFT)
#define LOG_ATTR_ARG_NUM(n) BITFIELD_VAL(LOG_ATTR_ARG_NUM, n)
#define LOG_ATTR_LEVEL_SHIFT 4
#define LOG_ATTR_LEVEL_MASK (0x7 << LOG_ATTR_LEVEL_SHIFT)
#define LOG_ATTR_LEVEL(n) BITFIELD_VAL(LOG_ATTR_LEVEL, n)
#define LOG_ATTR_MOD_SHIFT 7
#define LOG_ATTR_MOD_MASK (0x7F << LOG_ATTR_MOD_SHIFT)
#define LOG_ATTR_MOD(n) BITFIELD_VAL(LOG_ATTR_MOD, n)
#define LOG_ATTR_IMM (1 << 14)
#define LOG_ATTR_NO_LF (1 << 15)
#define LOG_ATTR_NO_TS (1 << 16)
#define LOG_ATTR_NO_ID (1 << 17)
// Count variadic argument number
#define _VAR_ARG_12(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, ...) a12
#define COUNT_ARG_NUM(...) _VAR_ARG_12(unused, ##__VA_ARGS__, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
#define COUNT_ARG_NUM(...) \
_VAR_ARG_12(unused, ##__VA_ARGS__, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
#if defined(TRACE_STR_SECTION) && !(defined(ROM_BUILD) || defined(PROGRAMMER) || defined(FPGA))
#define CONCAT_(x,y) x##y
#define CONCATS(x,y) CONCAT_(x,y)
#define __trcname CONCATS(__trc, __LINE__)
#define TRC_STR_LOC __attribute__((section(TO_STRING(CONCATS(.trc_str,__LINE__)))))
#define TRC_STR(s) (({ static const char TRC_STR_LOC __trcname[] = (s); __trcname; }))
#if defined(TRACE_STR_SECTION) && !(defined(ROM_BUILD) || defined(PROGRAMMER))
#define CONCAT_(x, y) x##y
#define CONCATS(x, y) CONCAT_(x, y)
#define __trcname CONCATS(__trc, __LINE__)
#define TRC_STR_LOC \
__attribute__((section(TO_STRING(CONCATS(.trc_str, __LINE__)))))
#define TRC_STR(s) \
(({ \
static const char TRC_STR_LOC __trcname[] = (s); \
__trcname; \
}))
#else
#define TRC_STR_LOC
#define TRC_STR(s) (s)
#define TRC_STR(s) (s)
#endif
#define LOG_DUMMY(attr, str, ...) hal_trace_dummy(str, ##__VA_ARGS__)
#define LOG_DUMMY(attr, str, ...) hal_trace_dummy(str, ##__VA_ARGS__)
#if (defined(DEBUG) || defined(REL_TRACE_ENABLE)) && !defined(NO_REL_TRACE)
#define REL_LOG(attr, str, ...) hal_trace_printf(((attr) & ~LOG_ATTR_ARG_NUM_MASK) | \
LOG_ATTR_ARG_NUM(COUNT_ARG_NUM(unused, ##__VA_ARGS__)), \
TRC_STR(str), ##__VA_ARGS__)
#define REL_LOG_RAW_OUTPUT(str, len) hal_trace_output(str, len)
#define REL_LOG_FLUSH() hal_trace_flush_buffer()
#define REL_DUMP8(str, buf, cnt) hal_trace_dump(str, sizeof(uint8_t), cnt, buf)
#define REL_DUMP16(str, buf, cnt) hal_trace_dump(str, sizeof(uint16_t), cnt, buf)
#define REL_DUMP32(str, buf, cnt) hal_trace_dump(str, sizeof(uint32_t), cnt, buf)
#define REL_LOG(attr, str, ...) \
hal_trace_printf(((attr) & ~LOG_ATTR_ARG_NUM_MASK) | \
LOG_ATTR_ARG_NUM(COUNT_ARG_NUM(unused, ##__VA_ARGS__)), \
TRC_STR(str), ##__VA_ARGS__)
#define REL_LOG_RAW_OUTPUT(str, len) hal_trace_output(str, len)
#define REL_LOG_FLUSH() hal_trace_flush_buffer()
#define REL_DUMP8(str, buf, cnt) hal_trace_dump(str, sizeof(uint8_t), cnt, buf)
#define REL_DUMP16(str, buf, cnt) \
hal_trace_dump(str, sizeof(uint16_t), cnt, buf)
#define REL_DUMP32(str, buf, cnt) \
hal_trace_dump(str, sizeof(uint32_t), cnt, buf)
#else
#define REL_LOG(attr, str, ...) hal_trace_dummy(str, ##__VA_ARGS__)
#define REL_LOG_RAW_OUTPUT(str, len) hal_trace_dummy((const char *)str, len)
#define REL_LOG_FLUSH() hal_trace_dummy(NULL)
#define REL_DUMP8(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define REL_DUMP16(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define REL_DUMP32(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define REL_LOG(attr, str, ...) hal_trace_dummy(str, ##__VA_ARGS__)
#define REL_LOG_RAW_OUTPUT(str, len) hal_trace_dummy((const char *)str, len)
#define REL_LOG_FLUSH() hal_trace_dummy(NULL)
#define REL_DUMP8(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define REL_DUMP16(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define REL_DUMP32(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#endif
#if (!defined(DEBUG) && defined(REL_TRACE_ENABLE)) && !defined(NO_TRACE)
// To avoid warnings on unused variables
#define NORM_LOG(num,str, ...) hal_trace_dummy(str, ##__VA_ARGS__)
#define NORM_LOG_RAW_OUTPUT(str, len) hal_trace_dummy((const char *)str, len)
#define NORM_LOG_FLUSH() hal_trace_dummy(NULL)
#define DUMP8(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define DUMP16(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define DUMP32(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define NORM_LOG(num, str, ...) hal_trace_dummy(str, ##__VA_ARGS__)
#define NORM_LOG_RAW_OUTPUT(str, len) hal_trace_dummy((const char *)str, len)
#define NORM_LOG_FLUSH() hal_trace_dummy(NULL)
#define DUMP8(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define DUMP16(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#define DUMP32(str, buf, cnt) hal_dump_dummy(str, buf, cnt)
#else
#define NORM_LOG REL_LOG
#define NORM_LOG_RAW_OUTPUT REL_LOG_RAW_OUTPUT
#define NORM_LOG_FLUSH REL_TRACE_FLUSH
#define DUMP8 REL_DUMP8
#define DUMP16 REL_DUMP16
#define DUMP32 REL_DUMP32
#define NORM_LOG REL_LOG
#define NORM_LOG_RAW_OUTPUT REL_LOG_RAW_OUTPUT
#define NORM_LOG_FLUSH REL_TRACE_FLUSH
#define DUMP8 REL_DUMP8
#define DUMP16 REL_DUMP16
#define DUMP32 REL_DUMP32
#endif
#define RLOG_CRITICAL(attr, str, ...) REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_CRITICAL), \
str, ##__VA_ARGS__)
#define RLOG_ERROR(attr, str, ...) REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_ERROR), \
str, ##__VA_ARGS__)
#define RLOG_WARN(attr, str, ...) REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_WARN), \
str, ##__VA_ARGS__)
#define RLOG_NOTIF(attr, str, ...) REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_NOTIF), \
str, ##__VA_ARGS__)
#define RLOG_INFO(attr, str, ...) REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_INFO), \
str, ##__VA_ARGS__)
#define RLOG_DEBUG(attr, str, ...) REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_DEBUG), \
str, ##__VA_ARGS__)
#define RLOG_VERBOSE(attr, str, ...) REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_VERBOSE), \
str, ##__VA_ARGS__)
#define RLOG_CRITICAL(attr, str, ...) \
REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | \
LOG_ATTR_LEVEL(LOG_LEVEL_CRITICAL), \
str, ##__VA_ARGS__)
#define RLOG_ERROR(attr, str, ...) \
REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_ERROR), \
str, ##__VA_ARGS__)
#define RLOG_WARN(attr, str, ...) \
REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_WARN), \
str, ##__VA_ARGS__)
#define RLOG_NOTIF(attr, str, ...) \
REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_NOTIF), \
str, ##__VA_ARGS__)
#define RLOG_INFO(attr, str, ...) \
REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_INFO), \
str, ##__VA_ARGS__)
#define RLOG_DEBUG(attr, str, ...) \
REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_DEBUG), \
str, ##__VA_ARGS__)
#define RLOG_VERBOSE(attr, str, ...) \
REL_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_VERBOSE), \
str, ##__VA_ARGS__)
#define LOG_CRITICAL(attr, str, ...) NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_CRITICAL), \
str, ##__VA_ARGS__)
#define LOG_ERROR(attr, str, ...) NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_ERROR), \
str, ##__VA_ARGS__)
#define LOG_WARN(attr, str, ...) NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_WARN), \
str, ##__VA_ARGS__)
#define LOG_NOTIF(attr, str, ...) NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_NOTIF), \
str, ##__VA_ARGS__)
#define LOG_INFO(attr, str, ...) NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_INFO), \
str, ##__VA_ARGS__)
#define LOG_DEBUG(attr, str, ...) NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_DEBUG), \
str, ##__VA_ARGS__)
#define LOG_VERBOSE(attr, str, ...) NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_VERBOSE), \
str, ##__VA_ARGS__)
#define LOG_CRITICAL(attr, str, ...) \
NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | \
LOG_ATTR_LEVEL(LOG_LEVEL_CRITICAL), \
str, ##__VA_ARGS__)
#define LOG_ERROR(attr, str, ...) \
NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_ERROR), \
str, ##__VA_ARGS__)
#define LOG_WARN(attr, str, ...) \
NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_WARN), \
str, ##__VA_ARGS__)
#define LOG_NOTIF(attr, str, ...) \
NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_NOTIF), \
str, ##__VA_ARGS__)
#define LOG_INFO(attr, str, ...) \
NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_INFO), \
str, ##__VA_ARGS__)
#define LOG_DEBUG(attr, str, ...) \
NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | LOG_ATTR_LEVEL(LOG_LEVEL_DEBUG), \
str, ##__VA_ARGS__)
#define LOG_VERBOSE(attr, str, ...) \
NORM_LOG(((attr) & ~LOG_ATTR_LEVEL_MASK) | \
LOG_ATTR_LEVEL(LOG_LEVEL_VERBOSE), \
str, ##__VA_ARGS__)
#define REL_TRACE(attr, str, ...) RLOG_NOTIF(attr, str, ##__VA_ARGS__)
#define REL_TRACE_IMM(attr, str, ...) RLOG_NOTIF((attr) | LOG_ATTR_IMM, str, ##__VA_ARGS__)
#define REL_TRACE_NOCRLF(attr, str, ...) RLOG_NOTIF((attr) | LOG_ATTR_NO_LF, str, ##__VA_ARGS__)
#define REL_TRACE_NOTS(attr, str, ...) RLOG_NOTIF((attr) | LOG_ATTR_NO_TS, str, ##__VA_ARGS__)
#define REL_TRACE_IMM_NOTS(attr, str, ...) RLOG_NOTIF((attr) | LOG_ATTR_IMM | LOG_ATTR_NO_TS, str, ##__VA_ARGS__)
#define REL_TRACE_NOCRLF_NOTS(attr, str, ...) RLOG_NOTIF((attr) | LOG_ATTR_NO_LF | LOG_ATTR_NO_TS, str, ##__VA_ARGS__)
#define REL_FUNC_ENTRY_TRACE() RLOG_NOTIF(1, "%s", __FUNCTION__)
#define REL_TRACE_OUTPUT(str, len) REL_LOG_RAW_OUTPUT(str, len)
#define REL_TRACE_FLUSH() REL_LOG_FLUSH()
#define REL_TRACE(attr, str, ...) RLOG_NOTIF(attr, str, ##__VA_ARGS__)
#define REL_TRACE_IMM(attr, str, ...) \
RLOG_NOTIF((attr) | LOG_ATTR_IMM, str, ##__VA_ARGS__)
#define REL_TRACE_NOCRLF(attr, str, ...) \
RLOG_NOTIF((attr) | LOG_ATTR_NO_LF, str, ##__VA_ARGS__)
#define REL_TRACE_NOTS(attr, str, ...) \
RLOG_NOTIF((attr) | LOG_ATTR_NO_TS, str, ##__VA_ARGS__)
#define REL_TRACE_IMM_NOTS(attr, str, ...) \
RLOG_NOTIF((attr) | LOG_ATTR_IMM | LOG_ATTR_NO_TS, str, ##__VA_ARGS__)
#define REL_TRACE_NOCRLF_NOTS(attr, str, ...) \
RLOG_NOTIF((attr) | LOG_ATTR_NO_LF | LOG_ATTR_NO_TS, str, ##__VA_ARGS__)
#define REL_FUNC_ENTRY_TRACE() RLOG_NOTIF(1, "%s", __FUNCTION__)
#define REL_TRACE_OUTPUT(str, len) REL_LOG_RAW_OUTPUT(str, len)
#define REL_TRACE_FLUSH() REL_LOG_FLUSH()
#define TRACE(attr, str, ...) LOG_INFO(attr, str, ##__VA_ARGS__)
#define TRACE_IMM(attr, str, ...) LOG_INFO((attr) | LOG_ATTR_IMM, str, ##__VA_ARGS__)
#define TRACE_NOCRLF(attr, str, ...) LOG_INFO((attr) | LOG_ATTR_NO_LF, str, ##__VA_ARGS__)
#define FUNC_ENTRY_TRACE() LOG_INFO(1, "%s", __FUNCTION__)
#define TRACE_OUTPUT(str, len) NORM_LOG_RAW_OUTPUT(str, len)
#define TRACE_FLUSH() NORM_LOG_FLUSH()
#define TRACE(attr, str, ...) LOG_INFO(attr, str, ##__VA_ARGS__)
#define TRACE_IMM(attr, str, ...) \
LOG_INFO((attr) | LOG_ATTR_IMM, str, ##__VA_ARGS__)
#define TRACE_NOCRLF(attr, str, ...) \
LOG_INFO((attr) | LOG_ATTR_NO_LF, str, ##__VA_ARGS__)
#define FUNC_ENTRY_TRACE() LOG_INFO(1, "%s", __FUNCTION__)
#define TRACE_OUTPUT(str, len) NORM_LOG_RAW_OUTPUT(str, len)
#define TRACE_FLUSH() NORM_LOG_FLUSH()
#ifdef BES_AUTOMATE_TEST
#define AUTO_TEST_TRACE(attr, str, ...) LOG_INFO(attr, "_AT_"str, ##__VA_ARGS__)
#define AUTO_TEST_TRACE(attr, str, ...) \
LOG_INFO(attr, "_AT_" str, ##__VA_ARGS__)
#else
#define AUTO_TEST_TRACE(attr, str, ...) LOG_INFO(attr, str, ##__VA_ARGS__)
#define AUTO_TEST_TRACE(attr, str, ...) LOG_INFO(attr, str, ##__VA_ARGS__)
#endif
#define TRACE_DUMMY(attr, str, ...) LOG_DUMMY(attr, str, ##__VA_ARGS__)
#define TRACE_DUMMY(attr, str, ...) LOG_DUMMY(attr, str, ##__VA_ARGS__)
#if (defined(DEBUG) || defined(REL_TRACE_ENABLE)) && defined(ASSERT_SHOW_FILE_FUNC)
#define ASSERT(cond, str, ...) { if (!(cond)) { hal_trace_assert_dump(__FILE__, __FUNCTION__, __LINE__, str, ##__VA_ARGS__); } }
#define ASSERT_DUMP_ARGS const char *file, const char *func, unsigned int line, const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 4
#if (defined(DEBUG) || defined(REL_TRACE_ENABLE)) && \
defined(ASSERT_SHOW_FILE_FUNC)
#define ASSERT(cond, str, ...) \
{ \
if (!(cond)) { \
hal_trace_assert_dump(__FILE__, __FUNCTION__, __LINE__, str, \
##__VA_ARGS__); \
} \
}
#define ASSERT_DUMP_ARGS \
const char *file, const char *func, unsigned int line, const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 4
#elif (defined(DEBUG) || defined(REL_TRACE_ENABLE)) && defined(ASSERT_SHOW_FILE)
#define ASSERT(cond, str, ...) { if (!(cond)) { hal_trace_assert_dump(__FILE__, __LINE__, str, ##__VA_ARGS__); } }
#define ASSERT_DUMP_ARGS const char *file, const char *func, unsigned int line, const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 4
#define ASSERT(cond, str, ...) \
{ \
if (!(cond)) { \
hal_trace_assert_dump(__FILE__, __LINE__, str, ##__VA_ARGS__); \
} \
}
#define ASSERT_DUMP_ARGS \
const char *file, const char *func, unsigned int line, const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 4
#elif (defined(DEBUG) || defined(REL_TRACE_ENABLE)) && defined(ASSERT_SHOW_FUNC)
#define ASSERT(cond, str, ...) { if (!(cond)) { hal_trace_assert_dump(__FUNCTION__, __LINE__, str, ##__VA_ARGS__); } }
#define ASSERT_DUMP_ARGS const char *scope, unsigned int line, const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 3
#define ASSERT(cond, str, ...) \
{ \
if (!(cond)) { \
hal_trace_assert_dump(__FUNCTION__, __LINE__, str, ##__VA_ARGS__); \
} \
}
#define ASSERT_DUMP_ARGS \
const char *scope, unsigned int line, const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 3
#elif (defined(DEBUG) || defined(REL_TRACE_ENABLE))
#define ASSERT(cond, str, ...) { if (!(cond)) { hal_trace_assert_dump(str, ##__VA_ARGS__); } }
#define ASSERT_DUMP_ARGS const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 1
#define ASSERT(cond, str, ...) \
{ \
if (!(cond)) { \
hal_trace_assert_dump(str, ##__VA_ARGS__); \
} \
}
#define ASSERT_DUMP_ARGS const char *fmt, ...
#define ASSERT_FMT_ARG_IDX 1
#else
#define ASSERT(cond, str, ...) { if (!(cond)) { hal_trace_dummy(str, ##__VA_ARGS__); hal_trace_assert_dump(NULL); } }
#define ASSERT_DUMP_ARGS const char *fmt
#define ASSERT_FMT_ARG_IDX 0
#define ASSERT(cond, str, ...) \
{ \
if (!(cond)) { \
hal_trace_dummy(str, ##__VA_ARGS__); \
hal_trace_assert_dump(NULL); \
} \
}
#define ASSERT_DUMP_ARGS const char *fmt
#define ASSERT_FMT_ARG_IDX 0
#endif
#if (defined(DEBUG) || defined(REL_TRACE_ENABLE))
#define TRACE_FUNC_DECLARE(d, r) d
#define TRACE_FUNC_DECLARE(d, r) d
#else
#ifndef TRACE_FUNC_SPEC
#define TRACE_FUNC_SPEC static inline
#define TRACE_FUNC_SPEC static inline
#endif
#define TRACE_FUNC_DECLARE(d, r) TRACE_FUNC_SPEC d { r; }
#define TRACE_FUNC_DECLARE(d, r) \
TRACE_FUNC_SPEC d { r; }
#endif
#if defined(__GNUC__) && !defined(NO_CHK_TRC_FMT)
#define TRC_FMT_CHK(sidx, vaidx) __attribute__((format(printf, (sidx), (vaidx))))
#define TRC_FMT_CHK(sidx, vaidx) \
__attribute__((format(printf, (sidx), (vaidx))))
#else
#define TRC_FMT_CHK(sidx, vaidx)
#endif
#define ASSERT_NODUMP(cond) { if (!(cond)) { SAFE_PROGRAM_STOP(); } }
#define ASSERT_NODUMP(cond) \
{ \
if (!(cond)) { \
SAFE_PROGRAM_STOP(); \
} \
}
#ifdef CHIP_BEST1000
// Avoid CPU instruction fetch blocking the system bus on BEST1000
#define SAFE_PROGRAM_STOP() do { asm volatile("nop; nop; nop; nop"); } while (1)
#define SAFE_PROGRAM_STOP() \
do { \
asm volatile("nop; nop; nop; nop"); \
} while (1)
#else
#define SAFE_PROGRAM_STOP() do { } while (1)
#define SAFE_PROGRAM_STOP() \
do { \
} while (1)
#endif
enum HAL_TRACE_TRANSPORT_T {
#ifdef CHIP_HAS_USB
HAL_TRACE_TRANSPORT_USB,
HAL_TRACE_TRANSPORT_USB,
#endif
HAL_TRACE_TRANSPORT_UART0,
HAL_TRACE_TRANSPORT_UART0,
#if (CHIP_HAS_UART > 1)
HAL_TRACE_TRANSPORT_UART1,
HAL_TRACE_TRANSPORT_UART1,
#endif
#if (CHIP_HAS_UART > 2)
HAL_TRACE_TRANSPORT_UART2,
HAL_TRACE_TRANSPORT_UART2,
#endif
HAL_TRACE_TRANSPORT_QTY
HAL_TRACE_TRANSPORT_QTY
};
enum HAL_TRACE_STATE_T {
HAL_TRACE_STATE_CRASH_ASSERT_START,
HAL_TRACE_STATE_CRASH_FAULT_START,
HAL_TRACE_STATE_CRASH_END,
HAL_TRACE_STATE_CRASH_ASSERT_START,
HAL_TRACE_STATE_CRASH_FAULT_START,
HAL_TRACE_STATE_CRASH_END,
};
enum HAL_TRACE_BUF_STATE_T {
HAL_TRACE_BUF_STATE_FLUSH,
HAL_TRACE_BUF_STATE_NEAR_FULL,
HAL_TRACE_BUF_STATE_FULL,
HAL_TRACE_BUF_STATE_FLUSH,
HAL_TRACE_BUF_STATE_NEAR_FULL,
HAL_TRACE_BUF_STATE_FULL,
};
enum HAL_TRACE_CRASH_DUMP_MODULE_T {
HAL_TRACE_CRASH_DUMP_MODULE_SYS = 0,
HAL_TRACE_CRASH_DUMP_MODULE_ID1 = 1,
HAL_TRACE_CRASH_DUMP_MODULE_ID2 = 2,
HAL_TRACE_CRASH_DUMP_MODULE_ID3 = 3,
HAL_TRACE_CRASH_DUMP_MODULE_BT = 4,
HAL_TRACE_CRASH_DUMP_MODULE_END = 5,
HAL_TRACE_CRASH_DUMP_MODULE_SYS = 0,
HAL_TRACE_CRASH_DUMP_MODULE_ID1 = 1,
HAL_TRACE_CRASH_DUMP_MODULE_ID2 = 2,
HAL_TRACE_CRASH_DUMP_MODULE_ID3 = 3,
HAL_TRACE_CRASH_DUMP_MODULE_BT = 4,
HAL_TRACE_CRASH_DUMP_MODULE_END = 5,
};
enum LOG_LEVEL_T {
LOG_LEVEL_CRITICAL = 0,
LOG_LEVEL_ERROR = 1,
LOG_LEVEL_WARN = 2,
LOG_LEVEL_NOTIF = 3,
LOG_LEVEL_INFO = 4,
LOG_LEVEL_DEBUG = 5,
LOG_LEVEL_VERBOSE = 6,
LOG_LEVEL_CRITICAL = 0,
LOG_LEVEL_ERROR = 1,
LOG_LEVEL_WARN = 2,
LOG_LEVEL_NOTIF = 3,
LOG_LEVEL_INFO = 4,
LOG_LEVEL_DEBUG = 5,
LOG_LEVEL_VERBOSE = 6,
LOG_LEVEL_QTY,
LOG_LEVEL_QTY,
};
typedef void (*HAL_TRACE_CRASH_DUMP_CB_T)(void);
typedef void (*HAL_TRACE_APP_NOTIFY_T)(enum HAL_TRACE_STATE_T state);
typedef void (*HAL_TRACE_APP_OUTPUT_T)(const unsigned char *buf, unsigned int buf_len);
typedef void (*HAL_TRACE_APP_OUTPUT_T)(const unsigned char *buf,
unsigned int buf_len);
typedef void (*HAL_TRACE_BUF_CTRL_T)(enum HAL_TRACE_BUF_STATE_T buf_ctrl);
@ -291,28 +369,54 @@ int hal_trace_open(enum HAL_TRACE_TRANSPORT_T transport);
int hal_trace_open_cp(void);
TRACE_FUNC_DECLARE(int hal_trace_switch(enum HAL_TRACE_TRANSPORT_T transport), return 0);
TRACE_FUNC_DECLARE(int hal_trace_switch(enum HAL_TRACE_TRANSPORT_T transport),
return 0);
TRACE_FUNC_DECLARE(int hal_trace_close(void), return 0);
TRACE_FUNC_DECLARE(int hal_trace_enable_log_module(enum LOG_MODULE_T module), return 0);
TRACE_FUNC_DECLARE(int hal_trace_enable_log_module(enum LOG_MODULE_T module),
return 0);
TRACE_FUNC_DECLARE(int hal_trace_disable_log_module(enum LOG_MODULE_T module), return 0);
TRACE_FUNC_DECLARE(int hal_trace_disable_log_module(enum LOG_MODULE_T module),
return 0);
TRACE_FUNC_DECLARE(int hal_trace_set_log_module(const uint32_t *map, uint32_t word_cnt), return 0);
TRACE_FUNC_DECLARE(int hal_trace_set_log_module(const uint32_t *map,
uint32_t word_cnt),
return 0);
TRACE_FUNC_DECLARE(int hal_trace_set_log_level(enum LOG_LEVEL_T level), return 0);
TRACE_FUNC_DECLARE(int hal_trace_set_log_level(enum LOG_LEVEL_T level),
return 0);
TRACE_FUNC_DECLARE(void hal_trace_get_history_buffer(const unsigned char **buf1, unsigned int *len1, \
const unsigned char **buf2, unsigned int *len2), \
{ if (buf1) { *buf1 = NULL; } if (len1) { *len1 = 0; } if (buf2) { *buf2 = NULL; } if (len2) { *len2 = 0; } });
TRACE_FUNC_DECLARE(void hal_trace_get_history_buffer(const unsigned char **buf1,
unsigned int *len1,
const unsigned char **buf2,
unsigned int *len2),
{
if (buf1) {
*buf1 = NULL;
}
if (len1) {
*len1 = 0;
}
if (buf2) {
*buf2 = NULL;
}
if (len2) {
*len2 = 0;
}
});
TRACE_FUNC_DECLARE(int hal_trace_output(const unsigned char *buf, unsigned int buf_len), return 0);
TRACE_FUNC_DECLARE(int hal_trace_output(const unsigned char *buf,
unsigned int buf_len),
return 0);
TRC_FMT_CHK(2, 3)
TRACE_FUNC_DECLARE(int hal_trace_printf(uint32_t attr, const char *fmt, ...), return 0);
TRACE_FUNC_DECLARE(int hal_trace_printf(uint32_t attr, const char *fmt, ...),
return 0);
TRACE_FUNC_DECLARE(int hal_trace_dump(const char *fmt, unsigned int size, unsigned int count, const void *buffer), return 0);
TRACE_FUNC_DECLARE(int hal_trace_dump(const char *fmt, unsigned int size,
unsigned int count, const void *buffer),
return 0);
TRACE_FUNC_DECLARE(int hal_trace_busy(void), return 0);
@ -324,24 +428,39 @@ TRACE_FUNC_DECLARE(int hal_trace_flush_buffer(void), return 0);
TRACE_FUNC_DECLARE(void hal_trace_idle_send(void), return);
TRACE_FUNC_DECLARE(int hal_trace_crash_dump_register(enum HAL_TRACE_CRASH_DUMP_MODULE_T module, HAL_TRACE_CRASH_DUMP_CB_T cb), return 0);
TRACE_FUNC_DECLARE(
int hal_trace_crash_dump_register(enum HAL_TRACE_CRASH_DUMP_MODULE_T module,
HAL_TRACE_CRASH_DUMP_CB_T cb),
return 0);
TRACE_FUNC_DECLARE(void hal_trace_app_register(HAL_TRACE_APP_NOTIFY_T notify_cb, HAL_TRACE_APP_OUTPUT_T output_cb), return);
TRACE_FUNC_DECLARE(
void hal_trace_app_register(HAL_TRACE_APP_NOTIFY_T notify_cb,
HAL_TRACE_APP_OUTPUT_T output_cb),
return);
TRACE_FUNC_DECLARE(void hal_trace_app_custom_register(HAL_TRACE_APP_NOTIFY_T notify_cb, HAL_TRACE_APP_OUTPUT_T output_cb, HAL_TRACE_APP_OUTPUT_T crash_custom_cb), return);
TRACE_FUNC_DECLARE(
void hal_trace_app_custom_register(HAL_TRACE_APP_NOTIFY_T notify_cb,
HAL_TRACE_APP_OUTPUT_T output_cb,
HAL_TRACE_APP_OUTPUT_T crash_custom_cb),
return);
TRACE_FUNC_DECLARE(void hal_trace_cp_register(HAL_TRACE_APP_NOTIFY_T notify_cb, HAL_TRACE_BUF_CTRL_T buf_cb), return);
TRACE_FUNC_DECLARE(void hal_trace_cp_register(HAL_TRACE_APP_NOTIFY_T notify_cb,
HAL_TRACE_BUF_CTRL_T buf_cb),
return);
TRACE_FUNC_DECLARE(void hal_trace_print_backtrace(uint32_t addr, uint32_t search_cnt, uint32_t print_cnt), return);
TRACE_FUNC_DECLARE(void hal_trace_print_backtrace(uint32_t addr,
uint32_t search_cnt,
uint32_t print_cnt),
return);
TRACE_FUNC_DECLARE(bool hal_trace_crash_dump_onprocess(void), return false);
TRACE_FUNC_DECLARE(uint32_t hal_trace_get_baudrate(void), return 0);
TRC_FMT_CHK(1, 2)
static inline void hal_trace_dummy(const char *fmt, ...) { }
static inline void hal_trace_dummy(const char *fmt, ...) {}
static inline void hal_dump_dummy(const char *fmt, ...) { }
static inline void hal_dump_dummy(const char *fmt, ...) {}
#if (ASSERT_FMT_ARG_IDX > 0)
TRC_FMT_CHK(ASSERT_FMT_ARG_IDX, ASSERT_FMT_ARG_IDX + 1)
@ -354,27 +473,24 @@ int hal_trace_address_executable(uint32_t addr);
int hal_trace_address_readable(uint32_t addr);
//==============================================================================
// AUDIO_DEBUG
//==============================================================================
#ifdef AUDIO_DEBUG
#define AUDIO_DEBUG_TRACE(str, ...) hal_trace_printf(str, ##__VA_ARGS__)
#define AUDIO_DEBUG_DUMP(buf, cnt) hal_trace_output(buf, cnt)
#define AUDIO_DEBUG_TRACE(str, ...) hal_trace_printf(str, ##__VA_ARGS__)
#define AUDIO_DEBUG_DUMP(buf, cnt) hal_trace_output(buf, cnt)
#endif
//==============================================================================
// INTERSYS_RAW_DATA_ONLY
//==============================================================================
#ifdef INTERSYS_RAW_DATA_ONLY
#define TRACE_RAW(str, ...) hal_trace_printf(str, ##__VA_ARGS__)
#define DUMP8_RAW(str, buf, cnt) hal_trace_dump(str, sizeof(uint8_t), cnt, buf)
#define TRACE_RAW(str, ...) hal_trace_printf(str, ##__VA_ARGS__)
#define DUMP8_RAW(str, buf, cnt) hal_trace_dump(str, sizeof(uint8_t), cnt, buf)
#endif
//==============================================================================
// TRACE RX
//==============================================================================
@ -384,21 +500,21 @@ int hal_trace_address_readable(uint32_t addr);
#define HAL_TRACE_RX_ENABLE
#endif
extern int auto_test_send(char *resp);
#define AUTO_TEST_SEND(str) auto_test_send((char*)str)
#define AUTO_TEST_SEND(str) auto_test_send((char *)str)
#endif
#include "stdio.h"
#define hal_trace_rx_parser(buf, str, ...) sscanf(buf, str, ##__VA_ARGS__)
#define hal_trace_rx_parser(buf, str, ...) sscanf(buf, str, ##__VA_ARGS__)
typedef unsigned int (*HAL_TRACE_RX_CALLBACK_T)(unsigned char *buf, unsigned int len);
typedef unsigned int (*HAL_TRACE_RX_CALLBACK_T)(unsigned char *buf,
unsigned int len);
int hal_trace_rx_register(const char *name, HAL_TRACE_RX_CALLBACK_T callback);
int hal_trace_rx_deregister(const char *name);
int hal_trace_rx_reopen();
int hal_trace_rx_open();
#ifdef __cplusplus
}
#endif

2
platform/hal/plat_addr_map.h
View File

@ -21,8 +21,6 @@ extern "C" {
#endif
#if 0
#elif defined(CHIP_FPGA1000)
#define CHIP_ID_LITERAL fpga1000
#elif defined(CHIP_BEST1000)
#define CHIP_ID_LITERAL best1000
#elif defined(CHIP_BEST1400) || defined(CHIP_BEST1402)

60
platform/main/main.cpp
View File

@ -152,32 +152,6 @@ int tgt_hardware_setup(void) {
void rom_utils_init(void);
#endif
#ifdef FPGA
uint32_t a2dp_audio_more_data(uint8_t *buf, uint32_t len);
uint32_t a2dp_audio_init(void);
extern "C" void app_audio_manager_open(void);
extern "C" void app_bt_init(void);
extern "C" uint32_t hal_iomux_init(const struct HAL_IOMUX_PIN_FUNCTION_MAP *map,
uint32_t count);
void app_overlay_open(void);
extern "C" void BesbtInit(void);
extern "C" int app_os_init(void);
extern "C" uint32_t af_open(void);
extern "C" int list_init(void);
extern "C" void app_audio_open(void);
volatile uint32_t ddddd = 0;
#if defined(AAC_TEST)
#include "app_overlay.h"
int decode_aac_frame_test(unsigned char *pcm_buffer, unsigned int pcm_len);
#define AAC_TEST_PCM_BUFF_LEN (4096)
unsigned char aac_test_pcm_buff[AAC_TEST_PCM_BUFF_LEN];
#endif
#endif
#if defined(_AUTO_TEST_)
extern int32_t at_Init(void);
#endif
@ -260,7 +234,6 @@ int main(void) {
hal_iomux_ispi_access_init();
#ifndef FPGA
uint8_t flash_id[HAL_NORFLASH_DEVICE_ID_LEN];
hal_norflash_get_id(HAL_NORFLASH_ID_0, flash_id, ARRAY_SIZE(flash_id));
TRACE(3, "FLASH_ID: %02X-%02X-%02X", flash_id[0], flash_id[1], flash_id[2]);
@ -285,7 +258,6 @@ int main(void) {
actualFlashSize);
ASSERT(false, " ");
}
#endif
pmu_open();
@ -306,36 +278,6 @@ int main(void) {
app_audio_buffer_check();
#endif
#ifdef FPGA
TRACE(0, "\n[best of best of best...]\n");
TRACE(1, "\n[ps: w4 0x%x,2]", &ddddd);
ddddd = 1;
while (ddddd == 1)
;
TRACE(0, "bt start");
list_init();
app_os_init();
app_bt_init();
a2dp_audio_init();
af_open();
app_audio_open();
app_audio_manager_open();
app_overlay_open();
#if defined(AAC_TEST)
app_overlay_select(APP_OVERLAY_A2DP_AAC);
decode_aac_frame_test(aac_test_pcm_buff, AAC_TEST_PCM_BUFF_LEN);
#endif
SAFE_PROGRAM_STOP();
#else // !FPGA
#ifdef __FACTORY_MODE_SUPPORT__
if (bootmode & HAL_SW_BOOTMODE_FACTORY) {
hal_sw_bootmode_clear(HAL_SW_BOOTMODE_FACTORY);
@ -411,7 +353,5 @@ int main(void) {
hal_cmu_sys_reboot();
}
#endif // !FPGA
return 0;
}

2
platform/main/noapp_main.cpp
View File

@ -113,7 +113,7 @@ int MAIN_ENTRY(void) {
#endif
#endif
#if !defined(SIMU) && !defined(FPGA)
#if !defined(SIMU)
uint8_t flash_id[HAL_NORFLASH_DEVICE_ID_LEN];
hal_norflash_get_id(HAL_NORFLASH_ID_0, flash_id, ARRAY_SIZE(flash_id));
TRACE(3, "FLASH_ID: %02X-%02X-%02X", flash_id[0], flash_id[1], flash_id[2]);

2
rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
View File

@ -209,7 +209,7 @@ void os_idle_demon(void) {
unsigned int start_os_time;
unsigned int start_tick;
#endif
#if defined(FPGA) || !(defined(ROM_BUILD) || defined(PROGRAMMER))
#if !(defined(ROM_BUILD) || defined(PROGRAMMER))
ret = hal_trace_crash_dump_register(HAL_TRACE_CRASH_DUMP_MODULE_SYS,
rtx_show_all_threads);
ASSERT(ret == 0, "IdleTask: Failed to register crash dump callback");

6
services/Makefile
View File

@ -58,9 +58,7 @@ endif
obj-y += nv_section/
ifneq ($(FPGA),1)
obj-y += nvrecord/
endif
ifeq ($(VOICE_RECOGNITION),1)
obj-y += voice_recognition/
@ -76,11 +74,7 @@ endif
ifeq ($(OTA_ENABLE),1)
ifeq ($(IBRT),1)
ifeq ($(FPGA_IBRT_OTA),1)
obj-y += fpga_ibrt_ota/
else
obj-y += ibrt_ota/
endif
else
endif
ifeq ($(OTA_ENABLE), 1)

15
services/app_ibrt/src/app_ibrt_nvrecord.cpp
View File

@ -186,7 +186,6 @@ int app_ibrt_nvrecord_choice_mobile_addr(bt_bdaddr_t *mobile_addr,
*****************************************************************************/
bt_status_t app_ibrt_nvrecord_get_mobile_addr(bt_bdaddr_t *mobile_addr) {
#if !defined(FPGA)
btif_device_record_t record1;
btif_device_record_t record2;
btif_device_record_t record;
@ -219,20 +218,6 @@ bt_status_t app_ibrt_nvrecord_get_mobile_addr(bt_bdaddr_t *mobile_addr) {
}
}
}
#else
#if 0 // for fpga test reconnect phone
ibrt_ctrl_t *p_ibrt_ctrl = app_tws_ibrt_get_bt_ctrl_ctx();
uint8_t nv_slave_connect_addr[] = {0xaf,0x55,0x68,0x68,0x76,0x7c};//huawei
//uint8_t nv_slave_connect_addr[] = {0x62, 0xb2, 0x60, 0x37, 0xab, 0x20};//LJH iphone
memcpy(mobile_addr, &nv_slave_connect_addr[0], BTIF_BD_ADDR_SIZE);
if (p_ibrt_ctrl->nv_role == IBRT_SLAVE)
{
return BT_STS_SUCCESS;
}
#endif
#endif
return BT_STS_FAILED;
}
/*****************************************************************************

18
services/audioflinger/audioflinger.c
View File

@ -51,19 +51,12 @@ extern void tws_playback_ticks_check_for_mix_prompt(void);
#include "floatlimiter.h"
#endif
#if defined(CHIP_BEST2001) && defined(FPGA)
#undef FPGA
#endif
#define AF_TRACE_DEBUG() // TRACE(2,"%s:%d\n", __func__, __LINE__)
//#define AF_STREAM_ID_0_PLAYBACK_FADEOUT
// #define AF_STREAM_ID_0_PLAYBACK_FADEOUT
//#define CORRECT_SAMPLE_VALUE
// #define CORRECT_SAMPLE_VALUE
#ifdef FPGA
#define AF_DEVICE_EXT_CODEC
#endif
#ifdef AUDIO_OUTPUT_DC_CALIB
#ifdef CHIP_BEST1000
#define AUDIO_OUTPUT_DC_CALIB_SW
@ -2421,9 +2414,7 @@ uint32_t af_stream_pause(enum AUD_STREAM_ID_T id, enum AUD_STREAM_T stream) {
hal_audma_stop(role->dma_cfg.ch);
#ifndef FPGA
codec_int_stream_stop(stream);
#endif
af_set_status(id, stream, AF_STATUS_STREAM_PAUSE_RESTART);
@ -2480,13 +2471,8 @@ uint32_t af_stream_restart(enum AUD_STREAM_ID_T id, enum AUD_STREAM_T stream) {
#endif
hal_audma_sg_start(&role->dma_desc[0], &role->dma_cfg);
#ifndef FPGA
codec_int_stream_start(stream);
#endif
af_clear_status(id, stream, AF_STATUS_STREAM_PAUSE_RESTART);
ret = AF_RES_SUCCESS;
_exit:

6
services/ble_app/app_main/app.c
View File

@ -137,10 +137,6 @@
#include "app_tws_ibrt.h"
#endif
#ifdef FPGA
#include "hal_timer.h"
#endif
#ifdef __GATT_OVER_BR_EDR__
#include "btgatt_api.h"
#endif
@ -301,7 +297,7 @@ enum appm_svc_list {
****************************************************************************************
*/
// gattc_msg_handler_tab
//#define KE_MSG_HANDLER_TAB(task) __STATIC const struct ke_msg_handler
// #define KE_MSG_HANDLER_TAB(task) __STATIC const struct ke_msg_handler
// task##_msg_handler_tab[] =
/// Application Task Descriptor

92
services/ble_stack/ble_ip/rwapp_config.h
View File

@ -10,7 +10,6 @@
****************************************************************************************
*/
/*
* INCLUDE FILES
****************************************************************************************
@ -22,22 +21,23 @@
*/
/******************************************************************************************/
/* ------------------------- BLE APPLICATION SETTINGS -----------------------------*/
/* ------------------------- BLE APPLICATION SETTINGS
* -----------------------------*/
/******************************************************************************************/
#define CFG_APP_DATAPATH_SERVER
#define FAST_PAIR_REV_1_0 0
#define FAST_PAIR_REV_2_0 1
#define BLE_APP_GFPS_VER FAST_PAIR_REV_2_0
#define FAST_PAIR_REV_1_0 0
#define FAST_PAIR_REV_2_0 1
#define BLE_APP_GFPS_VER FAST_PAIR_REV_2_0
#ifdef GFPS_ENABLED
#if BLE_APP_GFPS_VER==FAST_PAIR_REV_2_0
#define CFG_APP_GFPS
#ifndef CFG_APP_SEC
#define CFG_APP_SEC
#endif
#if BLE_APP_GFPS_VER == FAST_PAIR_REV_2_0
#define CFG_APP_GFPS
#ifndef CFG_APP_SEC
#define CFG_APP_SEC
#endif
#else
#undef CFG_APP_GFPS
#undef CFG_APP_GFPS
#endif
#endif
@ -88,118 +88,112 @@
#define CFG_APP_ANCC
#endif
#ifdef CHIP_FPGA1000
#ifndef CFG_APP_SEC
#define CFG_APP_SEC
#endif
#endif
/// Health Thermometer Application
#if defined(CFG_APP_HT)
#define BLE_APP_HT 1
#define BLE_APP_HT 1
#else // defined(CFG_APP_HT)
#define BLE_APP_HT 0
#define BLE_APP_HT 0
#endif // defined(CFG_APP_HT)
#if defined(CFG_APP_HR)
#define BLE_APP_HR 1
#define BLE_APP_HR 1
#else
#define BLE_APP_HR 0
#define BLE_APP_HR 0
#endif
/// Data Path Server Application
#if defined(CFG_APP_DATAPATH_SERVER)
#define BLE_APP_DATAPATH_SERVER 1
#define BLE_APP_DATAPATH_SERVER 1
#else // defined(CFG_APP_DATAPATH_SERVER)
#define BLE_APP_DATAPATH_SERVER 0
#define BLE_APP_DATAPATH_SERVER 0
#endif // defined(CFG_APP_DATAPATH_SERVER)
/// HID Application
#if defined(CFG_APP_HID)
#define BLE_APP_HID 1
#define BLE_APP_HID 1
#else // defined(CFG_APP_HID)
#define BLE_APP_HID 0
#define BLE_APP_HID 0
#endif // defined(CFG_APP_HID)
/// DIS Application
#if defined(CFG_APP_DIS)
#define BLE_APP_DIS 1
#define BLE_APP_DIS 1
#else // defined(CFG_APP_DIS)
#define BLE_APP_DIS 0
#define BLE_APP_DIS 0
#endif // defined(CFG_APP_DIS)
/// Time Application
#if defined(CFG_APP_TIME)
#define BLE_APP_TIME 1
#define BLE_APP_TIME 1
#else // defined(CFG_APP_TIME)
#define BLE_APP_TIME 0
#define BLE_APP_TIME 0
#endif // defined(CFG_APP_TIME)
/// Battery Service Application
#if (BLE_APP_HID)
#define BLE_APP_BATT 1
#define BLE_APP_BATT 1
#else
#define BLE_APP_BATT 0
#define BLE_APP_BATT 0
#endif // (BLE_APP_HID)
/// Security Application
#if (defined(CFG_APP_SEC) || BLE_APP_HID || defined(BLE_APP_AM0))
#define BLE_APP_SEC 1
#define BLE_APP_SEC 1
#else // defined(CFG_APP_SEC)
#define BLE_APP_SEC 0
#define BLE_APP_SEC 0
#endif // defined(CFG_APP_SEC)
/// Voice Path Application
#if defined(CFG_APP_VOICEPATH)
#define BLE_APP_VOICEPATH 1
#define BLE_APP_VOICEPATH 1
#else // defined(CFG_APP_VOICEPATH)
#define BLE_APP_VOICEPATH 0
#define BLE_APP_VOICEPATH 0
#endif // defined(CFG_APP_VOICEPATH)
#if defined(CFG_APP_TILE)
#define BLE_APP_TILE 1
#define BLE_APP_TILE 1
#else // defined(CFG_APP_TILE)
#define BLE_APP_TILE 0
#define BLE_APP_TILE 0
#endif // defined(CFG_APP_TILE)
/// OTA Application
#if defined(CFG_APP_OTA)
#define BLE_APP_OTA 1
#define BLE_APP_OTA 1
#else // defined(CFG_APP_OTA)
#define BLE_APP_OTA 0
#define BLE_APP_OTA 0
#endif // defined(CFG_APP_OTA)
#if defined(CFG_APP_TOTA)
#define BLE_APP_TOTA 1
#define BLE_APP_TOTA 1
#else // defined(CFG_APP_TOTA)
#define BLE_APP_TOTA 0
#define BLE_APP_TOTA 0
#endif // defined(CFG_APP_TOTA)
/// ANCC Application
#if defined(CFG_APP_ANCC)
#define BLE_APP_ANCC 1
#define BLE_APP_ANCC 1
#else // defined(CFG_APP_ANCC)
#define BLE_APP_ANCC 0
#define BLE_APP_ANCC 0
#endif // defined(CFG_APP_ANCC)
/// AMS Application
#if defined(CFG_APP_AMS)
#define BLE_APP_AMS 1
#define BLE_APP_AMS 1
#else // defined(CFG_APP_AMS)
#define BLE_APP_AMS 0
#define BLE_APP_AMS 0
#endif // defined(CFG_APP_AMS)
/// GFPS Application
#if defined(CFG_APP_GFPS)
#define BLE_APP_GFPS 1
#define BLE_APP_GFPS 1
#else // defined(CFG_APP_GFPS)
#define BLE_APP_GFPS 0
#define BLE_APP_GFPS 0
#endif // defined(CFG_APP_GFPS)
/// AMA Voice Application
#if defined(CFG_APP_AI_VOICE)
#define BLE_APP_AI_VOICE 1
#define BLE_APP_AI_VOICE 1
#else // defined(CFG_APP_AMA)
#define BLE_APP_AI_VOICE 0
#define BLE_APP_AI_VOICE 0
#endif // defined(CFG_APP_AMA)
/// @} rwapp_config

1386
services/ble_stack/ble_ip/rwip_config.h
View File

File diff suppressed because it is too large Load Diff

14
services/bt_app/app_a2dp.cpp
View File

@ -36,7 +36,7 @@
#include "nvrecord_bt.h"
#endif
#if defined(A2DP_LHDC_ON)
//#include "../liblhdc-dec/lhdcUtil.h"
// #include "../liblhdc-dec/lhdcUtil.h"
#include "lhdcUtil.h"
#endif
@ -1332,7 +1332,7 @@ extern "C" void avrcp_callback_CT(btif_avrcp_chnl_handle_t chnl,
if (app_bt_device.avrcp_control_rsp[device_id] == NULL)
btif_app_a2dp_avrcpadvancedpdu_mempool_calloc(
&app_bt_device.avrcp_control_rsp[device_id]);
//#if defined(__BQB_PROFILE_TEST__)
// #if defined(__BQB_PROFILE_TEST__)
if ((btif_get_avrcp_cmd_frame(parms)->operandLen !=
8)) // it works for BQB
{
@ -1342,7 +1342,7 @@ extern "C" void avrcp_callback_CT(btif_avrcp_chnl_handle_t chnl,
BTIF_AVCTP_RESPONSE_REJECTED, BTIF_AVRCP_ERR_INVALID_PARM);
TRACE(0, "reject invalid volume");
} else
//#endif
// #endif
btif_avrcp_set_control_rsp_cmd(
app_bt_device.avrcp_control_rsp[device_id],
btif_get_avrcp_cmd_frame(parms)->transId,
@ -1388,7 +1388,7 @@ extern "C" void avrcp_callback_CT(btif_avrcp_chnl_handle_t chnl,
status);
}
//#if defined(__BQB_PROFILE_TEST__)
// #if defined(__BQB_PROFILE_TEST__)
else if (btif_get_avrcp_cmd_frame(parms)->operands[7] ==
0xff) // it works for BQB
{
@ -1406,9 +1406,9 @@ extern "C" void avrcp_callback_CT(btif_avrcp_chnl_handle_t chnl,
channel, app_bt_device.avrcp_notify_rsp[device_id]);
TRACE(1, "AVRCP_CtInvalidVolume_Rsp,status%d", status);
}
//#endif
// #endif
}
//#endif
// #endif
break;
case BTIF_AVRCP_EVENT_ADV_NOTIFY: // 17
TRACE(3,
@ -4292,9 +4292,7 @@ void a2dp_volume_local_set(enum BT_DEVICE_ID_T id, int8_t vol) {
#if defined(NEW_NV_RECORD_ENABLED)
nv_record_btdevicevolume_set_a2dp_vol(app_bt_stream_volume_get_ptr(), vol);
#endif
#ifndef FPGA
nv_record_touch_cause_flush();
#endif
}
}

12
services/bt_app/app_a2dp_source.cpp
View File

@ -483,8 +483,7 @@ static void bt_a2dp_source_call_back(const BtEvent* event)
case BTEVENT_LINK_CONNECT_CNF:
case BTEVENT_LINK_CONNECT_IND:
SOURCE_DBLOG("CONNECT_IND/CNF evt:%d errCode:0x%0x newRole:%d activeCons:%d",event->eType, event->errCode, event->p.remDev->role, MEC(activeCons));
#if defined(__BTIF_EARPHONE__) && defined(__BTIF_AUTOPOWEROFF__) && \
!defined(FPGA)
#if defined(__BTIF_EARPHONE__) && defined(__BTIF_AUTOPOWEROFF__)
if (MEC(activeCons) == 0){
app_start_10_second_timer(APP_POWEROFF_TIMER_ID);
}else{
@ -585,8 +584,7 @@ static void bt_a2dp_source_call_back(const btif_event_t *Event) {
btif_me_get_remote_device_role(
btif_me_get_callback_event_rem_dev(Event)),
btif_me_get_activeCons());
#if defined(__BTIF_EARPHONE__) && defined(__BTIF_AUTOPOWEROFF__) && \
!defined(FPGA)
#if defined(__BTIF_EARPHONE__) && defined(__BTIF_AUTOPOWEROFF__)
if (btif_me_get_activeCons() == 0) {
app_start_10_second_timer(APP_POWEROFF_TIMER_ID);
} else {
@ -722,7 +720,7 @@ static void a2dp_source_send_sbc_packet(void) {
}
#endif
//#define BT_A2DP_SOURCE_LINEIN_BUFF_SIZE (512*5*2*2)
// #define BT_A2DP_SOURCE_LINEIN_BUFF_SIZE (512*5*2*2)
#define BT_A2DP_SOURCE_LINEIN_BUFF_SIZE (A2DP_TRANS_SIZE * 2)
#if defined(APP_LINEIN_A2DP_SOURCE)
@ -751,11 +749,7 @@ int app_a2dp_source_linein_on(bool on) {
stream_cfg.bits = AUD_BITS_16;
stream_cfg.channel_num = AUD_CHANNEL_NUM_2;
stream_cfg.sample_rate = a2dp_source.sample_rate;
#if FPGA == 0
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#else
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#endif
stream_cfg.vol = 10;
// stream_cfg.io_path = AUD_INPUT_PATH_HP_MIC;
// stream_cfg.io_path =AUD_INPUT_PATH_MAINMIC;

1020
services/bt_app/app_bt.cpp
View File

File diff suppressed because it is too large Load Diff

91
services/bt_app/app_bt_func.cpp
View File

@ -232,11 +232,9 @@ static void app_add_pending_stop_sniff_op(btif_remote_device_t *remDev) {
}
}
#ifdef FPGA
extern "C" bt_status_t
app_tws_ibrt_set_access_mode(btif_accessible_mode_t mode);
void app_start_ble_adv_for_test(void);
#endif
static inline int app_bt_mail_process(APP_BT_MAIL *mail_p) {
bt_status_t status = BT_STS_LAST_CODE;
@ -390,34 +388,6 @@ static inline int app_bt_mail_process(APP_BT_MAIL *mail_p) {
status = HS_EnableSniffMode(mail_p->param.HS_EnableSniffMode_param.Chan,
mail_p->param.HS_EnableSniffMode_param.Enable);
break;
#endif
#ifdef FPGA
case BT_Set_Access_Mode_Test:
#if defined(IBRT)
app_tws_ibrt_set_access_mode(mail_p->param.ME_SetAccessibleMode_param.mode);
#else
app_set_accessmode(mail_p->param.ME_SetAccessibleMode_param.mode);
#endif
break;
case BT_Set_Adv_Mode_Test:
#if defined(IBRT)
app_start_ble_adv_for_test();
#endif
break;
case Write_Controller_Memory_Test: {
status = btif_me_write_controller_memory(
mail_p->param.Me_writecontrollermem_param.addr,
mail_p->param.Me_writecontrollermem_param.memval,
mail_p->param.Me_writecontrollermem_param.type);
break;
}
case Read_Controller_Memory_Test: {
status = btif_me_read_controller_memory(
mail_p->param.Me_readcontrollermem_param.addr,
mail_p->param.Me_readcontrollermem_param.len,
mail_p->param.Me_readcontrollermem_param.type);
break;
}
#endif
case BT_Custom_Func_req:
if (mail_p->param.CustomFunc_param.func_ptr) {
@ -425,8 +395,8 @@ static inline int app_bt_mail_process(APP_BT_MAIL *mail_p) {
mail_p->param.CustomFunc_param.func_ptr,
mail_p->param.CustomFunc_param.param0,
mail_p->param.CustomFunc_param.param1);
((APP_BTTHREAD_REQ_CUSTOMER_CALL_CB_T)(
mail_p->param.CustomFunc_param.func_ptr))(
((APP_BTTHREAD_REQ_CUSTOMER_CALL_CB_T)(mail_p->param.CustomFunc_param
.func_ptr))(
(void *)mail_p->param.CustomFunc_param.param0,
(void *)mail_p->param.CustomFunc_param.param1);
}
@ -588,63 +558,6 @@ int app_bt_ME_SetAccessibleMode(btif_accessible_mode_t mode,
return 0;
}
#ifdef FPGA
int app_bt_ME_SetAccessibleMode_Fortest(btif_accessible_mode_t mode,
const btif_access_mode_info_t *info) {
#if defined(BLE_ONLY_ENABLED)
return 0;
#endif
APP_BT_MAIL *mail;
app_bt_mail_alloc(&mail);
mail->src_thread = (uint32_t)osThreadGetId();
mail->request_id = BT_Set_Access_Mode_Test;
mail->param.ME_SetAccessibleMode_param.mode = mode;
memcpy(&mail->param.ME_SetAccessibleMode_param.info, info,
sizeof(btif_access_mode_info_t));
app_bt_mail_send(mail);
return 0;
}
int app_bt_ME_Set_Advmode_Fortest(uint8_t en) {
APP_BT_MAIL *mail;
app_bt_mail_alloc(&mail);
mail->src_thread = (uint32_t)osThreadGetId();
mail->request_id = BT_Set_Adv_Mode_Test;
mail->param.ME_BtSetAdvMode_param.isEnable = en;
app_bt_mail_send(mail);
return 0;
}
int app_bt_ME_Write_Controller_Memory_Fortest(uint32_t addr, uint32_t val,
uint8_t type) {
APP_BT_MAIL *mail;
app_bt_mail_alloc(&mail);
mail->src_thread = (uint32_t)osThreadGetId();
mail->request_id = Write_Controller_Memory_Test;
mail->param.Me_writecontrollermem_param.addr = addr;
mail->param.Me_writecontrollermem_param.memval = val;
mail->param.Me_writecontrollermem_param.type = type;
app_bt_mail_send(mail);
return 0;
}
int app_bt_ME_Read_Controller_Memory_Fortest(uint32_t addr, uint32_t len,
uint8_t type) {
APP_BT_MAIL *mail;
app_bt_mail_alloc(&mail);
mail->src_thread = (uint32_t)osThreadGetId();
mail->request_id = Read_Controller_Memory_Test;
mail->param.Me_readcontrollermem_param.addr = addr;
mail->param.Me_readcontrollermem_param.len = len;
mail->param.Me_readcontrollermem_param.type = type;
app_bt_mail_send(mail);
return 0;
}
#endif
int app_bt_Me_SetLinkPolicy(btif_remote_device_t *remDev,
btif_link_policy_t policy) {
#if !defined(IBRT)

427
services/bt_app/app_bt_func.h
View File

@ -22,262 +22,265 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "me_api.h"
#include "a2dp_api.h"
#include "hfp_api.h"
#include "dip_api.h"
#include "hfp_api.h"
#include "me_api.h"
typedef enum _bt_fn_req {
Me_switch_sco_req = 0,
ME_SwitchRole_req = 1,
ME_SetConnectionRole_req = 2,
MeDisconnectLink_req = 3,
ME_StopSniff_req = 4,
ME_SetAccessibleMode_req = 5,
Me_SetLinkPolicy_req = 6,
CMGR_SetSniffTimer_req = 7,
CMGR_SetSniffInofToAllHandlerByRemDev_req = 8,
A2DP_OpenStream_req = 9,
A2DP_CloseStream_req = 10,
A2DP_SetMasterRole_req = 11,
HF_CreateServiceLink_req = 12,
HF_DisconnectServiceLink_req = 13,
HF_CreateAudioLink_req = 14,
HF_DisconnectAudioLink_req = 15,
HF_EnableSniffMode_req = 16,
HF_SetMasterRole_req = 17,
#if defined (__HSP_ENABLE__)
HS_CreateServiceLink_req = 18,
HS_CreateAudioLink_req = 19,
HS_DisconnectAudioLink_req = 20,
HS_EnableSniffMode_req = 21,
HS_DisconnectServiceLink_req = 22,
Me_switch_sco_req = 0,
ME_SwitchRole_req = 1,
ME_SetConnectionRole_req = 2,
MeDisconnectLink_req = 3,
ME_StopSniff_req = 4,
ME_SetAccessibleMode_req = 5,
Me_SetLinkPolicy_req = 6,
CMGR_SetSniffTimer_req = 7,
CMGR_SetSniffInofToAllHandlerByRemDev_req = 8,
A2DP_OpenStream_req = 9,
A2DP_CloseStream_req = 10,
A2DP_SetMasterRole_req = 11,
HF_CreateServiceLink_req = 12,
HF_DisconnectServiceLink_req = 13,
HF_CreateAudioLink_req = 14,
HF_DisconnectAudioLink_req = 15,
HF_EnableSniffMode_req = 16,
HF_SetMasterRole_req = 17,
#if defined(__HSP_ENABLE__)
HS_CreateServiceLink_req = 18,
HS_CreateAudioLink_req = 19,
HS_DisconnectAudioLink_req = 20,
HS_EnableSniffMode_req = 21,
HS_DisconnectServiceLink_req = 22,
#endif
BT_Control_SleepMode_req = 23,
BT_Custom_Func_req = 24,
ME_StartSniff_req = 25,
BT_Control_SleepMode_req = 23,
BT_Custom_Func_req = 24,
ME_StartSniff_req = 25,
#ifdef BTIF_DIP_DEVICE
DIP_QuryService_req = 26,
DIP_QuryService_req = 26,
#endif
A2DP_Force_OpenStream_req = 27,
HF_Force_CreateServiceLink_req = 28,
BT_Red_Ccmp_Client_Open = 29,
BT_Set_Access_Mode_Test = 30,
BT_Set_Adv_Mode_Test = 31,
Write_Controller_Memory_Test = 32,
Read_Controller_Memory_Test = 33,
}bt_fn_req;
A2DP_Force_OpenStream_req = 27,
HF_Force_CreateServiceLink_req = 28,
BT_Red_Ccmp_Client_Open = 29,
BT_Set_Access_Mode_Test = 30,
BT_Set_Adv_Mode_Test = 31,
Write_Controller_Memory_Test = 32,
Read_Controller_Memory_Test = 33,
} bt_fn_req;
typedef void (*APP_BTTHREAD_REQ_CUSTOMER_CALL_CB_T)(void *, void *);
typedef union _bt_fn_param {
// BtStatus Me_switch_sco(uint16_t scohandle)
struct {
uint16_t scohandle;
} Me_switch_sco_param;
// BtStatus Me_switch_sco(uint16_t scohandle)
struct {
uint16_t scohandle;
} Me_switch_sco_param;
// BtStatus ME_SwitchRole(btif_remote_device_t *remDev)
struct {
btif_remote_device_t* remDev;
} ME_SwitchRole_param;
// BtStatus ME_SwitchRole(btif_remote_device_t *remDev)
struct {
btif_remote_device_t *remDev;
} ME_SwitchRole_param;
//BtConnectionRole ME_SetConnectionRole(BtConnectionRole role)
struct {
btif_connection_role_t role;
} BtConnectionRole_param;
// BtConnectionRole ME_SetConnectionRole(BtConnectionRole role)
struct {
btif_connection_role_t role;
} BtConnectionRole_param;
// void MeDisconnectLink(btif_remote_device_t* remDev)
struct {
btif_remote_device_t* remDev;
} MeDisconnectLink_param;
// void MeDisconnectLink(btif_remote_device_t* remDev)
struct {
btif_remote_device_t *remDev;
} MeDisconnectLink_param;
//BtStatus ME_StopSniff(btif_remote_device_t *remDev)
struct {
btif_remote_device_t* remDev;
} ME_StopSniff_param;
// BtStatus ME_StopSniff(btif_remote_device_t *remDev)
struct {
btif_remote_device_t *remDev;
} ME_StopSniff_param;
struct {
btif_remote_device_t* remDev;
btif_sniff_info_t sniffInfo;
} ME_StartSniff_param;
struct {
btif_remote_device_t *remDev;
btif_sniff_info_t sniffInfo;
} ME_StartSniff_param;
struct {
bool isEnable;
} ME_BtControlSleepMode_param;
struct {
bool isEnable;
} ME_BtControlSleepMode_param;
struct {
bool isEnable;
} ME_BtSetAdvMode_param;
//BtStatus ME_SetAccessibleMode(btif_accessible_mode_t mode, const btif_access_mode_info_t *info)
struct {
btif_accessible_mode_t mode;
btif_access_mode_info_t info;
} ME_SetAccessibleMode_param;
struct {
bool isEnable;
} ME_BtSetAdvMode_param;
//BtStatus Me_SetLinkPolicy(btif_remote_device_t *remDev, btif_link_policy_t policy)
struct {
btif_remote_device_t *remDev;
btif_link_policy_t policy;
} Me_SetLinkPolicy_param;
// BtStatus ME_SetAccessibleMode(btif_accessible_mode_t mode, const
// btif_access_mode_info_t *info)
struct {
btif_accessible_mode_t mode;
btif_access_mode_info_t info;
} ME_SetAccessibleMode_param;
/*BtStatus CMGR_SetSniffTimer(CmgrHandler *Handler,
btif_sniff_info_t* SniffInfo,
TimeT Time)
*/
struct {
btif_cmgr_handler_t *Handler;
btif_sniff_info_t SniffInfo;
TimeT Time;
} CMGR_SetSniffTimer_param;
// BtStatus Me_SetLinkPolicy(btif_remote_device_t *remDev, btif_link_policy_t
// policy)
struct {
btif_remote_device_t *remDev;
btif_link_policy_t policy;
} Me_SetLinkPolicy_param;
/*BtStatus CMGR_SetSniffInofToAllHandlerByRemDev(btif_sniff_info_t* SniffInfo,
btif_remote_device_t *RemDev)
*/
struct {
btif_sniff_info_t SniffInfo;
btif_remote_device_t *RemDev;
} CMGR_SetSniffInofToAllHandlerByRemDev_param;
/*BtStatus CMGR_SetSniffTimer(CmgrHandler *Handler,
btif_sniff_info_t* SniffInfo,
TimeT Time)
*/
struct {
btif_cmgr_handler_t *Handler;
btif_sniff_info_t SniffInfo;
TimeT Time;
} CMGR_SetSniffTimer_param;
//BtStatus A2DP_OpenStream(a2dp_stream_t *Stream, bt_bdaddr_t *Addr)
struct {
a2dp_stream_t *Stream;
bt_bdaddr_t *Addr;
} A2DP_OpenStream_param;
/*BtStatus CMGR_SetSniffInofToAllHandlerByRemDev(btif_sniff_info_t* SniffInfo,
btif_remote_device_t
*RemDev)
*/
struct {
btif_sniff_info_t SniffInfo;
btif_remote_device_t *RemDev;
} CMGR_SetSniffInofToAllHandlerByRemDev_param;
//BtStatus A2DP_CloseStream(a2dp_stream_t *Stream);
struct {
a2dp_stream_t *Stream;
} A2DP_CloseStream_param;
// BtStatus A2DP_OpenStream(a2dp_stream_t *Stream, bt_bdaddr_t *Addr)
struct {
a2dp_stream_t *Stream;
bt_bdaddr_t *Addr;
} A2DP_OpenStream_param;
//BtStatus A2DP_SetMasterRole(a2dp_stream_t *Stream, BOOL Flag);
struct {
a2dp_stream_t *Stream;
BOOL Flag;
} A2DP_SetMasterRole_param;
// BtStatus A2DP_CloseStream(a2dp_stream_t *Stream);
struct {
a2dp_stream_t *Stream;
} A2DP_CloseStream_param;
//BtStatus HF_CreateServiceLink(HfChannel *Chan, bt_bdaddr_t *Addr)
struct {
hf_chan_handle_t Chan;
bt_bdaddr_t *Addr;
} HF_CreateServiceLink_param;
// BtStatus A2DP_SetMasterRole(a2dp_stream_t *Stream, BOOL Flag);
struct {
a2dp_stream_t *Stream;
BOOL Flag;
} A2DP_SetMasterRole_param;
//bt_status_t HF_DisconnectServiceLink(hf_chan_handle_t Chan)
struct {
hf_chan_handle_t Chan;
} HF_DisconnectServiceLink_param;
// BtStatus HF_CreateServiceLink(HfChannel *Chan, bt_bdaddr_t *Addr)
struct {
hf_chan_handle_t Chan;
bt_bdaddr_t *Addr;
} HF_CreateServiceLink_param;
//bt_status_t HF_CreateAudioLink(hf_chan_handle_t Chan)
struct {
hf_chan_handle_t Chan;
} HF_CreateAudioLink_param;
// bt_status_t HF_DisconnectServiceLink(hf_chan_handle_t Chan)
struct {
hf_chan_handle_t Chan;
} HF_DisconnectServiceLink_param;
//bt_status_t HF_DisconnectAudioLink(hf_chan_handle_t Chan)
struct {
hf_chan_handle_t Chan;
} HF_DisconnectAudioLink_param;
// bt_status_t HF_CreateAudioLink(hf_chan_handle_t Chan)
struct {
hf_chan_handle_t Chan;
} HF_CreateAudioLink_param;
//bt_status_t HF_EnableSniffMode(hf_chan_handle_t Chan, BOOL Enable)
struct {
hf_chan_handle_t Chan;
BOOL Enable;
} HF_EnableSniffMode_param;
// bt_status_t HF_DisconnectAudioLink(hf_chan_handle_t Chan)
struct {
hf_chan_handle_t Chan;
} HF_DisconnectAudioLink_param;
//bt_status_t HF_SetMasterRole(hf_chan_handle_t Chan, BOOL Flag);
struct {
hf_chan_handle_t Chan;
BOOL Flag;
} HF_SetMasterRole_param;
// bt_status_t HF_EnableSniffMode(hf_chan_handle_t Chan, BOOL Enable)
struct {
hf_chan_handle_t Chan;
BOOL Enable;
} HF_EnableSniffMode_param;
// bt_status_t HF_SetMasterRole(hf_chan_handle_t Chan, BOOL Flag);
struct {
hf_chan_handle_t Chan;
BOOL Flag;
} HF_SetMasterRole_param;
#ifdef BTIF_DIP_DEVICE
struct {
btif_remote_device_t* remDev;
btif_dip_client_t *dip_client;
} DIP_QuryService_param;
struct {
btif_remote_device_t *remDev;
btif_dip_client_t *dip_client;
} DIP_QuryService_param;
#endif
#if defined (__HSP_ENABLE__)
//bt_status_t HS_CreateServiceLink(HsChannel *Chan, bt_bdaddr_t *Addr)
struct {
HsChannel *Chan;
bt_bdaddr_t *Addr;
} HS_CreateServiceLink_param;
#if defined(__HSP_ENABLE__)
// bt_status_t HS_CreateServiceLink(HsChannel *Chan, bt_bdaddr_t *Addr)
struct {
HsChannel *Chan;
bt_bdaddr_t *Addr;
} HS_CreateServiceLink_param;
//BtStatus HS_CreateAudioLink(HsChannel *Chan)
struct {
HsChannel *Chan;
} HS_CreateAudioLink_param;
// BtStatus HS_CreateAudioLink(HsChannel *Chan)
struct {
HsChannel *Chan;
} HS_CreateAudioLink_param;
//BtStatus HS_DisconnectAudioLink(HsChannel *Chan)
struct {
HsChannel *Chan;
} HS_DisconnectAudioLink_param;
// BtStatus HS_DisconnectAudioLink(HsChannel *Chan)
struct {
HsChannel *Chan;
} HS_DisconnectAudioLink_param;
//BtStatus HS_DisconnectServiceLink(HsChannel *Chan)
struct {
HsChannel *Chan;
} HS_DisconnectServiceLink_param;
// BtStatus HS_DisconnectServiceLink(HsChannel *Chan)
struct {
HsChannel *Chan;
} HS_DisconnectServiceLink_param;
//BtStatus HS_EnableSniffMode(HsChannel *Chan, BOOL Enable)
struct {
HsChannel *Chan;
BOOL Enable;
} HS_EnableSniffMode_param;
// BtStatus HS_EnableSniffMode(HsChannel *Chan, BOOL Enable)
struct {
HsChannel *Chan;
BOOL Enable;
} HS_EnableSniffMode_param;
#endif
struct {
uint32_t func_ptr;
uint32_t param0;
uint32_t param1;
} CustomFunc_param;
struct {
uint32_t func_ptr;
uint32_t param0;
uint32_t param1;
} CustomFunc_param;
struct {
uint32_t addr;
uint32_t memval;
uint8_t type;
} Me_writecontrollermem_param;
struct {
uint32_t addr;
uint32_t memval;
uint8_t type;
} Me_writecontrollermem_param;
struct {
uint32_t addr;
uint8_t len;
uint8_t type;
} Me_readcontrollermem_param;
struct {
uint32_t addr;
uint8_t len;
uint8_t type;
} Me_readcontrollermem_param;
} bt_fn_param;
typedef struct {
uint32_t src_thread;
uint32_t request_id;
bt_fn_param param;
uint32_t src_thread;
uint32_t request_id;
bt_fn_param param;
} APP_BT_MAIL;
typedef struct
{
btif_remote_device_t *remDev;
btif_link_policy_t policy;
typedef struct {
btif_remote_device_t *remDev;
btif_link_policy_t policy;
} BT_SET_LINKPOLICY_REQ_T;
int app_bt_mail_init(void);
int app_bt_Me_switch_sco(uint16_t scohandle);
int app_bt_Me_switch_sco(uint16_t scohandle);
int app_bt_ME_SwitchRole(btif_remote_device_t* remDev);
int app_bt_ME_SwitchRole(btif_remote_device_t *remDev);
int app_bt_ME_SetConnectionRole(btif_connection_role_t role);
int app_bt_ME_SetConnectionRole(btif_connection_role_t role);
int app_bt_MeDisconnectLink(btif_remote_device_t* remDev);
int app_bt_MeDisconnectLink(btif_remote_device_t *remDev);
int app_bt_ME_StopSniff(btif_remote_device_t *remDev);
int app_bt_ME_SetAccessibleMode(btif_accessible_mode_t mode, const btif_access_mode_info_t *info);
int app_bt_ME_SetAccessibleMode(btif_accessible_mode_t mode,
const btif_access_mode_info_t *info);
int app_bt_Me_SetLinkPolicy(btif_remote_device_t *remDev, btif_link_policy_t policy);
int app_bt_Me_SetLinkPolicy(btif_remote_device_t *remDev,
btif_link_policy_t policy);
int app_bt_CMGR_SetSniffTimer(btif_cmgr_handler_t *Handler,
btif_sniff_info_t* SniffInfo,
TimeT Time);
btif_sniff_info_t *SniffInfo, TimeT Time);
int app_bt_CMGR_SetSniffInfoToAllHandlerByRemDev(btif_sniff_info_t* SniffInfo,
btif_remote_device_t *RemDev);
int app_bt_CMGR_SetSniffInfoToAllHandlerByRemDev(btif_sniff_info_t *SniffInfo,
btif_remote_device_t *RemDev);
int app_bt_A2DP_OpenStream(a2dp_stream_t *Stream, bt_bdaddr_t *Addr);
@ -298,17 +301,18 @@ int app_bt_HF_EnableSniffMode(hf_chan_handle_t Chan, BOOL Enable);
int app_bt_HF_SetMasterRole(hf_chan_handle_t Chan, BOOL Flag);
void app_bt_accessible_manager_process(const btif_event_t *Event);
void app_bt_role_manager_process(const btif_event_t* Event);
void app_bt_role_manager_process(const btif_event_t *Event);
void app_bt_sniff_manager_process(const btif_event_t *Event);
//void app_bt_golbal_handle_hook(const btif_event_t *Event);
// void app_bt_golbal_handle_hook(const btif_event_t *Event);
int app_bt_ME_ControlSleepMode(bool isEnabled);
#ifdef BTIF_DIP_DEVICE
int app_bt_dip_QuryService(btif_dip_client_t *client, btif_remote_device_t* rem);
int app_bt_dip_QuryService(btif_dip_client_t *client,
btif_remote_device_t *rem);
#endif
#if defined (__HSP_ENABLE__)
#if defined(__HSP_ENABLE__)
int app_bt_HS_CreateServiceLink(HsChannel *Chan, bt_bdaddr_t *Addr);
int app_bt_HS_CreateAudioLink(HsChannel *Chan);
@ -322,30 +326,19 @@ int app_bt_HS_EnableSniffMode(HsChannel *Chan, BOOL Enable);
#endif
bool app_is_access_mode_set_pending(void);
void app_set_pending_access_mode(void);
void app_bt_set_linkpolicy(btif_remote_device_t *remDev, btif_link_policy_t policy);
void app_bt_set_linkpolicy(btif_remote_device_t *remDev,
btif_link_policy_t policy);
void app_check_pending_stop_sniff_op(void);
BT_SET_LINKPOLICY_REQ_T* app_bt_pop_pending_set_linkpolicy(void);
BT_SET_LINKPOLICY_REQ_T *app_bt_pop_pending_set_linkpolicy(void);
void app_retry_setting_access_mode(void);
void app_set_accessmode(btif_accessible_mode_t mode);
int app_bt_start_custom_function_in_bt_thread(
uint32_t param0, uint32_t param1, uint32_t funcPtr);
int app_bt_ME_StartSniff(btif_remote_device_t *remDev, btif_sniff_info_t* sniffInfo);
#ifdef FPGA
int app_bt_ME_SetAccessibleMode_Fortest(btif_accessible_mode_t mode, const btif_access_mode_info_t *info);
int app_bt_ME_Set_Advmode_Fortest(uint8_t en);
int app_bt_ME_Write_Controller_Memory_Fortest(uint32_t addr,uint32_t val,uint8_t type);
int app_bt_ME_Read_Controller_Memory_Fortest(uint32_t addr,uint32_t len,uint8_t type);
#endif
int app_bt_start_custom_function_in_bt_thread(uint32_t param0, uint32_t param1,
uint32_t funcPtr);
int app_bt_ME_StartSniff(btif_remote_device_t *remDev,
btif_sniff_info_t *sniffInfo);
#ifdef __cplusplus
}
#endif
#endif /* __APP_BT_FUNC_H__ */

62
services/bt_app/app_bt_stream.cpp
View File

@ -13,7 +13,7 @@
* trademark and other intellectual property rights.
*
****************************************************************************/
//#include "mbed.h"
// #include "mbed.h"
#include <assert.h>
#include <stdio.h>
@ -209,7 +209,7 @@ hw_filter_codec_iir_state *hw_filter_codec_iir_st;
#include "audio_cfg.h"
//#define SCO_DMA_SNAPSHOT_DEBUG
// #define SCO_DMA_SNAPSHOT_DEBUG
extern uint8_t bt_audio_get_eq_index(AUDIO_EQ_TYPE_T audio_eq_type,
uint8_t anc_status);
@ -475,14 +475,14 @@ int app_bt_stream_trigger_checker_handler(uint32_t trigger_checker) {
extern struct BT_DEVICE_T app_bt_device;
#if defined(A2DP_LHDC_V3)
#define LHDC_AUDIO_96K_BUFF_SIZE (256 * 2 * 4 * 8)
//#define LHDC_AUDIO_96K_16BITS_BUFF_SIZE (256*2*2*8)
// #define LHDC_AUDIO_96K_16BITS_BUFF_SIZE (256*2*2*8)
#define LHDC_AUDIO_BUFF_SIZE (256 * 2 * 4 * 4)
//#define LHDC_AUDIO_16BITS_BUFF_SIZE (256*2*2*4)
// #define LHDC_AUDIO_16BITS_BUFF_SIZE (256*2*2*4)
#define LHDC_LLC_AUDIO_BUFF_SIZE (256 * 2 * 2 * 2)
#else
#define LHDC_AUDIO_BUFF_SIZE (512 * 2 * 4)
//#define LHDC_AUDIO_16BITS_BUFF_SIZE (512*2*2)
// #define LHDC_AUDIO_16BITS_BUFF_SIZE (512*2*2)
#endif
#endif
uint16_t gStreamplayer = APP_BT_STREAM_INVALID;
@ -516,7 +516,7 @@ int app_a2dp_source_linein_on(bool on);
#define LINEIN_CAPTURE_BUFFER_SIZE (LINEIN_PLAYER_BUFFER_SIZE / 2)
#elif (LINEIN_CAPTURE_CHANNEL == 2)
#define LINEIN_PLAYER_BUFFER_SIZE (1024 * LINEIN_PLAYER_CHANNEL)
//#define LINEIN_CAPTURE_BUFFER_SIZE (LINEIN_PLAYER_BUFFER_SIZE)
// #define LINEIN_CAPTURE_BUFFER_SIZE (LINEIN_PLAYER_BUFFER_SIZE)
#define LINEIN_CAPTURE_BUFFER_SIZE (1024 * 10)
#endif
@ -611,11 +611,7 @@ int app_a2dp_source_I2S_onoff(bool onoff) {
stream_cfg.sample_rate = AUD_SAMPRATE_44100;
#if 0
#if FPGA == 0
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#else
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#endif
stream_cfg.vol = 10;//stream_linein_volume;
//TRACE_AUD_STREAM_I("vol = %d",stream_linein_volume);
@ -1206,7 +1202,6 @@ FRAM_TEXT_LOC uint32_t bt_sbc_player_more_data(uint8_t *buf, uint32_t len) {
#endif
#endif
#ifndef FPGA
uint8_t codec_type = bt_sbc_player_get_codec_type();
uint32_t overlay_id = 0;
if (codec_type == BTIF_AVDTP_CODEC_TYPE_MPEG2_4_AAC) {
@ -1238,7 +1233,6 @@ FRAM_TEXT_LOC uint32_t bt_sbc_player_more_data(uint8_t *buf, uint32_t len) {
if (app_get_current_overlay() != overlay_id) {
return len;
}
#endif
#ifdef PLAYBACK_FORCE_48K
app_playback_resample_run(force48k_resample, buf, len);
@ -1246,11 +1240,9 @@ FRAM_TEXT_LOC uint32_t bt_sbc_player_more_data(uint8_t *buf, uint32_t len) {
#if (A2DP_DECODER_VER == 2)
a2dp_audio_playback_handler(buf, len);
#else
#ifndef FPGA
a2dp_audio_more_data(overlay_id, buf, len);
#endif
#endif
#endif
#ifdef __AUDIO_SPECTRUM__
audio_spectrum_run(buf, len);
@ -1293,7 +1285,7 @@ FRAM_TEXT_LOC uint32_t bt_sbc_player_more_data(uint8_t *buf, uint32_t len) {
audio_process_run(buf, len);
#if defined(IBRT) && !defined(FPGA)
#if defined(IBRT)
app_tws_ibrt_audio_analysis_audiohandler_tick();
#endif
@ -3707,13 +3699,11 @@ int bt_sbc_player(enum PLAYER_OPER_T on, enum APP_SYSFREQ_FREQ_T freq) {
#ifdef __A2DP_PLAYER_USE_BT_TRIGGER__
app_bt_stream_trigger_deinit();
#endif
#ifndef FPGA
#ifdef BT_XTAL_SYNC
bt_term_xtal_sync(false);
#ifndef BT_XTAL_SYNC_NO_RESET
bt_term_xtal_sync_default();
#endif
#endif
#endif
a2dp_audio_deinit();
#if defined(AUDIO_ANC_FB_MC) && defined(ANC_APP) && \
@ -3962,15 +3952,12 @@ int bt_sbc_player(enum PLAYER_OPER_T on, enum APP_SYSFREQ_FREQ_T freq) {
stream_cfg.sample_rate = sample_rate;
#endif
#ifdef FPGA
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#else
#ifdef PLAYBACK_USE_I2S
stream_cfg.device = AUD_STREAM_USE_I2S0_MASTER;
#else
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#endif
#endif
#ifdef PLAYBACK_USE_I2S
stream_cfg.io_path = AUD_IO_PATH_NULL;
#else
@ -5152,7 +5139,7 @@ static int32_t wnr_buf[256 * 2];
static short wnr_buf[256 * 2];
#endif
#endif
//#define BT_SCO_HANDLER_PROFILE
// #define BT_SCO_HANDLER_PROFILE
//( codec:mic-->btpcm:tx
// codec:mic
@ -6207,12 +6194,10 @@ int bt_sco_player(bool on, enum APP_SYSFREQ_FREQ_T freq) {
TRACE_AUD_STREAM_I("[SCO_PLAYER] sysfreq calc : %d\n",
hal_sys_timer_calc_cpu_freq(5, 0));
#ifndef FPGA
app_overlay_select(APP_OVERLAY_HFP);
#ifdef BT_XTAL_SYNC
bt_init_xtal_sync(BT_XTAL_SYNC_MODE_VOICE, BT_INIT_XTAL_SYNC_MIN,
BT_INIT_XTAL_SYNC_MAX, BT_INIT_XTAL_SYNC_FCAP_RANGE);
#endif
#endif
btdrv_rf_bit_offset_track_enable(true);
@ -6236,9 +6221,6 @@ int bt_sco_player(bool on, enum APP_SYSFREQ_FREQ_T freq) {
sco_cap_chan_num = (enum AUD_CHANNEL_NUM_T)SPEECH_CODEC_CAPTURE_CHANNEL_NUM;
#if defined(FPGA)
sco_cap_chan_num = AUD_CHANNEL_NUM_2;
#endif
#if defined(SPEECH_TX_AEC_CODEC_REF)
sco_cap_chan_num = (enum AUD_CHANNEL_NUM_T)(sco_cap_chan_num + 1);
@ -6306,11 +6288,7 @@ int bt_sco_player(bool on, enum APP_SYSFREQ_FREQ_T freq) {
#endif
stream_cfg.vol = stream_local_volume;
#ifdef FPGA
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#else
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#endif
stream_cfg.io_path = AUD_INPUT_PATH_MAINMIC;
stream_cfg.handler = bt_sco_codec_capture_data;
app_audio_mempool_get_buff(&bt_audio_buff, stream_cfg.data_size);
@ -6699,10 +6677,6 @@ defined(ANC_APP) && !defined(__AUDIO_RESAMPLE__)
#endif
#ifdef FPGA
app_bt_stream_volumeset(stream_local_volume);
// btdrv_set_bt_pcm_en(1);
#endif
app_bt_stream_trigger_checker_start();
TRACE_AUD_STREAM_I("[SCO_PLAYER] on");
} else {
@ -6818,14 +6792,12 @@ defined(ANC_APP) && !defined(__AUDIO_RESAMPLE__)
lis25ba_deinit();
#endif
#ifndef FPGA
#ifdef BT_XTAL_SYNC
bt_term_xtal_sync(false);
#ifndef BT_XTAL_SYNC_NO_RESET
bt_term_xtal_sync_default();
#endif
#endif
#endif
#if defined(HFP_1_6_ENABLE)
TRACE(1, "clear sco tx fifo codec:%d", bt_sco_player_code_type);
bt_drv_reg_op_sco_txfifo_reset(bt_sco_player_code_type);
@ -6983,11 +6955,7 @@ int app_play_linein_onoff(bool onoff) {
#else
stream_cfg.sample_rate = AUD_SAMPRATE_44100;
#endif
#if FPGA == 0
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#else
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#endif
stream_cfg.vol = stream_linein_volume;
TRACE_AUD_STREAM_I("[LINEIN_PLAYER] vol = %d", stream_linein_volume);
stream_cfg.io_path = AUD_OUTPUT_PATH_SPEAKER;
@ -7114,11 +7082,7 @@ int app_play_linein_onoff(bool onoff) {
#else
stream_cfg.sample_rate = AUD_SAMPRATE_44100;
#endif
#if FPGA == 0
stream_cfg.device = AUD_STREAM_USE_INT_CODEC;
#else
stream_cfg.device = AUD_STREAM_USE_EXT_CODEC;
#endif
stream_cfg.io_path = AUD_INPUT_PATH_LINEIN;
stream_cfg.channel_num = (enum AUD_CHANNEL_NUM_T)LINEIN_CAPTURE_CHANNEL;
stream_cfg.channel_map =
@ -7521,9 +7485,7 @@ void app_bt_stream_volumeup(void) {
TRACE_AUD_STREAM_I("[STRM_PLAYER][VOL][UP] hfp: %d",
btdevice_volume_p->hfp_vol);
}
#ifndef FPGA
nv_record_touch_cause_flush();
#endif
}
void app_bt_set_volume(uint16_t type, uint8_t level) {
@ -7562,9 +7524,7 @@ void app_bt_set_volume(uint16_t type, uint8_t level) {
TRACE_AUD_STREAM_I("[STRM_PLAYER][VOL] a2dp: %d",
btdevice_volume_p->a2dp_vol);
TRACE_AUD_STREAM_I("[STRM_PLAYER][VOL] hfp: %d", btdevice_volume_p->hfp_vol);
#ifndef FPGA
nv_record_touch_cause_flush();
#endif
}
void app_bt_stream_volumedown(void) {
@ -7624,9 +7584,7 @@ void app_bt_stream_volumedown(void) {
TRACE_AUD_STREAM_I("[STRM_PLAYER][VOL][DONW] hfp: %d",
btdevice_volume_p->hfp_vol);
}
#ifndef FPGA
nv_record_touch_cause_flush();
#endif
}
void app_bt_stream_volumeset_handler(int8_t vol) {
@ -7697,7 +7655,6 @@ void app_bt_stream_volume_ptr_update(uint8_t *bdAddr) {
NVRAM_ENV_STREAM_VOLUME_A2DP_VOL_DEFAULT,
NVRAM_ENV_STREAM_VOLUME_HFP_VOL_DEFAULT};
#ifndef FPGA
nvrec_btdevicerecord *record = NULL;
memset(&current_btdevice_volume, 0, sizeof(btdevice_volume));
@ -7711,7 +7668,6 @@ void app_bt_stream_volume_ptr_update(uint8_t *bdAddr) {
btdevice_volume_p->a2dp_vol, btdevice_volume_p->hfp_vol,
btdevice_volume_p);
} else
#endif
{
btdevice_volume_p = &stream_volume;
TRACE_AUD_STREAM_I("[STRM_PLAYER][VOL][UPDATE] default");

17
services/bt_app/app_hfp.cpp
View File

@ -520,7 +520,7 @@ bool app_hfp_cur_chnl_is_on_3_way_calling(void) {
return true;
}
#endif
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
static void hfp_app_status_indication(enum BT_DEVICE_ID_T chan_id,
struct hfp_context *ctx) {
#ifdef __BT_ONE_BRING_TWO__
@ -699,9 +699,7 @@ void hfp_volume_local_set(enum BT_DEVICE_ID_T id, int8_t vol) {
#if defined(NEW_NV_RECORD_ENABLED)
nv_record_btdevicevolume_set_hfp_vol(app_bt_stream_volume_get_ptr(), vol);
#endif
#ifndef FPGA
nv_record_touch_cause_flush();
#endif
}
}
@ -746,7 +744,7 @@ static void hfp_connected_ind_handler(hf_chan_handle_t chan,
TRACE(1, "::HF_EVENT_SERVICE_CONNECTED Chan_id:%d\n", chan_id_flag.id);
app_bt_device.phone_earphone_mark = 1;
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
if (ctx->state == BTIF_HF_STATE_OPEN) {
////report connected voice
app_bt_device.hf_conn_flag[chan_id_flag.id] = 1;
@ -801,7 +799,7 @@ static void hfp_disconnected_ind_handler(hf_chan_handle_t chan,
#if defined(HFP_1_6_ENABLE)
btif_hf_set_negotiated_codec(chan, BTIF_HF_SCO_CODEC_CVSD);
#endif
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
if (app_bt_device.hf_conn_flag[chan_id_flag.id]) {
////report device disconnected voice
app_bt_device.hf_conn_flag[chan_id_flag.id] = 0;
@ -951,7 +949,7 @@ static void hfp_call_ind_handler(hf_chan_handle_t chan,
#endif
}
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
hfp_app_status_indication(chan_id_flag.id, ctx);
#endif
@ -1044,7 +1042,7 @@ static void hfp_callsetup_ind_handler(hf_chan_handle_t chan,
if ((ctx->call_setup & 0x03) != 0) {
hfp_call_setup_running_on_set(1);
}
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
hfp_app_status_indication(chan_id_flag.id, ctx);
#endif
@ -1125,7 +1123,7 @@ static void hfp_callsetup_ind_handler(hf_chan_handle_t chan,
static void hfp_current_call_state_handler(hf_chan_handle_t chan,
struct hfp_context *ctx) {
TRACE(1, "::HF_EVENT_CURRENT_CALL_STATE chan_id:%d\n", chan_id_flag.id);
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
hfp_app_status_indication(chan_id_flag.id, ctx);
#endif
}
@ -1428,8 +1426,7 @@ static void hfp_audio_disconnected_handler(hf_chan_handle_t chan,
static void hfp_ring_ind_handler(hf_chan_handle_t chan,
struct hfp_context *ctx) {
#if !defined(FPGA) && defined(__BTIF_EARPHONE__) && \
defined(MEDIA_PLAYER_SUPPORT)
#if defined(__BTIF_EARPHONE__) && defined(MEDIA_PLAYER_SUPPORT)
#ifdef __BT_ONE_BRING_TWO__
enum BT_DEVICE_ID_T anotherDevice =
(BT_DEVICE_ID_1 == chan_id_flag.id) ? BT_DEVICE_ID_2 : BT_DEVICE_ID_1;

6
services/bt_app/app_hsp.cpp
View File

@ -191,7 +191,7 @@ void hsp_callback(HsChannel *Chan, HsCallbackParms *Info) {
case HS_EVENT_SERVICE_CONNECTED:
TRACE(1, "::HS_EVENT_SERVICE_CONNECTED Chan_id:%d\n", chan_id_flag.id);
app_bt_profile_connect_manager_hs(chan_id_flag.id, Chan, Info);
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
if (Chan->state == HF_STATE_OPEN) {
////report connected voice
app_bt_device.hs_conn_flag[chan_id_flag.id] = 1;
@ -258,7 +258,7 @@ void hsp_callback(HsChannel *Chan, HsCallbackParms *Info) {
app_audio_manager_sendrequest(APP_BT_STREAM_MANAGER_STOP, BT_STREAM_VOICE,
chan_id_flag.id, MAX_RECORD_NUM);
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
if (app_bt_device.hs_conn_flag[chan_id_flag.id]) {
////report device disconnected voice
app_bt_device.hs_conn_flag[chan_id_flag.id] = 0;
@ -320,7 +320,7 @@ void hsp_callback(HsChannel *Chan, HsCallbackParms *Info) {
case HS_EVENT_RING_IND:
TRACE(1, "::HS_EVENT_RING_IND chan_id:%d\n", chan_id_flag.id);
#if !defined(FPGA) && defined(__BTIF_EARPHONE__)
#if defined(__BTIF_EARPHONE__)
// if(app_bt_device.hs_audio_state[chan_id_flag.id] != HF_AUDIO_CON)
app_voice_report(APP_STATUS_INDICATION_INCOMINGCALL, chan_id_flag.id);
#endif

20
services/bt_app/app_keyhandle.cpp
View File

@ -13,7 +13,7 @@
* trademark and other intellectual property rights.
*
****************************************************************************/
//#include "mbed.h"
// #include "mbed.h"
#include "analog.h"
#include "audioflinger.h"
#include "cmsis.h"
@ -1179,9 +1179,7 @@ void bt_key_handle_func_key(enum APP_KEY_EVENT_T event)
if((app_bt_device.hfchan_call[current_device_id] == BTIF_HF_CALL_ACTIVE)&&(app_bt_device.hfchan_call[another_device_id] != BTIF_HF_CALL_ACTIVE)
&&(app_bt_device.hfchan_callSetup[another_device_id] == BTIF_HF_CALL_SETUP_IN)){//A is active, B is incoming call
TRACE(2,"HFP_KEY_DUAL_HF_HOLD_CURR_ANSWER_ANOTHER: current=%d, g_current_device_id=%d",app_bt_device.curr_hf_channel_id, current_device_id);
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
//hfp_handle_key(HFP_KEY_DUAL_HF_HOLD_CURR_ANSWER_ANOTHER); //hold and answer
//app_bt_device.curr_hf_channel_id = another_device_id;
btif_hf_answer_call(app_bt_device.hf_channel[another_device_id]);
@ -1191,9 +1189,7 @@ void bt_key_handle_func_key(enum APP_KEY_EVENT_T event)
(app_bt_device.hfchan_callSetup[current_device_id] == BTIF_HF_CALL_SETUP_IN))
{
TRACE(2,"HFP_KEY_DUAL_HF_HOLD_CURR_ANSWER_ANOTHER: current=%d, g_current_device_id=%d",app_bt_device.curr_hf_channel_id, current_device_id);
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
btif_hf_answer_call(app_bt_device.hf_channel[current_device_id]);
btif_hf_call_hold(app_bt_device.hf_channel[another_device_id], BTIF_HF_HOLD_HOLD_ACTIVE_CALLS, 0);
} else if (app_bt_device.hfchan_call[current_device_id] == BTIF_HF_CALL_ACTIVE &&
@ -1201,9 +1197,7 @@ void bt_key_handle_func_key(enum APP_KEY_EVENT_T event)
app_bt_device.hf_callheld[another_device_id] == BTIF_HF_CALL_HELD_NO_ACTIVE)
{
TRACE(0,"!!!!1switch hold call and active call\n");
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
btif_hf_call_hold(app_bt_device.hf_channel[current_device_id], BTIF_HF_HOLD_HOLD_ACTIVE_CALLS, 0);
btif_hf_call_hold(app_bt_device.hf_channel[another_device_id], BTIF_HF_HOLD_HOLD_ACTIVE_CALLS, 0);
} else if (app_bt_device.hfchan_call[another_device_id] == BTIF_HF_CALL_ACTIVE &&
@ -1211,17 +1205,13 @@ void bt_key_handle_func_key(enum APP_KEY_EVENT_T event)
app_bt_device.hf_callheld[current_device_id] == BTIF_HF_CALL_HELD_NO_ACTIVE)
{
TRACE(0,"!!!!2switch hold call and active call\n");
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
btif_hf_call_hold(app_bt_device.hf_channel[another_device_id], BTIF_HF_HOLD_HOLD_ACTIVE_CALLS, 0);
btif_hf_call_hold(app_bt_device.hf_channel[current_device_id], BTIF_HF_HOLD_HOLD_ACTIVE_CALLS, 0);
} else if((app_bt_device.hfchan_call[current_device_id] == BTIF_HF_CALL_ACTIVE)&&(app_bt_device.hfchan_call[another_device_id] == BTIF_HF_CALL_ACTIVE)
&&(app_bt_device.hfchan_callSetup[current_device_id] == BTIF_HF_CALL_SETUP_NONE)&&(app_bt_device.hfchan_callSetup[another_device_id] == BTIF_HF_CALL_SETUP_NONE)){//A is active, B is active
TRACE(2,"AB is active: current=%d, g_current_device_id=%d",app_bt_device.curr_hf_channel_id, current_device_id);
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
if (bt_get_sco_number()>1){
#ifdef __HF_KEEP_ONE_ALIVE__
bt_key_hf_channel_switch_active(current_device_id, another_device_id);
@ -1237,9 +1227,7 @@ void bt_key_handle_func_key(enum APP_KEY_EVENT_T event)
} else if((app_bt_device.hfchan_call[current_device_id] == BTIF_HF_CALL_ACTIVE)&&(app_bt_device.hfchan_call[another_device_id] == BTIF_HF_CALL_ACTIVE)
&&((app_bt_device.hfchan_callSetup[current_device_id] == BTIF_HF_CALL_SETUP_IN)||(app_bt_device.hfchan_callSetup[another_device_id] == BTIF_HF_CALL_SETUP_IN))){
TRACE(2,"AB is active and incoming call: current=%d, g_current_device_id=%d",app_bt_device.curr_hf_channel_id, current_device_id);
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
if (bt_get_sco_number()>1){
#ifdef __HF_KEEP_ONE_ALIVE__
bt_key_hf_channel_switch_active(current_device_id, another_device_id);
@ -1256,9 +1244,7 @@ void bt_key_handle_func_key(enum APP_KEY_EVENT_T event)
((app_bt_device.hfchan_call[BT_DEVICE_ID_2] == BTIF_HF_CALL_ACTIVE)&&(app_bt_device.hfchan_callSetup[BT_DEVICE_ID_1] == BTIF_HF_CALL_SETUP_NONE))){
//three call
TRACE(0,"three way call");
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
hfp_handle_key(HFP_KEY_THREEWAY_HOLD_AND_ANSWER);
#if 0
if(app_bt_device.phone_earphone_mark == 0){
@ -1283,9 +1269,7 @@ void bt_key_handle_func_key(enum APP_KEY_EVENT_T event)
(((app_bt_device.hfchan_callSetup[BT_DEVICE_ID_1] == BTIF_HF_CALL_SETUP_NONE)&&(app_bt_device.hfchan_call[BT_DEVICE_ID_1] == BTIF_HF_CALL_NONE)&&(btif_get_hf_chan_state(app_bt_device.hf_channel[BT_DEVICE_ID_2]) == BTIF_HF_STATE_CLOSED))||
//(((app_bt_device.hfchan_callSetup[BT_DEVICE_ID_1] == BTIF_HF_CALL_SETUP_NONE)&&(app_bt_device.hfchan_call[BT_DEVICE_ID_1] == BTIF_HF_CALL_NONE)&&(app_bt_device.hf_channel[BT_DEVICE_ID_2].state == BTIF_HF_STATE_CLOSED))||
((app_bt_device.hfchan_callSetup[BT_DEVICE_ID_1] == BTIF_HF_CALL_SETUP_NONE)&&(app_bt_device.hfchan_call[BT_DEVICE_ID_1] == BTIF_HF_CALL_NONE)&&(app_bt_device.hfchan_callSetup[BT_DEVICE_ID_2] == BTIF_HF_CALL_SETUP_NONE)&&(app_bt_device.hfchan_call[BT_DEVICE_ID_2] == BTIF_HF_CALL_NONE)))){
#ifndef FPGA
app_voice_report(APP_STATUS_INDICATION_WARNING, 0);
#endif
open_siri_flag = 1;
}
#endif
@ -1360,7 +1344,7 @@ void bt_key_handle_down_key(enum APP_KEY_EVENT_T event) {
break;
}
}
#else //#elif defined(__APP_KEY_FN_STYLE_B__)
#else // #elif defined(__APP_KEY_FN_STYLE_B__)
void bt_key_handle_up_key(enum APP_KEY_EVENT_T event) {
TRACE(1, "%s", __func__);
switch (event) {

2
services/bt_app/app_sec.cpp
View File

@ -31,7 +31,6 @@ void pair_handler_func(enum pair_event evt, const btif_event_t *event) {
AUTO_TEST_SEND("Pairing ok.");
#endif
#ifndef FPGA
#ifdef MEDIA_PLAYER_SUPPORT
if (btif_me_get_callback_event_err_code(event) == BTIF_BEC_NO_ERROR) {
#if defined(IBRT)
@ -41,7 +40,6 @@ void pair_handler_func(enum pair_event evt, const btif_event_t *event) {
app_voice_report(APP_STATUS_INDICATION_PAIRFAIL, 0);
}
#endif
#endif
#if defined(IBRT)
if (app_ibrt_if_is_audio_active()) {
TRACE(0, "!!!!!!!!!! flash_touch");

6
services/bt_app/besmain.cpp
View File

@ -13,7 +13,7 @@
* trademark and other intellectual property rights.
*
****************************************************************************/
//#include "mbed.h"
// #include "mbed.h"
#include "analog.h"
#include "app_bt_func.h"
#include "app_bt_stream.h"
@ -268,9 +268,7 @@ static void __set_local_dev_name(void) {
devinfo.localname = bt_get_local_name();
devinfo.ble_name = bt_get_ble_local_name();
#ifndef FPGA
nvrec_dev_localname_addr_init(&devinfo);
#endif
bt_set_local_dev_name((const unsigned char *)devinfo.localname,
strlen(devinfo.localname) + 1);
}
@ -317,9 +315,7 @@ static void stack_ready_callback(int status) {
devinfo.localname = bt_get_local_name();
devinfo.ble_name = bt_get_ble_local_name();
#ifndef FPGA
nvrec_dev_localname_addr_init(&devinfo);
#endif
bt_set_local_dev_name((const unsigned char *)devinfo.localname,
strlen(devinfo.localname) + 1);

6
services/nv_section/Makefile
View File

@ -3,8 +3,4 @@ obj-y += customparam_section/
obj-y += log_section/
obj-y += factory_section/
ifeq ($(FPGA),1)
obj-y += fpga_section/
else
obj-y += userdata_section/
endif
obj-y += userdata_section/

39
services/nv_section/fpga_section/Makefile
View File

@ -1,39 +0,0 @@
cur_dir := $(dir $(lastword $(MAKEFILE_LIST)))
obj_c := $(patsubst $(cur_dir)%,%,$(wildcard $(cur_dir)*.c))
obj_cpp := $(patsubst $(cur_dir)%,%,$(wildcard $(cur_dir)*.cpp))
obj-y := $(obj_c:.c=.o) $(obj_s:.S=.o) $(obj_cpp:.cpp=.o)
ccflags-y := \
-I$(obj)/../../nv_section/fpga_section \
-I$(obj)/../../nv_section/include \
-I$(obj)/../platform/cmsis/inc \
-Iutils/crc32 \
$(BT_IF_INCLUDES) \
-Iutils/hexdump \
-Iapps/key \
-Iservices/bt_app \
-Iplatform/drivers/ana \
-Iservices/nv_section/customparam_section \
-Iservices/ble_stack/common/api \
-Iservices/ble_stack/ble_ip \
-Iutils/heap \
-Iservices/nvrecord \
-Iservices/norflash_api \
-Iservices/nv_setion/userdata_section \
-Iplatform/drivers/norflash \
-Iplatform/hal \
-Iplatform/cmsis/inc
ccflags-y += -DAUDIO_OUTPUT_VOLUME_DEFAULT=$(AUDIO_OUTPUT_VOLUME_DEFAULT)
ifeq ($(FLASH_SUSPEND),1)
ccflags-y += -DFLASH_SUSPEND
endif
ifeq ($(TX_IQ_CAL),1)
subdir-ccflags-y += -DTX_IQ_CAL
endif

418
services/nv_section/fpga_section/nvrecord_ble.c
View File

@ -1,418 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#if defined(NEW_NV_RECORD_ENABLED)
#include "nvrecord_ble.h"
#include "besbt.h"
#include "co_math.h"
#include "hal_timer.h"
#include "hal_trace.h"
#include "nvrecord_extension.h"
#include "tgt_hardware.h"
#include <assert.h>
#include <stdbool.h>
#include <string.h>
#define ble_nv_debug
#ifdef ble_nv_debug
#define ble_trace TRACE
#else
#define ble_trace
#endif
static NV_RECORD_PAIRED_BLE_DEV_INFO_T *nvrecord_ble_p = NULL;
static uint8_t INVALID_ADDR[BTIF_BD_ADDR_SIZE] = {0x00, 0x00, 0x00,
0x00, 0x00, 0x00};
void nvrecord_rebuild_paired_ble_dev_info(
NV_RECORD_PAIRED_BLE_DEV_INFO_T *pPairedBtInfo) {
memset((uint8_t *)pPairedBtInfo, 0, sizeof(NV_RECORD_PAIRED_BLE_DEV_INFO_T));
pPairedBtInfo->saved_list_num = 0; // init saved num
uint8_t index;
// avoid ble irk collision low probability
uint32_t generatedSeed = hal_sys_timer_get();
for (uint8_t index = 0; index < sizeof(bt_addr); index++) {
generatedSeed ^=
(((uint32_t)(bt_addr[index])) << (hal_sys_timer_get() & 0xF));
}
srand(generatedSeed);
// generate a new IRK
for (index = 0; index < BLE_IRK_SIZE; index++) {
pPairedBtInfo->self_info.ble_irk[index] = (uint8_t)co_rand_word();
}
}
static bool blerec_specific_value_prepare(const BleDeviceinfo *param_rec) {
// Preparations before adding new ble record:
// 1. If not existing. Check the record count. If it's BLE_RECORD_NUM,
// move 0-(BLE_RECORD_NUM-2) right side by one slot, to discard the last
// one and leave slot 0, decrease the record number. If it's smaller than
// BLE_RECORD_NUM, move 0-(count-1) right side by one slot, leave slot 0,
// don't change the record number.
// 2. If existing already and the location is entryToFree , move
// 0-(entryToFree-1)
// right side by one slot, leave slot 0. Decrease the record number for
// adding the new one.
bool isEntryExisting = false;
uint8_t entryToFree = 0;
NV_RECORD_PAIRED_BLE_DEV_INFO_T *dest_ptr;
dest_ptr = nvrecord_ble_p;
TRACE(3, "%s start search addr %p list_num=%d", __func__, dest_ptr,
dest_ptr->saved_list_num);
if (dest_ptr->saved_list_num > 0) {
for (uint8_t i = 0; i < dest_ptr->saved_list_num; i++) {
if (0 == memcmp(dest_ptr->ble_nv[i].peer_bleAddr, param_rec->peer_bleAddr,
BLE_ADDR_SIZE)) {
ble_trace(2, "%s Find the existing entry %d", __func__, i);
DUMP8("%02x ", (uint8_t *)param_rec, sizeof(BleDeviceinfo));
DUMP8("%02x ", (uint8_t *)&dest_ptr->ble_nv[i], sizeof(BleDeviceinfo));
if (!memcmp((uint8_t *)param_rec, (uint8_t *)&dest_ptr->ble_nv[i],
sizeof(BleDeviceinfo))) {
ble_trace(
0, "The new coming BLE device info is the same as the recorded.");
return false;
}
memset(&(dest_ptr->ble_nv[i]), 0, sizeof(BleDeviceinfo));
entryToFree = i;
dest_ptr->saved_list_num--;
isEntryExisting = true;
break;
}
}
} else {
return true;
}
if (!isEntryExisting) {
if (BLE_RECORD_NUM == dest_ptr->saved_list_num) {
TRACE(0, "<=====>blerec list is full,delete the oldest and add param_rec "
"to list");
for (uint8_t k = 0; k < BLE_RECORD_NUM - 1; k++) {
memcpy(&(dest_ptr->ble_nv[BLE_RECORD_NUM - 1 - k]),
&(dest_ptr->ble_nv[BLE_RECORD_NUM - 2 - k]),
sizeof(BleDeviceinfo));
}
dest_ptr->saved_list_num--;
} else {
for (uint8_t k = 0; k < dest_ptr->saved_list_num; k++) {
memcpy(&(dest_ptr->ble_nv[dest_ptr->saved_list_num - k]),
&(dest_ptr->ble_nv[dest_ptr->saved_list_num - 1 - k]),
sizeof(BleDeviceinfo));
}
}
} else {
for (uint8_t list_updata = 0; list_updata < entryToFree; list_updata++) {
memcpy(&(dest_ptr->ble_nv[entryToFree - list_updata]),
&(dest_ptr->ble_nv[entryToFree - list_updata - 1]),
sizeof(BleDeviceinfo));
}
}
return true;
}
void nv_record_blerec_init(void) {
uint32_t lock = nv_record_pre_write_operation();
if (NULL == nvrecord_ble_p) {
nvrecord_ble_p = &(nvrecord_extension_p->ble_pair_info);
if (!memcmp(nvrecord_ble_p->self_info.ble_addr, INVALID_ADDR,
BTIF_BD_ADDR_SIZE)) {
memcpy(nvrecord_ble_p->self_info.ble_addr, bt_get_ble_local_address(),
BTIF_BD_ADDR_SIZE);
}
}
nv_record_post_write_operation(lock);
}
NV_RECORD_PAIRED_BLE_DEV_INFO_T *nv_record_blerec_get_ptr(void) {
return nvrecord_ble_p;
}
void nv_record_blerec_get_local_irk(uint8_t *pIrk) {
memcpy(pIrk, nvrecord_ble_p->self_info.ble_irk, BLE_IRK_SIZE);
}
bool nv_record_blerec_get_bd_addr_from_irk(uint8_t *pBdAddr, uint8_t *pIrk) {
if (nvrecord_ble_p->saved_list_num > 0) {
for (uint8_t index = 0; index < nvrecord_ble_p->saved_list_num; index++) {
if (!memcmp(pIrk, nvrecord_ble_p->ble_nv[index].IRK, BLE_IRK_SIZE)) {
memcpy(pBdAddr, nvrecord_ble_p->ble_nv[index].peer_bleAddr,
BLE_ADDR_SIZE);
return true;
}
}
return false;
} else {
return false;
}
}
int nv_record_blerec_add(const BleDeviceinfo *param_rec) {
int nRet = 0;
uint8_t isNeedToUpdateNv = true;
isNeedToUpdateNv = blerec_specific_value_prepare(param_rec);
if (isNeedToUpdateNv) {
uint32_t lock = nv_record_pre_write_operation();
// add device info into nv struct
memcpy(nvrecord_ble_p->ble_nv[0].peer_bleAddr, param_rec->peer_bleAddr,
BLE_ADDR_SIZE); // addr
nvrecord_ble_p->ble_nv[0].EDIV = param_rec->EDIV; // EDIV
memcpy(nvrecord_ble_p->ble_nv[0].RANDOM, param_rec->RANDOM,
BLE_ENC_RANDOM_SIZE); // RANDOM
memcpy(nvrecord_ble_p->ble_nv[0].LTK, param_rec->LTK, BLE_LTK_SIZE); // LTK
memcpy(nvrecord_ble_p->ble_nv[0].IRK, param_rec->IRK, BLE_IRK_SIZE); // IRK
nvrecord_ble_p->ble_nv[0].bonded = param_rec->bonded; // bond status
nvrecord_ble_p->saved_list_num++; // updata saved num
nv_record_post_write_operation(lock);
nv_record_update_runtime_userdata();
nv_record_execute_async_flush();
TRACE(2, "%s CURRENT BLE LIST NUM=%d", __func__,
nvrecord_ble_p->saved_list_num);
}
#ifdef ble_nv_debug
for (uint8_t k = 0; k < nvrecord_ble_p->saved_list_num; k++) {
TRACE(0, "=========================================");
TRACE(1, "Num %d BLE record:", k);
TRACE(0, "BLE addr:");
DUMP8("%02x ", (uint8_t *)nvrecord_ble_p->ble_nv[k].peer_bleAddr,
BLE_ADDR_SIZE);
TRACE(1, "NV EDIV %d and random is:", nvrecord_ble_p->ble_nv[k].EDIV);
DUMP8("%02x ", (uint8_t *)nvrecord_ble_p->ble_nv[k].RANDOM,
BLE_ENC_RANDOM_SIZE);
TRACE(0, "NV LTK:");
DUMP8("%02x ", (uint8_t *)nvrecord_ble_p->ble_nv[k].LTK, BLE_LTK_SIZE);
TRACE(0, "NV irk:");
DUMP8("%02x ", (uint8_t *)nvrecord_ble_p->ble_nv[k].IRK, BLE_IRK_SIZE);
}
#endif
return nRet;
}
uint8_t nv_record_ble_fill_irk(uint8_t *irkToFill) {
NV_RECORD_PAIRED_BLE_DEV_INFO_T *find_ptr = nvrecord_ble_p;
if ((NULL == find_ptr) || (0 == find_ptr->saved_list_num)) {
return 0;
}
if (find_ptr->saved_list_num > 0) {
for (uint8_t index = 0; index < find_ptr->saved_list_num; index++) {
memcpy(irkToFill + index * BLE_IRK_SIZE, find_ptr->ble_nv[index].IRK,
BLE_IRK_SIZE);
}
return find_ptr->saved_list_num;
} else {
return 0;
}
}
// when master send encription req,if bonded,use ltk to bonding again(skip the
// pair step)
bool nv_record_ble_record_find_ltk_through_static_bd_addr(uint8_t *pBdAddr,
uint8_t *ltk) {
NV_RECORD_PAIRED_BLE_DEV_INFO_T *find_ptr = nvrecord_ble_p;
if ((NULL == find_ptr) || (0 == find_ptr->saved_list_num)) {
TRACE(3, "%s find data failed, ptr:%x, list_num:%d", __func__,
(uint32_t)find_ptr, find_ptr->saved_list_num);
return false;
}
for (uint8_t find_index = 0; find_index < find_ptr->saved_list_num;
find_index++) {
if (!memcmp(find_ptr->ble_nv[find_index].peer_bleAddr, pBdAddr,
BLE_ADDR_SIZE)) {
ble_trace(2, "%s FIND LTK IN NV SUCCESS %p", __func__,
find_ptr->ble_nv[find_index].LTK);
memcpy(ltk, find_ptr->ble_nv[find_index].LTK, BLE_LTK_SIZE);
return true;
}
}
return false;
}
bool nv_record_ble_record_Once_a_device_has_been_bonded(void) {
NV_RECORD_PAIRED_BLE_DEV_INFO_T *find_ptr = nvrecord_ble_p;
if ((NULL == find_ptr) || (0 == find_ptr->saved_list_num)) {
return false;
}
for (uint8_t find_index = 0; find_index < find_ptr->saved_list_num;
find_index++) {
if (find_ptr->ble_nv[find_index].bonded == true) {
return true;
}
}
return false;
}
void nv_record_ble_delete_entry(uint8_t *pBdAddr) {
NV_RECORD_PAIRED_BLE_DEV_INFO_T *find_ptr = nvrecord_ble_p;
if ((NULL == find_ptr) || (0 == find_ptr->saved_list_num)) {
return;
}
int8_t indexToDelete = -1;
for (uint8_t find_index = 0; find_index < find_ptr->saved_list_num;
find_index++) {
if (!memcmp(find_ptr->ble_nv[find_index].peer_bleAddr, pBdAddr,
BLE_ADDR_SIZE)) {
indexToDelete = find_index;
break;
}
}
if (indexToDelete >= 0) {
uint32_t lock = nv_record_pre_write_operation();
uint8_t index;
for (index = indexToDelete; index < find_ptr->saved_list_num - 1; index++) {
memcpy(&(find_ptr->ble_nv[index]), &(find_ptr->ble_nv[index + 1]),
sizeof(BleDeviceinfo));
}
memset((uint8_t *)&(find_ptr->ble_nv[index]), 0, sizeof(BleDeviceinfo));
find_ptr->saved_list_num--;
nv_record_update_runtime_userdata();
nv_record_post_write_operation(lock);
}
}
#ifdef TWS_SYSTEM_ENABLED
static bool tws_use_same_ble_addr(uint8_t *peer_ble_addr) {
TRACE(1, "[%s] peer addr:", __func__);
DUMP8("%x ", peer_ble_addr, BTIF_BD_ADDR_SIZE);
NV_EXTENSION_RECORD_T *pNvExtRec = nv_record_get_extension_entry_ptr();
if (!memcmp(pNvExtRec->ble_pair_info.self_info.ble_addr, peer_ble_addr,
BTIF_BD_ADDR_SIZE)) {
return true;
}
return false;
}
void nv_record_extension_update_tws_ble_info(
NV_RECORD_PAIRED_BLE_DEV_INFO_T *info) {
ASSERT(info, "null pointer received in [%s]", __func__);
bool isNvExtentionPendingForUpdate = false;
NV_EXTENSION_RECORD_T *pNvExtRec = nv_record_get_extension_entry_ptr();
if (tws_use_same_ble_addr(info->self_info.ble_addr)) {
if (memcmp(&pNvExtRec->ble_pair_info.self_info, &info->self_info,
sizeof(BLE_BASIC_INFO_T))) {
TRACE(0, "save the peer ble info to self_info");
memcpy(&pNvExtRec->ble_pair_info.self_info, &info->self_info,
sizeof(BLE_BASIC_INFO_T));
nv_record_extension_update();
isNvExtentionPendingForUpdate = true;
}
}
if (memcmp(&pNvExtRec->tws_info.ble_info, &info->self_info,
sizeof(BLE_BASIC_INFO_T))) {
TRACE(0, "save the peer ble info to tws_info");
memcpy(&pNvExtRec->tws_info.ble_info, &info->self_info,
sizeof(BLE_BASIC_INFO_T));
nv_record_extension_update();
isNvExtentionPendingForUpdate = true;
}
if (isNvExtentionPendingForUpdate) {
nv_record_execute_async_flush();
}
TRACE(0, "peer addr:");
DUMP8("0x%02x ", pNvExtRec->tws_info.ble_info.ble_addr, BTIF_BD_ADDR_SIZE);
TRACE(0, "peer irk");
DUMP8("0x%02x ", pNvExtRec->tws_info.ble_info.ble_irk, BLE_IRK_SIZE);
}
void nv_record_tws_exchange_ble_info(void) {
TRACE(1, "[%s]+++", __func__);
return;
NV_EXTENSION_RECORD_T *pNvExtRec = nv_record_get_extension_entry_ptr();
uint8_t ble_address[6] = {0, 0, 0, 0, 0, 0};
if (tws_use_same_ble_addr(pNvExtRec->tws_info.ble_info.ble_addr)) {
TRACE(0, "tws use same ble addr");
return;
}
if (!memcmp(pNvExtRec->tws_info.ble_info.ble_addr, ble_address,
BTIF_BD_ADDR_SIZE)) {
TRACE(0, "don't have tws ble addr");
return;
}
#ifdef BLE_USE_RPA
uint8_t temp_ble_irk[BLE_IRK_SIZE];
memcpy(temp_ble_irk, pNvExtRec->ble_pair_info.self_info.ble_irk,
BLE_IRK_SIZE);
memcpy(pNvExtRec->ble_pair_info.self_info.ble_irk,
pNvExtRec->tws_info.ble_info.ble_irk, BLE_IRK_SIZE);
memcpy(pNvExtRec->tws_info.ble_info.ble_irk, temp_ble_irk, BLE_IRK_SIZE);
TRACE(0, "current local ble irk:");
DUMP8("0x%02x ", pNvExtRec->ble_pair_info.self_info.ble_irk, BLE_IRK_SIZE);
#else
uint8_t temp_ble_addr[BTIF_BD_ADDR_SIZE];
memcpy(temp_ble_addr, pNvExtRec->ble_pair_info.self_info.ble_addr,
BTIF_BD_ADDR_SIZE);
memcpy(pNvExtRec->ble_pair_info.self_info.ble_addr,
pNvExtRec->tws_info.ble_info.ble_addr, BTIF_BD_ADDR_SIZE);
memcpy(pNvExtRec->tws_info.ble_info.ble_addr, temp_ble_addr,
BTIF_BD_ADDR_SIZE);
memcpy(bt_get_ble_local_address(),
pNvExtRec->ble_pair_info.self_info.ble_addr, BTIF_BD_ADDR_SIZE);
TRACE(0, "current local ble addr:");
DUMP8("0x%02x ", pNvExtRec->ble_pair_info.self_info.ble_addr,
BTIF_BD_ADDR_SIZE);
bt_set_ble_local_address(pNvExtRec->ble_pair_info.self_info.ble_addr);
#endif
nv_record_extension_update();
TRACE(1, "[%s]---", __func__);
}
uint8_t *nv_record_tws_get_self_ble_info(void) {
TRACE(1, "[%s]+++", __func__);
NV_EXTENSION_RECORD_T *pNvExtRec = nv_record_get_extension_entry_ptr();
TRACE(0, "current local ble addr:");
DUMP8("0x%02x ", pNvExtRec->ble_pair_info.self_info.ble_addr,
BTIF_BD_ADDR_SIZE);
TRACE(1, "[%s]---", __func__);
return pNvExtRec->ble_pair_info.self_info.ble_addr;
}
#endif
#endif //#if defined(NEW_NV_RECORD_ENABLED)

49
services/nv_section/fpga_section/nvrecord_ble.h
View File

@ -1,49 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#if defined(NEW_NV_RECORD_ENABLED)
#ifndef NVRECORD_BLE_H
#define NVRECORD_BLE_H
#include "nvrecord_extension.h"
#ifdef __cplusplus
extern "C" {
#endif
int nv_record_blerec_add(const BleDeviceinfo *param_rec);
bool nv_record_ble_record_find_ltk_through_static_bd_addr(uint8_t* pBdAddr, uint8_t *ltk);
bool nv_record_ble_record_Once_a_device_has_been_bonded(void);
void nv_record_ble_delete_entry(uint8_t* pBdAddr);
uint8_t nv_record_ble_fill_irk(uint8_t* ltkToFill);
void nv_record_blerec_init(void);
NV_RECORD_PAIRED_BLE_DEV_INFO_T* nv_record_blerec_get_ptr(void);
void nv_record_blerec_get_local_irk(uint8_t* pIrk);
bool nv_record_blerec_get_bd_addr_from_irk(uint8_t* pBdAddr, uint8_t* pIrk);
void nvrecord_rebuild_paired_ble_dev_info(NV_RECORD_PAIRED_BLE_DEV_INFO_T* pPairedBtInfo);
#ifdef TWS_SYSTEM_ENABLED
void nv_record_extension_update_tws_ble_info(NV_RECORD_PAIRED_BLE_DEV_INFO_T *info);
void nv_record_tws_exchange_ble_info(void);
uint8_t *nv_record_tws_get_self_ble_info(void);
#endif
#ifdef __cplusplus
}
#endif
#endif
#endif // #if defined(NEW_NV_RECORD_ENABLED)

416
services/nv_section/fpga_section/nvrecord_bt.c
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@ -1,416 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#if defined(NEW_NV_RECORD_ENABLED)
#include "nvrecord_bt.h"
#include "hal_trace.h"
#include "nvrecord_extension.h"
#include <assert.h>
#include <stdbool.h>
#include <string.h>
nvrec_btdevicerecord g_fpga_ram_record;
void ram_record_ddbrec_init(void) { g_fpga_ram_record.record.trusted = false; }
bt_status_t ram_record_ddbrec_find(const bt_bdaddr_t *bd_ddr,
nvrec_btdevicerecord **record) {
if (g_fpga_ram_record.record.trusted &&
!memcmp(&g_fpga_ram_record.record.bdAddr.address[0], &bd_ddr->address[0],
6)) {
*record = &g_fpga_ram_record;
return BT_STS_SUCCESS;
} else {
return BT_STS_FAILED;
}
}
bt_status_t ram_record_ddbrec_add(const nvrec_btdevicerecord *param_rec) {
g_fpga_ram_record = *param_rec;
g_fpga_ram_record.record.trusted = true;
return BT_STS_SUCCESS;
}
bt_status_t ram_record_ddbrec_delete(const bt_bdaddr_t *bdaddr) {
if (g_fpga_ram_record.record.trusted &&
!memcmp(&g_fpga_ram_record.record.bdAddr.address[0], &bdaddr->address[0],
6)) {
g_fpga_ram_record.record.trusted = false;
}
return BT_STS_SUCCESS;
}
void nvrecord_rebuild_paired_bt_dev_info(
NV_RECORD_PAIRED_BT_DEV_INFO_T *pPairedBtInfo) {
memset((uint8_t *)pPairedBtInfo, 0, sizeof(NV_RECORD_PAIRED_BT_DEV_INFO_T));
pPairedBtInfo->pairedDevNum = 0;
}
void nv_record_btdevicerecord_set_a2dp_profile_active_state(
btdevice_profile *device_plf, bool isActive) {
device_plf->hsp_act = isActive;
}
void nv_record_btdevicerecord_set_hfp_profile_active_state(
btdevice_profile *device_plf, bool isActive) {
device_plf->hsp_act = isActive;
}
void nv_record_btdevicerecord_set_hsp_profile_active_state(
btdevice_profile *device_plf, bool isActive) {
device_plf->hsp_act = isActive;
}
void nv_record_btdevicerecord_set_a2dp_profile_codec(
btdevice_profile *device_plf, uint8_t a2dpCodec) {
device_plf->a2dp_codectype = a2dpCodec;
}
int nv_record_get_paired_dev_count(void) {
if (NULL == nvrecord_extension_p) {
return 0;
}
return nvrecord_extension_p->bt_pair_info.pairedDevNum;
}
/*
return:
-1: enum dev failure.
0: without paired dev.
1: only 1 paired dev,store@record1.
2: get 2 paired dev.notice:record1 is the latest record.
*/
int nv_record_enum_latest_two_paired_dev(btif_device_record_t *record1,
btif_device_record_t *record2) {
if ((NULL == record1) || (NULL == record2) ||
(NULL == nvrecord_extension_p)) {
return -1;
}
if (nvrecord_extension_p->bt_pair_info.pairedDevNum > 0) {
if (1 == nvrecord_extension_p->bt_pair_info.pairedDevNum) {
memcpy(
(uint8_t *)record1,
(uint8_t *)&(nvrecord_extension_p->bt_pair_info.pairedBtDevInfo[0]),
sizeof(btif_device_record_t));
return 1;
} else {
memcpy(
(uint8_t *)record1,
(uint8_t *)&(nvrecord_extension_p->bt_pair_info.pairedBtDevInfo[0]),
sizeof(btif_device_record_t));
memcpy(
(uint8_t *)record2,
(uint8_t *)&(nvrecord_extension_p->bt_pair_info.pairedBtDevInfo[1]),
sizeof(btif_device_record_t));
return 2;
}
} else {
return 0;
}
}
static void nv_record_print_dev_record(const btif_device_record_t *record) {}
void nv_record_all_ddbrec_print(void) {
if (NULL == nvrecord_extension_p) {
TRACE(0, "No BT paired dev.");
return;
}
if (nvrecord_extension_p->bt_pair_info.pairedDevNum > 0) {
for (uint8_t tmp_i = 0;
tmp_i < nvrecord_extension_p->bt_pair_info.pairedDevNum; tmp_i++) {
btif_device_record_t record;
bt_status_t ret_status;
ret_status = nv_record_enum_dev_records(tmp_i, &record);
if (BT_STS_SUCCESS == ret_status) {
nv_record_print_dev_record(&record);
}
}
} else {
TRACE(0, "No BT paired dev.");
}
}
/*
this function should be surrounded by OS_LockStack and OS_UnlockStack when call.
*/
bt_status_t nv_record_enum_dev_records(unsigned short index,
btif_device_record_t *record) {
btif_device_record_t *recaddr = NULL;
if ((index >= nvrecord_extension_p->bt_pair_info.pairedDevNum) ||
(NULL == nvrecord_extension_p)) {
return BT_STS_FAILED;
}
recaddr = (btif_device_record_t *)&(
nvrecord_extension_p->bt_pair_info.pairedBtDevInfo[index].record);
memcpy(record, recaddr, sizeof(btif_device_record_t));
nv_record_print_dev_record(record);
return BT_STS_SUCCESS;
}
static int8_t nv_record_get_bt_pairing_info_index(const uint8_t *btAddr) {
NV_RECORD_PAIRED_BT_DEV_INFO_T *pBtDevInfo =
(NV_RECORD_PAIRED_BT_DEV_INFO_T *)(&(nvrecord_extension_p->bt_pair_info));
for (uint8_t index = 0; index < pBtDevInfo->pairedDevNum; index++) {
if (!memcmp(pBtDevInfo->pairedBtDevInfo[index].record.bdAddr.address,
btAddr, BTIF_BD_ADDR_SIZE)) {
return (int8_t)index;
}
}
return -1;
}
/**********************************************
this function should be surrounded by OS_LockStack and OS_UnlockStack when call.
**********************************************/
static bt_status_t POSSIBLY_UNUSED
nv_record_ddbrec_add(const btif_device_record_t *param_rec) {
if ((NULL == param_rec) || (NULL == nvrecord_extension_p)) {
return BT_STS_FAILED;
}
uint32_t lock = nv_record_pre_write_operation();
bool isFlushNv = false;
// try to find the entry
int8_t indexOfEntry = -1;
NV_RECORD_PAIRED_BT_DEV_INFO_T *pBtDevInfo =
(NV_RECORD_PAIRED_BT_DEV_INFO_T *)(&(nvrecord_extension_p->bt_pair_info));
indexOfEntry = nv_record_get_bt_pairing_info_index(param_rec->bdAddr.address);
if (-1 == indexOfEntry) {
// don't exist, need to add to the head of the entry list
if (MAX_BT_PAIRED_DEVICE_COUNT == pBtDevInfo->pairedDevNum) {
for (uint8_t k = 0; k < MAX_BT_PAIRED_DEVICE_COUNT - 1; k++) {
memcpy((uint8_t *)&(
pBtDevInfo
->pairedBtDevInfo[MAX_BT_PAIRED_DEVICE_COUNT - 1 - k]),
(uint8_t *)&(
pBtDevInfo
->pairedBtDevInfo[MAX_BT_PAIRED_DEVICE_COUNT - 2 - k]),
sizeof(nvrec_btdevicerecord));
}
pBtDevInfo->pairedDevNum--;
} else {
for (uint8_t k = 0; k < pBtDevInfo->pairedDevNum; k++) {
memcpy(
(uint8_t *)&(
pBtDevInfo->pairedBtDevInfo[pBtDevInfo->pairedDevNum - k]),
(uint8_t *)&(
pBtDevInfo->pairedBtDevInfo[pBtDevInfo->pairedDevNum - 1 - k]),
sizeof(nvrec_btdevicerecord));
}
}
// fill the default value
nvrec_btdevicerecord *nvrec_pool_record = &(pBtDevInfo->pairedBtDevInfo[0]);
memcpy((uint8_t *)&(nvrec_pool_record->record), (uint8_t *)param_rec,
sizeof(btif_device_record_t));
nvrec_pool_record->device_vol.a2dp_vol =
NVRAM_ENV_STREAM_VOLUME_A2DP_VOL_DEFAULT;
nvrec_pool_record->device_vol.hfp_vol =
NVRAM_ENV_STREAM_VOLUME_HFP_VOL_DEFAULT;
nvrec_pool_record->device_plf.hfp_act = false;
nvrec_pool_record->device_plf.hsp_act = false;
nvrec_pool_record->device_plf.a2dp_act = false;
#ifdef BTIF_DIP_DEVICE
nvrec_pool_record->vend_id = 0;
nvrec_pool_record->vend_id_source = 0;
#endif
pBtDevInfo->pairedDevNum++;
// need to flush the nv record
isFlushNv = true;
} else {
// exist
// check whether it's already at the head
// if not, move it to the head
if (indexOfEntry > 0) {
nvrec_btdevicerecord record;
memcpy((uint8_t *)&record,
(uint8_t *)&(pBtDevInfo->pairedBtDevInfo[indexOfEntry]),
sizeof(record));
// if not, move it to the head
for (uint8_t k = 0; k < indexOfEntry; k++) {
memcpy((uint8_t *)&(pBtDevInfo->pairedBtDevInfo[indexOfEntry - k]),
(uint8_t *)&(pBtDevInfo->pairedBtDevInfo[indexOfEntry - 1 - k]),
sizeof(nvrec_btdevicerecord));
}
memcpy((uint8_t *)&(pBtDevInfo->pairedBtDevInfo[0]), (uint8_t *)&record,
sizeof(record));
// update the link info
memcpy((uint8_t *)&(pBtDevInfo->pairedBtDevInfo[0].record),
(uint8_t *)param_rec, sizeof(btif_device_record_t));
// need to flush the nv record
isFlushNv = true;
}
// else, check whether the link info needs to be updated
else {
if (memcmp((uint8_t *)&(pBtDevInfo->pairedBtDevInfo[0].record),
(uint8_t *)param_rec, sizeof(btif_device_record_t))) {
// update the link info
memcpy((uint8_t *)&(pBtDevInfo->pairedBtDevInfo[0].record),
(uint8_t *)param_rec, sizeof(btif_device_record_t));
// need to flush the nv record
isFlushNv = true;
}
}
}
TRACE(1, "paired Bt dev:%d", pBtDevInfo->pairedDevNum);
TRACE(1, "Is to flush nv: %d", isFlushNv);
nv_record_all_ddbrec_print();
if (isFlushNv) {
nv_record_update_runtime_userdata();
}
nv_record_post_write_operation(lock);
return BT_STS_SUCCESS;
}
/*
this function should be surrounded by OS_LockStack and OS_UnlockStack when call.
*/
bt_status_t nv_record_add(SECTIONS_ADP_ENUM type, void *record) {
bt_status_t retstatus = BT_STS_FAILED;
if ((NULL == record) || (section_none == type)) {
return BT_STS_FAILED;
}
switch (type) {
case section_usrdata_ddbrecord:
retstatus = ram_record_ddbrec_add(record);
break;
default:
break;
}
return retstatus;
}
/*
this function should be surrounded by OS_LockStack and OS_UnlockStack when call.
*/
bt_status_t nv_record_ddbrec_find(const bt_bdaddr_t *bd_ddr,
btif_device_record_t *record) {
if ((NULL == bd_ddr) || (NULL == record) || (NULL == nvrecord_extension_p)) {
return BT_STS_FAILED;
}
int8_t indexOfEntry = -1;
NV_RECORD_PAIRED_BT_DEV_INFO_T *pBtDevInfo =
(NV_RECORD_PAIRED_BT_DEV_INFO_T *)(&(nvrecord_extension_p->bt_pair_info));
indexOfEntry = nv_record_get_bt_pairing_info_index(bd_ddr->address);
if (-1 == indexOfEntry) {
return BT_STS_FAILED;
} else {
memcpy((uint8_t *)record,
(uint8_t *)&(pBtDevInfo->pairedBtDevInfo[indexOfEntry].record),
sizeof(btif_device_record_t));
return BT_STS_SUCCESS;
}
}
/*
this function should be surrounded by OS_LockStack and OS_UnlockStack when call.
*/
bt_status_t nv_record_ddbrec_delete(const bt_bdaddr_t *bdaddr) {
ram_record_ddbrec_delete(bdaddr);
return BT_STS_SUCCESS;
}
int nv_record_btdevicerecord_find(const bt_bdaddr_t *bd_ddr,
nvrec_btdevicerecord **record) {
ram_record_ddbrec_find(bd_ddr, record);
return 0;
}
void nv_record_btdevicerecord_set_a2dp_vol(nvrec_btdevicerecord *pRecord,
int8_t vol) {
uint32_t lock = nv_record_pre_write_operation();
if (vol != pRecord->device_vol.a2dp_vol) {
nv_record_update_runtime_userdata();
pRecord->device_vol.a2dp_vol = vol;
}
nv_record_post_write_operation(lock);
}
void nv_record_btdevicerecord_set_hfp_vol(nvrec_btdevicerecord *pRecord,
int8_t vol) {
uint32_t lock = nv_record_pre_write_operation();
if (vol != pRecord->device_vol.hfp_vol) {
nv_record_update_runtime_userdata();
pRecord->device_vol.hfp_vol = vol;
}
nv_record_post_write_operation(lock);
}
void nv_record_btdevicevolume_set_a2dp_vol(btdevice_volume *device_vol,
int8_t vol) {
uint32_t lock = nv_record_pre_write_operation();
if (vol != device_vol->a2dp_vol) {
nv_record_update_runtime_userdata();
device_vol->a2dp_vol = vol;
}
nv_record_post_write_operation(lock);
}
void nv_record_btdevicevolume_set_hfp_vol(btdevice_volume *device_vol,
int8_t vol) {
uint32_t lock = nv_record_pre_write_operation();
if (vol != device_vol->hfp_vol) {
nv_record_update_runtime_userdata();
device_vol->hfp_vol = vol;
}
nv_record_post_write_operation(lock);
}
void nv_record_btdevicerecord_set_vend_id_and_source(
nvrec_btdevicerecord *pRecord, int16_t vend_id, int16_t vend_id_source) {
#ifdef BTIF_DIP_DEVICE
TRACE(2, "%s vend id 0x%x", __func__, vend_id);
uint32_t lock = nv_record_pre_write_operation();
if (vend_id != pRecord->vend_id) {
nv_record_update_runtime_userdata();
pRecord->vend_id = vend_id;
pRecord->vend_id_source = vend_id_source;
}
nv_record_post_write_operation(lock);
#endif
}
#endif //#if defined(NEW_NV_RECORD_ENABLED)

58
services/nv_section/fpga_section/nvrecord_bt.h
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@ -1,58 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#if defined(NEW_NV_RECORD_ENABLED)
#ifndef NVRECORD_BT_H
#define NVRECORD_BT_H
#include "nvrecord_extension.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NVRAM_ENV_STREAM_VOLUME_A2DP_VOL_DEFAULT (AUDIO_OUTPUT_VOLUME_DEFAULT)
#define NVRAM_ENV_STREAM_VOLUME_HFP_VOL_DEFAULT (AUDIO_OUTPUT_VOLUME_DEFAULT)
void nv_record_btdevicerecord_set_a2dp_vol(nvrec_btdevicerecord* pRecord, int8_t vol);
void nv_record_btdevicerecord_set_hfp_vol(nvrec_btdevicerecord* pRecord, int8_t vol);
void nv_record_btdevicevolume_set_a2dp_vol(btdevice_volume* device_vol, int8_t vol);
void nv_record_btdevicevolume_set_hfp_vol(btdevice_volume* device_vol, int8_t vol);
void nv_record_btdevicerecord_set_vend_id_and_source(nvrec_btdevicerecord* pRecord, int16_t vend_id, int16_t vend_id_source);
void nv_record_btdevicerecord_set_a2dp_profile_active_state(btdevice_profile* device_plf, bool isActive);
void nv_record_btdevicerecord_set_hfp_profile_active_state(btdevice_profile* device_plf, bool isActive);
void nv_record_btdevicerecord_set_hsp_profile_active_state(btdevice_profile* device_plf, bool isActive);
int nv_record_enum_latest_two_paired_dev(btif_device_record_t* record1,btif_device_record_t* record2);
void nv_record_all_ddbrec_print(void);
void nv_record_update_runtime_userdata(void);
void nvrecord_rebuild_paired_bt_dev_info(NV_RECORD_PAIRED_BT_DEV_INFO_T* pPairedBtInfo);
int nv_record_btdevicerecord_find(const bt_bdaddr_t *bd_ddr, nvrec_btdevicerecord **record);
void nv_record_btdevicerecord_set_a2dp_profile_codec(btdevice_profile* device_plf, uint8_t a2dpCodec);
bt_status_t nv_record_ddbrec_delete(const bt_bdaddr_t *bdaddr);
bt_status_t nv_record_enum_dev_records(unsigned short index,btif_device_record_t* record);
bt_status_t nv_record_ddbrec_find(const bt_bdaddr_t *bd_ddr, btif_device_record_t*record);
bt_status_t nv_record_add(SECTIONS_ADP_ENUM type,void *record);
int nv_record_get_paired_dev_count(void);
void ram_record_ddbrec_init(void);
bt_status_t ram_record_ddbrec_find(const bt_bdaddr_t* bd_ddr, nvrec_btdevicerecord **record);
bt_status_t ram_record_ddbrec_add(const nvrec_btdevicerecord* param_rec);
bt_status_t ram_record_ddbrec_delete(const bt_bdaddr_t *bdaddr);
#ifdef __cplusplus
}
#endif
#endif
#endif // #if defined(NEW_NV_RECORD_ENABLED)

99
services/nv_section/fpga_section/nvrecord_env.c
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@ -1,99 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#if defined(NEW_NV_RECORD_ENABLED)
#include "nvrecord_env.h"
#include "hal_trace.h"
#include "nvrecord_extension.h"
#include <assert.h>
#include <stdbool.h>
#include <string.h>
static struct nvrecord_env_t localSystemInfo;
void nvrecord_rebuild_system_env(struct nvrecord_env_t *pSystemEnv) {
memset((uint8_t *)pSystemEnv, 0, sizeof(struct nvrecord_env_t));
pSystemEnv->media_language.language = NVRAM_ENV_MEDIA_LANGUAGE_DEFAULT;
pSystemEnv->ibrt_mode.mode = NVRAM_ENV_TWS_MODE_DEFAULT;
pSystemEnv->ibrt_mode.tws_connect_success = 0;
pSystemEnv->factory_tester_status.status =
NVRAM_ENV_FACTORY_TESTER_STATUS_DEFAULT;
pSystemEnv->voice_key_enable = false;
pSystemEnv->aiManagerInfo.setedCurrentAi = 0;
pSystemEnv->aiManagerInfo.aiStatusDisableFlag = 0;
pSystemEnv->aiManagerInfo.amaAssistantEnableStatus = 1;
localSystemInfo = *pSystemEnv;
}
int nv_record_env_get(struct nvrecord_env_t **nvrecord_env) {
if (NULL == nvrecord_env) {
return -1;
}
localSystemInfo.ibrt_mode.tws_connect_success = true;
*nvrecord_env = &localSystemInfo;
return 0;
}
int nv_record_env_set(struct nvrecord_env_t *nvrecord_env) {
if (NULL == nvrecord_extension_p) {
return -1;
}
uint32_t lock = nv_record_pre_write_operation();
nvrecord_extension_p->system_info = *nvrecord_env;
nv_record_update_runtime_userdata();
nv_record_post_write_operation(lock);
return 0;
}
void nv_record_update_ibrt_info(uint32_t newMode, bt_bdaddr_t *ibrtPeerAddr) {
if (NULL == nvrecord_extension_p) {
return;
}
uint32_t lock = nv_record_pre_write_operation();
TRACE(2, "##%s,%d", __func__, newMode);
nvrecord_extension_p->system_info.ibrt_mode.mode = newMode;
memcpy(nvrecord_extension_p->system_info.ibrt_mode.record.bdAddr.address,
ibrtPeerAddr->address, BTIF_BD_ADDR_SIZE);
nv_record_update_runtime_userdata();
nv_record_post_write_operation(lock);
}
void nv_record_update_factory_tester_status(uint32_t status) {
if (NULL == nvrecord_extension_p) {
return;
}
uint32_t lock = nv_record_pre_write_operation();
nvrecord_extension_p->system_info.factory_tester_status.status = status;
nv_record_update_runtime_userdata();
nv_record_post_write_operation(lock);
}
int nv_record_env_init(void) {
nv_record_open(section_usrdata_ddbrecord);
return 0;
}
#endif // #if defined(NEW_NV_RECORD_ENABLED)

45
services/nv_section/fpga_section/nvrecord_env.h
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@ -1,45 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#if defined(NEW_NV_RECORD_ENABLED)
#ifndef NVRECORD_ENV_H
#define NVRECORD_ENV_H
#ifdef __cplusplus
extern "C" {
#endif
#include "me_api.h"
#include "nvrecord_extension.h"
#define NVRAM_ENV_MEDIA_LANGUAGE_DEFAULT (0)
#define NVRAM_ENV_TWS_MODE_DEFAULT (0xff)
#define NVRAM_ENV_FACTORY_TESTER_STATUS_DEFAULT (0xaabbccdd)
#define NVRAM_ENV_FACTORY_TESTER_STATUS_TEST_PASS (0xffffaa55)
int nv_record_env_init(void);
int nv_record_env_get(struct nvrecord_env_t **nvrecord_env);
int nv_record_env_set(struct nvrecord_env_t *nvrecord_env);
void nv_record_update_ibrt_info(uint32_t newMode,bt_bdaddr_t *ibrtPeerAddr);
void nvrecord_rebuild_system_env(struct nvrecord_env_t* pSystemEnv);
void nv_record_update_factory_tester_status(uint32_t status);
#ifdef __cplusplus
}
#endif
#endif
#endif // #if defined(NEW_NV_RECORD_ENABLED)

481
services/nv_section/fpga_section/nvrecord_externsion.c
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@ -1,481 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#ifdef NEW_NV_RECORD_ENABLED
#include "besbt.h"
#include "cmsis.h"
#include "crc32.h"
#include "customparam_section.h"
#include "hal_norflash.h"
#include "hal_trace.h"
#include "mpu.h"
#include "norflash_api.h"
#include "norflash_drv.h"
#include "nvrecord_ble.h"
#include "nvrecord_bt.h"
#include "nvrecord_dma_config.h"
#include "nvrecord_env.h"
#include "nvrecord_extension.h"
#include "nvrecord_fp_account_key.h"
#include <assert.h>
#include <stdbool.h>
#include <string.h>
extern uint32_t __userdata_start[];
extern uint32_t __userdata_end[];
extern void nvrecord_rebuild_system_env(struct nvrecord_env_t *pSystemEnv);
extern void nvrecord_rebuild_paired_bt_dev_info(
NV_RECORD_PAIRED_BT_DEV_INFO_T *pPairedBtInfo);
#ifdef GFPS_ENABLED
extern void
nvrecord_rebuild_fp_account_key(NV_FP_ACCOUNT_KEY_RECORD_T *pFpAccountKey);
#endif
#ifdef NVREC_BAIDU_DATA_SECTION
extern void
nvrecord_rebuild_dma_configuration(NV_DMA_CONFIGURATION_T *pDmaConfig);
#endif
typedef enum {
NV_STATE_IDLE,
NV_STATE_ERASED,
} NV_STATE;
NV_EXTENSION_RECORD_T *nvrecord_extension_p = NULL;
static uint8_t isNvExtentionPendingForUpdate = false;
static NV_STATE isNvExtentionState = NV_STATE_IDLE;
/*
*Note: the NV_EXTENSION_MIRROR_RAM_SIZE must be power of 2
*/
#if defined(__ARM_ARCH_8M_MAIN__)
#define __NV_BUF_MPU_ALIGNED __ALIGNED(0x20)
#else
/*
* armv7 mpu require the address must be aligned to the section size and
* the section size must be algined to power of 2
*/
#define __NV_BUF_MPU_ALIGNED __ALIGNED(NV_EXTENSION_MIRROR_RAM_SIZE)
#endif
static NV_MIRROR_BUF_T local_extension_data __NV_BUF_MPU_ALIGNED __attribute__((
section(".sram_data"))) = {
.nv_record = {
{
// header
NV_EXTENSION_MAGIC_NUMBER,
NV_EXTENSION_MAJOR_VERSION,
NV_EXTENSION_MINOR_VERSION,
NV_EXTENSION_VALID_LEN,
0,
},
{
// system info
},
{// bt_pair_info
0},
{
// ble_pair_info
},
#ifdef TWS_SYSTEM_ENABLED
{
// tws_info
},
#endif
#ifdef GFPS_ENABLED
{// fp_account_key_rec
0},
#endif
#ifdef NVREC_BAIDU_DATA_SECTION
{
// dma_config
BAIDU_DATA_DEF_FM_FREQ,
},
#endif
#ifdef TILE_DATAPATH
{{0}},
#endif
#if defined(BISTO_ENABLED)
{
true,
GSOUND_OTA_STATUS_NONE,
0,
0,
},
#endif
#ifdef TX_IQ_CAL
{
BT_IQ_INVALID_MAGIC_NUM,
{0},
{0},
},
#endif
// TODO:
// If want to extend the nvrecord while keeping the history information,
// append the new items to the tail of NV_EXTENSION_RECORD_T and
// set their intial content here
}};
STATIC_ASSERT(sizeof(local_extension_data) <= NV_EXTENSION_MIRROR_RAM_SIZE,
"NV local buffer too small");
static void _nv_record_extension_init(void) {
enum NORFLASH_API_RET_T result;
uint32_t sector_size = 0;
uint32_t block_size = 0;
uint32_t page_size = 0;
hal_norflash_get_size(HAL_NORFLASH_ID_0, NULL, &block_size, &sector_size,
&page_size);
result = norflash_api_register(
NORFLASH_API_MODULE_ID_USERDATA_EXT, HAL_NORFLASH_ID_0,
((uint32_t)__userdata_start),
((uint32_t)__userdata_end - (uint32_t)__userdata_start), block_size,
sector_size, page_size, NV_EXTENSION_SIZE * 2, nv_extension_callback);
ASSERT(result == NORFLASH_API_OK,
"_nv_record_extension_init: module register failed! result = %d.",
result);
}
uint32_t nv_record_pre_write_operation(void) {
uint32_t lock = int_lock_global();
mpu_clear(MPU_ID_USER_DATA_SECTION);
return lock;
}
void nv_record_post_write_operation(uint32_t lock) {
int ret = 0;
uint32_t nv_start = (uint32_t)&local_extension_data.nv_record;
uint32_t len = NV_EXTENSION_MIRROR_RAM_SIZE;
ret = mpu_set(MPU_ID_USER_DATA_SECTION, nv_start, len, 0, MPU_ATTR_READ);
int_unlock_global(lock);
TRACE(2, "set mpu 0x%x len %d result %d", nv_start, len, ret);
}
static void nv_record_extension_init(void) {
if (NULL == nvrecord_extension_p) {
uint32_t lock = nv_record_pre_write_operation();
_nv_record_extension_init();
nvrecord_extension_p = &local_extension_data.nv_record;
NVRECORD_HEADER_T *pExtRecInFlash =
&(((NV_EXTENSION_RECORD_T *)__userdata_start)->header);
TRACE(2, "nv ext magic 0x%x valid len %d", pExtRecInFlash->magicNumber,
pExtRecInFlash->validLen);
if ((NV_EXTENSION_MAJOR_VERSION == pExtRecInFlash->majorVersion) &&
(NV_EXTENSION_MAGIC_NUMBER == pExtRecInFlash->magicNumber)) {
// check whether the data length is valid
if (pExtRecInFlash->validLen <=
(NV_EXTENSION_SIZE - NV_EXTENSION_HEADER_SIZE)) {
// check crc32
uint32_t crc =
crc32(0, ((uint8_t *)pExtRecInFlash + NV_EXTENSION_HEADER_SIZE),
pExtRecInFlash->validLen);
TRACE(2, "generated crc32 0x%x crc32 in flash 0x%x", crc,
pExtRecInFlash->crc32);
if (crc == pExtRecInFlash->crc32) {
// correct
TRACE(0, "Nv extension is valid.");
TRACE(1, "Former nv ext valid len %d", pExtRecInFlash->validLen);
TRACE(1, "Current FW version nv ext valid len %d",
NV_EXTENSION_VALID_LEN);
if (NV_EXTENSION_VALID_LEN < pExtRecInFlash->validLen) {
TRACE(0, "Valid length of extension must be increased,"
"jump over the recovery but use the default value.");
} else {
memcpy(((uint8_t *)nvrecord_extension_p) + NV_EXTENSION_HEADER_SIZE,
((uint8_t *)pExtRecInFlash) + NV_EXTENSION_HEADER_SIZE,
pExtRecInFlash->validLen);
// frimware updates the nv extension data structure
if (pExtRecInFlash->validLen < NV_EXTENSION_VALID_LEN) {
// update the version number
nvrecord_extension_p->header.minorVersion =
NV_EXTENSION_MINOR_VERSION;
// re-calculate the crc32
nvrecord_extension_p->header.crc32 = crc32(
0,
((uint8_t *)nvrecord_extension_p + NV_EXTENSION_HEADER_SIZE),
NV_EXTENSION_VALID_LEN);
// need to update the content in the flash
nv_record_extension_update();
}
goto exit;
}
}
}
}
// the nv extension is invalid, should be recreated
nvrecord_rebuild_system_env(&(nvrecord_extension_p->system_info));
nvrecord_rebuild_paired_bt_dev_info(&(nvrecord_extension_p->bt_pair_info));
nvrecord_rebuild_paired_ble_dev_info(
&(nvrecord_extension_p->ble_pair_info));
#ifdef GFPS_ENABLED
nvrecord_rebuild_fp_account_key(
&(nvrecord_extension_p->fp_account_key_rec));
#endif
#ifdef NVREC_BAIDU_DATA_SECTION
nvrecord_rebuild_dma_configuration(&(nvrecord_extension_p->dma_config));
#endif
pExtRecInFlash->crc32 =
crc32(0, ((uint8_t *)nvrecord_extension_p + NV_EXTENSION_HEADER_SIZE),
NV_EXTENSION_VALID_LEN);
// need to update the content in the flash
nv_record_extension_update();
exit:
nv_record_post_write_operation(lock);
}
}
NV_EXTENSION_RECORD_T *nv_record_get_extension_entry_ptr(void) {
return nvrecord_extension_p;
}
void nv_record_extension_update(void) { isNvExtentionPendingForUpdate = true; }
static void nv_record_extension_flush(bool is_async) {
enum NORFLASH_API_RET_T ret;
uint32_t lock;
uint32_t crc;
#if defined(FLASH_SUSPEND) && defined(NVREC_BURN_TEST)
static uint32_t stime = 0;
if (hal_sys_timer_get() - stime > MS_TO_TICKS(20000)) {
stime = hal_sys_timer_get();
isNvExtentionPendingForUpdate = true;
}
#endif
if (isNvExtentionPendingForUpdate) {
if (is_async) {
lock = int_lock_global();
if (isNvExtentionState == NV_STATE_IDLE) {
ret = norflash_api_erase(NORFLASH_API_MODULE_ID_USERDATA_EXT,
(uint32_t)(__userdata_start),
NV_EXTENSION_SIZE, true);
if (ret == NORFLASH_API_OK) {
isNvExtentionState = NV_STATE_ERASED;
TRACE(2, "%s: norflash_api_erase ok,addr = 0x%x.", __func__,
(uint32_t)__userdata_start);
} else if (ret == NORFLASH_API_BUFFER_FULL) {
// do nothing.
} else {
ASSERT(0, "%s: norflash_api_erase err,ret = %d,addr = 0x%x.",
__func__, ret, (uint32_t)__userdata_start);
}
}
if (isNvExtentionState == NV_STATE_ERASED) {
uint32_t tmpLock = nv_record_pre_write_operation();
crc =
crc32(0, (uint8_t *)nvrecord_extension_p + NV_EXTENSION_HEADER_SIZE,
NV_EXTENSION_VALID_LEN);
nvrecord_extension_p->header.crc32 = crc;
nv_record_post_write_operation(tmpLock);
ret = norflash_api_write(
NORFLASH_API_MODULE_ID_USERDATA_EXT, (uint32_t)(__userdata_start),
(uint8_t *)nvrecord_extension_p, NV_EXTENSION_SIZE, true);
if (ret == NORFLASH_API_OK) {
isNvExtentionPendingForUpdate = false;
isNvExtentionState = NV_STATE_IDLE;
TRACE(2, "%s: norflash_api_write ok,addr = 0x%x.", __func__,
(uint32_t)__userdata_start);
} else if (ret == NORFLASH_API_BUFFER_FULL) {
// do nothing.
} else {
ASSERT(0, "%s: norflash_api_write err,ret = %d,addr = 0x%x.",
__func__, ret, (uint32_t)__userdata_start);
}
}
int_unlock_global(lock);
} else {
if (isNvExtentionState == NV_STATE_IDLE) {
do {
lock = int_lock_global();
ret = norflash_api_erase(NORFLASH_API_MODULE_ID_USERDATA_EXT,
(uint32_t)(__userdata_start),
NV_EXTENSION_SIZE, false);
int_unlock_global(lock);
if (ret == NORFLASH_API_OK) {
isNvExtentionState = NV_STATE_ERASED;
TRACE(2, "%s: norflash_api_erase ok,addr = 0x%x.", __func__,
(uint32_t)__userdata_start);
} else if (ret == NORFLASH_API_BUFFER_FULL) {
do {
norflash_api_flush();
} while (norflash_api_get_free_buffer_count(NORFLASH_API_ERASING) ==
0);
} else {
ASSERT(0, "%s: norflash_api_erase err,ret = %d,addr = 0x%x.",
__func__, ret, (uint32_t)__userdata_start);
}
} while (ret == NORFLASH_API_BUFFER_FULL);
}
if (isNvExtentionState == NV_STATE_ERASED) {
do {
lock = nv_record_pre_write_operation();
crc = crc32(
0, (uint8_t *)nvrecord_extension_p + NV_EXTENSION_HEADER_SIZE,
NV_EXTENSION_VALID_LEN);
nvrecord_extension_p->header.crc32 = crc;
ret = norflash_api_write(
NORFLASH_API_MODULE_ID_USERDATA_EXT, (uint32_t)(__userdata_start),
(uint8_t *)nvrecord_extension_p, NV_EXTENSION_SIZE, true);
nv_record_post_write_operation(lock);
if (ret == NORFLASH_API_OK) {
isNvExtentionPendingForUpdate = false;
isNvExtentionState = NV_STATE_IDLE;
TRACE(2, "%s: norflash_api_write ok,addr = 0x%x.", __func__,
(uint32_t)__userdata_start);
} else if (ret == NORFLASH_API_BUFFER_FULL) {
do {
norflash_api_flush();
} while (
norflash_api_get_free_buffer_count(NORFLASH_API_WRITTING) == 0);
} else {
ASSERT(0, "%s: norflash_api_write err,ret = %d,addr = 0x%x.",
__func__, ret, (uint32_t)__userdata_start);
}
} while (ret == NORFLASH_API_BUFFER_FULL);
do {
norflash_api_flush();
} while (norflash_api_get_used_buffer_count(
NORFLASH_API_MODULE_ID_USERDATA_EXT, NORFLASH_API_ALL) >
0);
}
}
}
}
void nv_extension_callback(void *param) {
NORFLASH_API_OPERA_RESULT *opera_result;
opera_result = (NORFLASH_API_OPERA_RESULT *)param;
TRACE(6, "%s:type = %d, addr = 0x%x,len = 0x%x,remain = %d,result = %d.",
__func__, opera_result->type, opera_result->addr, opera_result->len,
opera_result->remain_num, opera_result->result);
}
void nv_record_init(void) {
nv_record_open(section_usrdata_ddbrecord);
nv_custom_parameter_section_init();
}
bt_status_t nv_record_open(SECTIONS_ADP_ENUM section_id) {
nv_record_extension_init();
return BT_STS_SUCCESS;
}
void nv_record_update_runtime_userdata(void) { nv_record_extension_update(); }
int nv_record_touch_cause_flush(void) {
nv_record_update_runtime_userdata();
return 0;
}
void nv_record_sector_clear(void) {
uint32_t lock;
enum NORFLASH_API_RET_T ret;
lock = int_lock_global();
ret =
norflash_api_erase(NORFLASH_API_MODULE_ID_USERDATA_EXT,
(uint32_t)__userdata_start, NV_EXTENSION_SIZE, false);
nvrecord_extension_p = NULL;
int_unlock_global(lock);
nv_record_update_runtime_userdata();
ASSERT(ret == NORFLASH_API_OK,
"nv_record_sector_clear: norflash_api_erase failed! ret = %d.", ret);
}
void nv_record_rebuild(void) {
nv_record_sector_clear();
nv_record_extension_init();
}
void nv_record_flash_flush(void) {}
int nv_record_flash_flush_in_sleep(void) {
nv_record_extension_flush(true);
return 0;
}
#if defined(OTA_ENABLED)
void nv_record_extension_update_gsound_ota_session(uint8_t gsoundOtaStatus,
uint32_t totalImageSize,
const char *session) {
NV_EXTENSION_RECORD_T *pNvExtRec = nv_record_get_extension_entry_ptr();
TRACE(2, "gsound ota status is %d, is start is %d",
pNvExtRec->gsound_info.gsoundOtaStatus, gsoundOtaStatus);
if (pNvExtRec->gsound_info.gsoundOtaStatus != gsoundOtaStatus) {
if (GSOUND_OTA_STATUS_NONE == gsoundOtaStatus) {
pNvExtRec->gsound_info.gsoundOtaOffset = 0;
memset(pNvExtRec->gsound_info.gsoundOtaSessionString, 0,
sizeof(pNvExtRec->gsound_info.gsoundOtaSessionString));
} else if (GSOUND_OTA_STAGE_ONGOING == gsoundOtaStatus) {
ASSERT(totalImageSize, "Received total image size is 0.");
ASSERT(session, "Received session pointer is NULL.");
pNvExtRec->gsound_info.gsoundOtaImageSize = totalImageSize;
memcpy(pNvExtRec->gsound_info.gsoundOtaSessionString, session,
strlen(session) + 1);
} else if (GSOUND_OTA_STATUS_COMPLETE == gsoundOtaStatus) {
ASSERT(GSOUND_OTA_STAGE_ONGOING == pNvExtRec->gsound_info.gsoundOtaStatus,
"Wrong status transmission.");
ASSERT(totalImageSize == pNvExtRec->gsound_info.gsoundOtaImageSize,
"total image size changed.");
pNvExtRec->gsound_info.gsoundOtaOffset = totalImageSize;
}
pNvExtRec->gsound_info.gsoundOtaStatus = gsoundOtaStatus;
TRACE(1, "update gsound ota status to %d",
pNvExtRec->gsound_info.gsoundOtaStatus);
nv_record_extension_update();
nv_record_flash_flush();
}
}
void nv_record_extension_update_gsound_ota_progress(uint32_t otaOffset) {
NV_EXTENSION_RECORD_T *pNvExtRec = nv_record_get_extension_entry_ptr();
if ((GSOUND_OTA_STAGE_ONGOING == pNvExtRec->gsound_info.gsoundOtaStatus) &&
(otaOffset <= pNvExtRec->gsound_info.gsoundOtaImageSize)) {
pNvExtRec->gsound_info.gsoundOtaOffset = otaOffset;
nv_record_extension_update();
nv_record_flash_flush();
}
}
#endif
#endif // #if defined(NEW_NV_RECORD_ENABLED)

316
services/nv_section/fpga_section/nvrecord_externsion.h
View File

@ -1,316 +0,0 @@
/***************************************************************************
*
* Copyright 2015-2019 BES.
* All rights reserved. All unpublished rights reserved.
*
* No part of this work may be used or reproduced in any form or by any
* means, or stored in a database or retrieval system, without prior written
* permission of BES.
*
* Use of this work is governed by a license granted by BES.
* This work contains confidential and proprietary information of
* BES. which is protected by copyright, trade secret,
* trademark and other intellectual property rights.
*
****************************************************************************/
#ifdef NEW_NV_RECORD_ENABLED
#ifndef __NVRECORD_EXTENSION_H__
#define __NVRECORD_EXTENSION_H__
#include "bluetooth.h"
#include "me_api.h"
#include "btif_sys_config.h"
// increase by 1 if the nvrecord's whole data structure is changed and the content needs to be rebuilt
#define NV_EXTENSION_MAJOR_VERSION 2
// increase by 1 if the new items are appended to the tail of the former nvrecord's data structure
#define NV_EXTENSION_MINOR_VERSION 1
#define NV_EXTENSION_SIZE 4096 // one flash page
#define NV_EXTENSION_HEADER_SIZE sizeof(NVRECORD_HEADER_T) // magic number and valid length
#define NV_EXTENSION_MAGIC_NUMBER 0x4E455854
#define NV_EXTENSION_VALID_LEN (sizeof(NV_EXTENSION_RECORD_T) - sizeof(NVRECORD_HEADER_T))
/* unused, just for backwards compatible */
#define section_name_ddbrec "ddbrec"
/* BT paired device info */
#define MAX_BT_PAIRED_DEVICE_COUNT 8
/* BLE paired device information */
#define BLE_RECORD_NUM 5
#define BLE_ADDR_SIZE 6
#define BLE_ENC_RANDOM_SIZE 8
#define BLE_LTK_SIZE 16
#define BLE_IRK_SIZE 16
#define BLE_STATIC_ADDR 0
#define BLE_RANDOM_ADDR 1
#ifdef GFPS_ENABLED
/* fast pair account key */
#define FP_ACCOUNT_KEY_RECORD_NUM 5
#define FP_ACCOUNT_KEY_SIZE 16
#define FP_MAX_NAME_LEN 64
#endif
// TODO: should be increased if NV_EXTENSION_MIRROR_RAM_SIZE exceeds this value
#define TILE_INFO_SIZE 400
#define BT_FREQENCY_RANGE_NUM 3
#define BT_IQ_INVALID_MAGIC_NUM 0xFFFFFFFF
#define BT_IQ_VALID_MAGIC_NUM 0x5a5a5a5a
typedef struct
{
uint32_t validityMagicNum;
uint16_t gain_cal_val[BT_FREQENCY_RANGE_NUM];
uint16_t phase_cal_val[BT_FREQENCY_RANGE_NUM];
} BT_IQ_CALIBRATION_CONFIG_T;
/* nv record header data structure */
typedef struct
{
uint32_t magicNumber;
uint16_t majorVersion; // should be NV_EXTENSION_MAJOR_VERSION
uint16_t minorVersion; // should be NV_EXTENSION_MINOR_VERSION
uint32_t validLen; // should be the valid content in this nv record version
uint32_t crc32; // crc32 of following valid values in the nv extention section
} NVRECORD_HEADER_T;
/* system information */
typedef struct {
int8_t language;
} media_language_t;
#if defined(APP_LINEIN_A2DP_SOURCE) || defined(APP_I2S_A2DP_SOURCE)
typedef struct {
int8_t src_snk_mode;
} src_snk_t;
#endif
typedef struct {
uint32_t mode;
btif_device_record_t record;
bool tws_connect_success;
} ibrt_mode_t;
typedef struct {
uint32_t status;
} factory_tester_status_t;
typedef struct {
uint8_t setedCurrentAi;
uint8_t currentAiSpec;
uint8_t aiStatusDisableFlag;
uint8_t amaAssistantEnableStatus;
} AI_MANAGER_INFO_T;
struct nvrecord_env_t {
media_language_t media_language;
#if defined(APP_LINEIN_A2DP_SOURCE) || defined(APP_I2S_A2DP_SOURCE)
src_snk_t src_snk_flag;
#endif
ibrt_mode_t ibrt_mode;
factory_tester_status_t factory_tester_status;
uint8_t flag_value[8];
bool voice_key_enable;
AI_MANAGER_INFO_T aiManagerInfo;
};
typedef struct btdevice_volume {
int8_t a2dp_vol;
int8_t hfp_vol;
} btdevice_volume;
typedef struct btdevice_profile {
bool hfp_act;
bool hsp_act;
bool a2dp_act;
uint8_t a2dp_codectype;
} btdevice_profile;
typedef struct {
btif_device_record_t record;
btdevice_volume device_vol;
btdevice_profile device_plf;
#ifdef BTIF_DIP_DEVICE
uint16_t vend_id;
uint16_t vend_id_source;
uint16_t reserve;
#endif
} nvrec_btdevicerecord;
typedef struct {
uint32_t pairedDevNum;
nvrec_btdevicerecord pairedBtDevInfo[MAX_BT_PAIRED_DEVICE_COUNT];
} NV_RECORD_PAIRED_BT_DEV_INFO_T;
typedef enum {
section_usrdata_ddbrecord,
section_none
} SECTIONS_ADP_ENUM;
#if defined(OTA_ENABLED)
typedef enum {
OTA_STATUS_NONE = 0,
OTA_STAGE_ONGOING = 1,
OTA_STATUS_COMPLETE = 2,
OTA_STATUS_NUM,
} GSOUND_OTA_STATUS_E;
#endif
typedef struct {
uint8_t ble_addr[BTIF_BD_ADDR_SIZE];
uint8_t ble_irk[BLE_IRK_SIZE];
} BLE_BASIC_INFO_T;
typedef struct {
uint8_t peer_bleAddr[BLE_ADDR_SIZE];
uint16_t EDIV;
uint8_t RANDOM[BLE_ENC_RANDOM_SIZE];
uint8_t LTK[BLE_LTK_SIZE];
uint8_t IRK[BLE_IRK_SIZE];
uint8_t bonded;
} BleDeviceinfo;
typedef struct {
uint32_t saved_list_num;
BLE_BASIC_INFO_T self_info;
BleDeviceinfo ble_nv[BLE_RECORD_NUM];
} NV_RECORD_PAIRED_BLE_DEV_INFO_T;
#ifdef TWS_SYSTEM_ENABLED
typedef struct {
BLE_BASIC_INFO_T ble_info;
} TWS_INFO_T;
#endif // #ifdef TWS_SYSTEM_ENABLED
#ifdef GFPS_ENABLED
typedef struct {
uint8_t key[FP_ACCOUNT_KEY_SIZE];
} NV_FP_ACCOUNT_KEY_ENTRY_T;
typedef struct {
uint32_t key_count;
NV_FP_ACCOUNT_KEY_ENTRY_T accountKey[FP_ACCOUNT_KEY_RECORD_NUM];
uint16_t nameLen;
uint8_t name[FP_MAX_NAME_LEN];
} NV_FP_ACCOUNT_KEY_RECORD_T;
#endif // #ifdef GFPS_ENABLED
#ifdef NVREC_BAIDU_DATA_SECTION
/* DMA owned configuration information */
typedef struct {
int32_t fmfreq;
char rand[BAIDU_DATA_RAND_LEN + 1];
} NV_DMA_CONFIGURATION_T;
#endif // #ifdef NVREC_BAIDU_DATA_SECTION
#ifdef TILE_DATAPATH
typedef struct {
uint8_t tileInfo[TILE_INFO_SIZE];
} NV_TILE_INFO_CONFIG_T;
#endif
#if defined(BISTO_ENABLED)
typedef struct {
uint8_t isGsoundEnabled;
uint8_t gsoundOtaStatus;
uint32_t gsoundOtaOffset;
uint32_t gsoundOtaImageSize;
uint8_t gsoundOtaSessionString[16];
} NV_GSOUND_INFO_T;
#endif
typedef struct {
NVRECORD_HEADER_T header;
struct nvrecord_env_t system_info;
NV_RECORD_PAIRED_BT_DEV_INFO_T bt_pair_info;
NV_RECORD_PAIRED_BLE_DEV_INFO_T ble_pair_info;
#ifdef TWS_SYSTEM_ENABLED
TWS_INFO_T tws_info;
#endif
#ifdef GFPS_ENABLED
NV_FP_ACCOUNT_KEY_RECORD_T fp_account_key_rec;
#endif
#ifdef NVREC_BAIDU_DATA_SECTION
NV_DMA_CONFIGURATION_T dma_config;
#endif
#ifdef TILE_DATAPATH
NV_TILE_INFO_CONFIG_T tileConfig;
#endif
#if defined(BISTO_ENABLED)
NV_GSOUND_INFO_T gsound_info;
#endif
#ifdef TX_IQ_CAL
BT_IQ_CALIBRATION_CONFIG_T btIqCalConfig;
#endif
// TODO: If wanna OTA to update the nv record, two choices:
// 1. Change above data structures and increase NV_EXTENSION_MAJOR_VERSION.
// Then the nv record will be rebuilt and the whole history information will be cleared
// 2. Don't touch above data structures but just add new items here and increase NV_EXTENSION_MINOR_VERSION.
// Then the nv record will keep all the whole hisotry.
} NV_EXTENSION_RECORD_T;
typedef union {
NV_EXTENSION_RECORD_T nv_record;
/*
* dummy data, just make sure the mirror buffer's size is
* "NV_EXTENSION_MIRROR_RAM_SIZE"
*/
uint8_t dummy_data[NV_EXTENSION_MIRROR_RAM_SIZE];
} NV_MIRROR_BUF_T;
#ifdef __cplusplus
extern "C" {
#endif
extern NV_EXTENSION_RECORD_T *nvrecord_extension_p;
int nv_record_env_init(void);
NV_EXTENSION_RECORD_T *nv_record_get_extension_entry_ptr(void);
void nv_record_extension_update(void);
void nv_extension_callback(void *param);
int nv_record_touch_cause_flush(void);
void nv_record_sector_clear(void);
void nv_record_flash_flush(void);
int nv_record_flash_flush_in_sleep(void);
void nv_record_execute_async_flush(void);
void nv_record_update_runtime_userdata(void);
void nv_record_rebuild(void);
uint32_t nv_record_pre_write_operation(void);
void nv_record_post_write_operation(uint32_t lock);
bt_status_t nv_record_open(SECTIONS_ADP_ENUM section_id);
void nv_record_init(void);
#ifdef __cplusplus
}
#endif
#endif
#endif //#if defined(NEW_NV_RECORD_ENABLED)

317
services/osif/ddbif_bes.c
View File

@ -21,7 +21,6 @@
#include "hal_trace.h"
#include "me_api.h"
#ifndef FPGA
#include "cmsis.h"
#include "cmsis_os.h"
#include "nvrecord.h"
@ -71,319 +70,3 @@ bt_status_t ddbif_delete_record(const bt_bdaddr_t *bdAddr) {
bt_status_t ddbif_enum_device_records(I16 index, btif_device_record_t *record) {
return nv_record_enum_dev_records((unsigned short)index, record);
}
#else
typedef struct _DDB_List {
struct _DDB_List *next;
btif_device_record_t *record;
} DDB_List;
static DDB_List *head = NULL;
static bt_bdaddr_t remDev_addr;
static int DDB_Print_Node(btif_device_record_t *record);
static int DDB_Print();
static void *DDB_Malloc(uint32_t size) { return malloc(size); }
static void DDB_Free(void *p_mem) { free(p_mem); }
static char POSSIBLY_UNUSED Hex2String(unsigned char *src, char *dest,
unsigned int srcLen,
unsigned int destLen) {
unsigned int i = 0;
unsigned char hb = 0, lb = 0;
memset((char *)dest, 0, destLen);
for (i = 0; i < srcLen; i++) {
hb = (src[i] & 0xf0) >> 4;
if (hb >= 0 && hb <= 9)
hb += 0x30;
else if (hb >= 10 && hb <= 15)
hb = hb - 10 + 'A';
else
return 0;
lb = src[i] & 0x0f;
if (lb >= 0 && lb <= 9)
lb += 0x30;
else if (lb >= 10 && lb <= 15)
lb = lb - 10 + 'A';
else
return 0;
dest[i * 2 + 0] = hb;
dest[i * 2 + 1] = lb;
}
return 1;
}
static void DDB_List_delete(DDB_List *list_head) {
DDB_List *list = list_head, *list_tmp = NULL;
while (NULL != list) {
list_tmp = list;
if (NULL != list->record)
DDB_Free(list->record);
list = list->next;
DDB_Free(list_tmp);
}
}
bt_status_t ddbif_close(void) {
DDB_List *Close_tmp = NULL;
Close_tmp = head;
while (1) {
DDB_Print();
Close_tmp = Close_tmp->next;
if (Close_tmp == NULL) {
TRACE(0, "DDB_Close.\n");
break;
}
}
DDB_List_delete(head);
return BT_STS_SUCCESS;
}
bt_status_t ddbif_add_record(btif_device_record_t *record) {
DDB_List *ptr = NULL;
DDB_List *tmp = NULL;
ptr = head;
tmp = (DDB_List *)DDB_Malloc(sizeof(DDB_List));
if (tmp == NULL) {
TRACE(
0,
"DDB_AddRecord head == NULL:There is no enough space for DDB_List.\n");
return BT_STS_FAILED;
}
tmp->next = NULL;
tmp->record =
(btif_device_record_t *)DDB_Malloc(sizeof(btif_device_record_t));
if (NULL == tmp->record) {
TRACE(0, "DDB_AddRecord head == NULL:There is no enough space for "
"DDB_List.record.\n");
return BT_STS_FAILED;
}
if (head == NULL) {
memcpy(tmp->record->bdAddr.address, record->bdAddr.address,
sizeof(record->bdAddr.address));
tmp->record->keyType = record->keyType;
memcpy(tmp->record->linkKey, record->linkKey, sizeof(record->linkKey));
tmp->record->pinLen = record->pinLen;
tmp->record->trusted = record->trusted;
head = tmp;
memcpy(remDev_addr.address, tmp->record->bdAddr.address,
sizeof(tmp->record->bdAddr.address));
TRACE(0, "DDB_AddRecord head:\n");
DDB_Print_Node(tmp->record);
DDB_Print();
return BT_STS_SUCCESS;
}
while ((ptr->next != NULL) &&
(memcmp(ptr->record->bdAddr.address, record->bdAddr.address,
sizeof(ptr->record->bdAddr.address)))) {
ptr = ptr->next;
}
if (!memcmp(ptr->record->bdAddr.address, record->bdAddr.address,
sizeof(ptr->record->bdAddr.address))) {
ptr->record->keyType = record->keyType;
memcpy(ptr->record->linkKey, record->linkKey, sizeof(record->linkKey));
ptr->record->pinLen = record->pinLen;
ptr->record->trusted = record->trusted;
TRACE(0, "DDB_AddRecord head::\n");
DDB_Print_Node(ptr->record);
DDB_Print();
free(tmp->record);
free(tmp);
return BT_STS_SUCCESS;
}
if (ptr->next == NULL) {
tmp->next = NULL;
memcpy(tmp->record->bdAddr.address, record->bdAddr.address,
sizeof(record->bdAddr.address));
tmp->record->keyType = record->keyType;
memcpy(tmp->record->linkKey, record->linkKey, sizeof(record->linkKey));
tmp->record->pinLen = record->pinLen;
tmp->record->trusted = record->trusted;
memcpy(remDev_addr.address, tmp->record->bdAddr.address,
sizeof(tmp->record->bdAddr.address));
ptr->next = tmp;
TRACE(0, "DDB_AddRecord head:::\n");
DDB_Print_Node(tmp->record);
DDB_Print();
return BT_STS_SUCCESS;
}
return BT_STS_FAILED;
}
bt_status_t ddbif_open(const bt_bdaddr_t *bdAddr) {
// DDB_List *head = NULL;
return BT_STS_SUCCESS;
}
static int DDB_Print_Node(btif_device_record_t *record) {
int i;
for (i = 0; i < 6; i++) {
TRACE(1, "%x ", record->bdAddr.address[i]);
}
TRACE(0, "\n");
/*
for(i=0; i<16; i++)
{
TRACE(1,"%x ",record->linkKey[i]);
}
TRACE(0,"\n");
TRACE(3,"%d,%d,%d\n",record->keyType,record->pinLen,record->trusted);
*/
return 1;
}
static int DDB_Print() {
DDB_List *Print_tmp = NULL;
Print_tmp = head;
if (Print_tmp == NULL) {
TRACE(0, "DDB list is null!\n");
return 0;
}
TRACE(0, "-----------------DDB list-------------------\n");
while (Print_tmp != NULL) {
DDB_Print_Node(Print_tmp->record);
Print_tmp = Print_tmp->next;
}
TRACE(0, "--------------------end---------------------\n");
return 0;
}
bt_status_t ddbif_find_record(const bt_bdaddr_t *bdAddr,
btif_device_record_t *record) {
DDB_List *FindRecord_tmp = NULL;
FindRecord_tmp = head;
if (head == NULL) {
TRACE(0, "DDB_FindRecord:DDB is null!\n");
return BT_STS_FAILED;
}
while (memcmp(FindRecord_tmp->record->bdAddr.address, bdAddr->address,
sizeof(FindRecord_tmp->record->bdAddr.address)) &&
(FindRecord_tmp->next != NULL)) {
FindRecord_tmp = FindRecord_tmp->next;
}
if (!memcmp(FindRecord_tmp->record->bdAddr.address, bdAddr->address,
sizeof(FindRecord_tmp->record->bdAddr.address))) {
memcpy(record->bdAddr.address, FindRecord_tmp->record->bdAddr.address,
sizeof(FindRecord_tmp->record->bdAddr.address));
record->keyType = FindRecord_tmp->record->keyType;
memcpy(record->linkKey, FindRecord_tmp->record->linkKey,
sizeof(FindRecord_tmp->record->linkKey));
record->pinLen = FindRecord_tmp->record->pinLen;
record->trusted = FindRecord_tmp->record->trusted;
TRACE(0, "DDB_FindRecord:\n");
DDB_Print_Node(record);
return BT_STS_SUCCESS;
}
if (FindRecord_tmp->next == NULL) {
TRACE(0, "DDB_FindRecord ends.\n");
return BT_STS_FAILED;
}
return BT_STS_FAILED;
}
bt_status_t ddbif_delete_record(const bt_bdaddr_t *bdAddr) {
DDB_List *checkingAddr = NULL;
DDB_List *checkedAddr = NULL;
checkingAddr = head;
if (head == NULL) {
TRACE(0, "DDB_DeleteRecord:list is null!\n");
return BT_STS_FAILED;
}
while (memcmp(checkingAddr->record->bdAddr.address, bdAddr->address,
sizeof(checkingAddr->record->bdAddr.address)) &&
(checkingAddr->next != NULL)) {
checkedAddr = checkingAddr;
checkingAddr = checkingAddr->next;
}
if (!memcmp(checkingAddr->record->bdAddr.address, bdAddr->address,
sizeof(checkingAddr->record->bdAddr.address))) {
if (checkingAddr == head) {
head = checkingAddr->next;
free(checkingAddr->record);
free(checkingAddr);
DDB_Print();
return BT_STS_SUCCESS;
} else {
checkedAddr->next = checkingAddr->next;
free(checkingAddr->record);
free(checkingAddr);
DDB_Print();
return BT_STS_SUCCESS;
}
}
if (checkingAddr->next == NULL) {
return BT_STS_FAILED;
}
return BT_STS_FAILED;
}
bt_status_t ddbif_enum_device_records(I16 index, btif_device_record_t *record) {
DDB_List *databaselist;
databaselist = head;
if (head == NULL) {
TRACE(0, "DDB_EnumDeviceRecords:No records!\n");
return BT_STS_FAILED;
}
TRACE(1, "index=%d\n", (uint32_t)index);
while (databaselist != NULL) {
if (!index) {
break;
}
databaselist = databaselist->next;
index--;
}
if ((index == 0) && (databaselist != NULL)) {
TRACE(0, "Enum record:\n");
DDB_Print_Node(databaselist->record);
TRACE(0, "Enumeration ends!\n\n");
return BT_STS_SUCCESS;
}
if (databaselist == NULL) {
TRACE(0, "Enumeration failed.\n");
return BT_STS_FAILED;
}
return BT_STS_FAILED;
}
#endif

2
services/overlay/app_overlay.cpp
View File

@ -26,7 +26,6 @@ static APP_OVERLAY_ID_T app_overlay_id = APP_OVERLAY_ID_QTY;
APP_OVERLAY_ID_T app_get_current_overlay(void) { return app_overlay_id; }
void app_overlay_select(enum APP_OVERLAY_ID_T id) {
#ifndef FPGA
TRACE(3, "%s id:%d:%d", __func__, id, app_overlay_id);
osMutexWait(app_overlay_mutex_id, osWaitForever);
@ -40,7 +39,6 @@ void app_overlay_select(enum APP_OVERLAY_ID_T id) {
}
app_overlay_id = id;
osMutexRelease(app_overlay_mutex_id);
#endif
}
void app_overlay_unloadall(void) {

2
tests/anc_usb/main.c
View File

@ -416,7 +416,7 @@ int MAIN_ENTRY(void) {
hal_trace_open(HAL_TRACE_TRANSPORT_UART0);
#endif
#if !defined(SIMU) && !defined(FPGA)
#if !defined(SIMU)
uint8_t flash_id[HAL_NORFLASH_DEVICE_ID_LEN];
hal_norflash_get_id(HAL_NORFLASH_ID_0, flash_id, ARRAY_SIZE(flash_id));
TRACE(3, "FLASH_ID: %02X-%02X-%02X", flash_id[0], flash_id[1], flash_id[2]);

4
utils/hwtimer_list/hwtimer_list.c
View File

@ -21,7 +21,7 @@
#include "hal_trace.h"
#include "stdio.h"
#if defined(ROM_BUILD) && !defined(SIMU) && !defined(FPGA)
#if defined(ROM_BUILD) && !defined(SIMU)
#error \
"The user of raw timer API must be unique. Now rom is using raw timer API."
#endif
@ -32,7 +32,7 @@
#define HWTIMER_NUM 10
#endif
//#define HWTIMER_TEST
// #define HWTIMER_TEST
enum HWTIMER_STATE_T {
HWTIMER_STATE_FREE = 0,