117 lines
4.5 KiB
C
117 lines
4.5 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_UART_H__
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#define __REG_UART_H__
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#include "plat_types.h"
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// UART Registers
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struct UART_T {
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__IO uint32_t UARTDR; // 0x000
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union {
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__I uint32_t UARTRSR; // 0x004
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__O uint32_t UARTECR; // 0x004
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};
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uint32_t RESERVED_008[4]; // 0x008
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__I uint32_t UARTFR; // 0x018
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uint32_t RESERVED_01C; // 0x01C
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__IO uint32_t UARTILPR; // 0x020
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__IO uint32_t UARTIBRD; // 0x024
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__IO uint32_t UARTFBRD; // 0x028
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__IO uint32_t UARTLCR_H; // 0x02C
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__IO uint32_t UARTCR; // 0x030
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__IO uint32_t UARTIFLS; // 0x034
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__IO uint32_t UARTIMSC; // 0x038
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__I uint32_t UARTRIS; // 0x03C
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__I uint32_t UARTMIS; // 0x040
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__O uint32_t UARTICR; // 0x044
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__IO uint32_t UARTDMACR; // 0x048
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uint32_t RESERVED_04C[997]; // 0x04C
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__I uint32_t UARTPID0; // 0xFE0
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__I uint32_t UARTPID1; // 0xFE4
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__I uint32_t UARTPID2; // 0xFE8
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__I uint32_t UARTPID3; // 0xFEC
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__I uint32_t UARTPCID0; // 0xFF0
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__I uint32_t UARTPCID1; // 0xFF4
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__I uint32_t UARTPCID2; // 0xFF8
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__I uint32_t UARTPCID3; // 0xFFC
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};
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// Data status bits
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#define UART_DATA_ERROR_MASK 0x0F00
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// Status reg bits
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#define UART_STATUS_ERROR_MASK 0x0F
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// Flag reg bits
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#define UARTFR_RI (1 << 8) // Ring indicator
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#define UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define UARTFR_BUSY (1 << 3) // UART busy
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#define UARTFR_DCD (1 << 2) // Data carrier detect
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#define UARTFR_DSR (1 << 1) // Data set ready
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#define UARTFR_CTS (1 << 0) // Clear to send
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// Flag reg bits - alternative names
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#define UART_TX_EMPTY_FLAG_MASK UARTFR_TXFE
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#define UART_RX_FULL_FLAG_MASK UARTFR_RXFF
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#define UART_TX_FULL_FLAG_MASK UARTFR_TXFF
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#define UART_RX_EMPTY_FLAG_MASK UARTFR_RXFE
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#define UART_BUSY_FLAG_MASK UARTFR_BUSY
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// Control reg bits
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#define UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
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#define UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
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#define UARTCR_RTS (1 << 11) // Request to send
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#define UARTCR_DTR (1 << 10) // Data transmit ready.
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#define UARTCR_RXE (1 << 9) // Receive enable
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#define UARTCR_TXE (1 << 8) // Transmit enable
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#define UARTCR_LBE (1 << 7) // Loopback enable
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#define UARTCR_UARTEN (1 << 0) // UART Enable
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// Line Control Register Bits
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#define UARTLCR_H_DMA_RT_EN (1 << 15)
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#define UARTLCR_H_DMA_RT_CNT(n) (((n) & 0x7F) << 8)
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#define UARTLCR_H_DMA_RT_CNT_MASK (0x7F << 8)
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#define UARTLCR_H_DMA_RT_CNT_SHIFT (8)
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#define UARTLCR_H_SPS (1 << 7) // Stick parity select
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#define UARTLCR_H_WLEN_8 (3 << 5)
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#define UARTLCR_H_WLEN_7 (2 << 5)
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#define UARTLCR_H_WLEN_6 (1 << 5)
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#define UARTLCR_H_WLEN_5 (0 << 5)
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#define UARTLCR_H_FEN (1 << 4) // FIFOs Enable
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#define UARTLCR_H_STP2 (1 << 3) // Two stop bits select
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#define UARTLCR_H_EPS (1 << 2) // Even parity select
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#define UARTLCR_H_PEN (1 << 1) // Parity Enable
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#define UARTLCR_H_BRK (1 << 0) // Send break
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// UARTIFLS reg bits
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#define UARTIFLS_TXFIFO_LEVEL(n) (((n) & 3) << 0)
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#define UARTIFLS_TXFIFO_LEVEL_MASK (3 << 0)
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#define UARTIFLS_TXFIFO_LEVEL_SHIFT (0)
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#define UARTIFLS_RXFIFO_LEVEL(n) (((n) & 3) << 3)
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#define UARTIFLS_RXFIFO_LEVEL_MASK (3 << 3)
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#define UARTIFLS_RXFIFO_LEVEL_SHIFT (3)
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// DMACR reg bits
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#define UARTDMACR_RXDMAE (1 << 0)
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#define UARTDMACR_TXDMAE (1 << 1)
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#define UARTDMACR_DMAONERR (1 << 2)
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#endif
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