113 lines
4.0 KiB
C
113 lines
4.0 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_SPI_H__
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#define __REG_SPI_H__
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#include "plat_types.h"
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struct SPI_T
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{
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__IO uint32_t SSPCR0; //0x00000000
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__IO uint32_t SSPCR1; //0x00000004
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__IO uint32_t SSPDR; //0x00000008
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__I uint32_t SSPSR; //0x0000000C
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__IO uint32_t SSPCPSR; //0x00000010
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__IO uint32_t SSPIMSC; //0x00000014
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__I uint32_t SSPRIS; //0x00000018
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__I uint32_t SSPMIS; //0x0000001C
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__O uint32_t SSPICR; //0x00000020
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__IO uint32_t SSPDMACR; //0x00000024
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uint32_t reserved[0x18]; //0x00000028
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__IO uint32_t SSPRXCR; //0x00000088
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};
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#define MAX_SCR (0xFF)
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#define MIN_SCR (0)
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#define MAX_DATA_BITS (32)
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#define MIN_DATA_BITS (4)
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#define SPI_SSPCR0_DSS(n) (((n) & 0x1F) << 16)
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#define SPI_SSPCR0_DSS_MASK (0x1F << 16)
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#define SPI_SSPCR0_DSS_SHIFT (16)
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#define SPI_SSPCR0_SCR(n) (((n) & 0xFF) << 8)
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#define SPI_SSPCR0_SCR_MASK (0xFF << 8)
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#define SPI_SSPCR0_SCR_SHIFT (8)
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#define SPI_SSPCR0_SPH (1 << 7)
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#define SPI_SSPCR0_SPO (1 << 6)
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#define SPI_SSPCR0_FRF(n) (((n) & 3) << 4)
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#define SPI_SSPCR0_FRF_MASK (3 << 4)
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#define SPI_SSPCR0_FRF_SHIFT (4)
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#if (CHIP_SPI_VER >= 4)
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#define SPI_RX_SEL_EN (1 << 11)
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#define SPI_SLAVE_ID_SHIFT (7)
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#define SPI_SLAVE_ID_MASK (0xF << SPI_SLAVE_ID_SHIFT)
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#define SPI_SLAVE_ID(n) BITFIELD_VAL(SPI_SLAVE_ID, n)
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#else
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#define SPI_RX_SEL_EN (1 << 9)
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#define SPI_SLAVE_ID_SHIFT (7)
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#define SPI_SLAVE_ID_MASK (3 << SPI_SLAVE_ID_SHIFT)
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#define SPI_SLAVE_ID(n) BITFIELD_VAL(SPI_SLAVE_ID, n)
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#endif
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#define SPI_LCD_DC_DATA (1 << 4)
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#define SPI_SSPCR1_SOD (1 << 3)
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#define SPI_SSPCR1_MS (1 << 2)
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#define SPI_SSPCR1_SSE (1 << 1)
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#define SPI_SSPCR1_LBM (1 << 0)
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#define SPI_SSPSR_BSY (1 << 4)
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#define SPI_SSPSR_RFF (1 << 3)
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#define SPI_SSPSR_RNE (1 << 2)
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#define SPI_SSPSR_TNF (1 << 1)
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#define SPI_SSPSR_TFE (1 << 0)
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#define MAX_CPSDVSR (0xFE)
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#define MIN_CPSDVSR (2)
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#define SPI_SSPCPSR_CPSDVSR(n) (((n) & 0xFF) << 0)
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#define SPI_SSPCPSR_CPSDVSR_MASK (0xFF << 0)
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#define SPI_SSPCPSR_CPSDVSR_SHIFT (0)
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#define SPI_SSPIMSC_TXIM (1 << 3)
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#define SPI_SSPIMSC_RXIM (1 << 2)
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#define SPI_SSPIMSC_RTIM (1 << 1)
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#define SPI_SSPIMSC_RORIM (1 << 0)
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#define SPI_SSPRIS_TXRIS (1 << 3)
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#define SPI_SSPRIS_RXRIS (1 << 2)
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#define SPI_SSPRIS_RTRIS (1 << 1)
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#define SPI_SSPRIS_RORRIS (1 << 0)
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#define SPI_SSPMIS_TXMIS (1 << 3)
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#define SPI_SSPMIS_RXMIS (1 << 2)
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#define SPI_SSPMIS_RTMIS (1 << 1)
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#define SPI_SSPMIS_RORMIS (1 << 0)
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#define SPI_SSPICR_RTIC (1 << 1)
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#define SPI_SSPICR_RORIC (1 << 0)
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#define SPI_SSPDMACR_TXDMAE (1 << 1)
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#define SPI_SSPDMACR_RXDMAE (1 << 0)
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#define SPI_SSPRXCR_EN (1 << 6)
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#define SPI_SSPRXCR_OEN_POLARITY (1 << 5)
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#define SPI_SSPRXCR_RXBITS(n) (((n) & 0x1F) << 0)
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#define SPI_SSPRXCR_RXBITS_MASK (0x1F << 0)
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#define SPI_SSPRXCR_RXBITS_SHIFT (0)
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#endif
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