150 lines
5.4 KiB
C
150 lines
5.4 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __SDMMCIP_REG_HW_H
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#define __SDMMCIP_REG_HW_H
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#include "plat_types.h"
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#define SDMMCIP_REG_CTRL 0x000
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#define SDMMCIP_REG_PWREN 0x004
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#define SDMMCIP_REG_CLKDIV 0x008
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#define SDMMCIP_REG_CLKSRC 0x00C
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#define SDMMCIP_REG_CLKENA 0x010
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#define SDMMCIP_REG_TMOUT 0x014
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#define SDMMCIP_REG_CTYPE 0x018
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#define SDMMCIP_REG_BLKSIZ 0x01C
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#define SDMMCIP_REG_BYTCNT 0x020
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#define SDMMCIP_REG_INTMASK 0x024
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#define SDMMCIP_REG_CMDARG 0x028
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#define SDMMCIP_REG_CMD 0x02C
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#define SDMMCIP_REG_RESP0 0x030
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#define SDMMCIP_REG_RESP1 0x034
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#define SDMMCIP_REG_RESP2 0x038
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#define SDMMCIP_REG_RESP3 0x03C
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#define SDMMCIP_REG_MINTSTS 0x040
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#define SDMMCIP_REG_RINTSTS 0x044
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#define SDMMCIP_REG_STATUS 0x048
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#define SDMMCIP_REG_FIFOTH 0x04C
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#define SDMMCIP_REG_CDETECT 0x050
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#define SDMMCIP_REG_WRTPRT 0x054
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#define SDMMCIP_REG_GPIO 0x058
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#define SDMMCIP_REG_TCMCNT 0x05C
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#define SDMMCIP_REG_TBBCNT 0x060
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#define SDMMCIP_REG_DEBNCE 0x064
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#define SDMMCIP_REG_USRID 0x068
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#define SDMMCIP_REG_VERID 0x06C
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#define SDMMCIP_REG_HCON 0x070
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#define SDMMCIP_REG_UHS_REG 0x074
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#define SDMMCIP_REG_RESET_CARD 0x078
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#define SDMMCIP_REG_BMOD 0x080
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#define SDMMCIP_REG_PLDMND 0x084
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#define SDMMCIP_REG_DBADDR 0x088
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#define SDMMCIP_REG_IDSTS 0x08C
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#define SDMMCIP_REG_IDINTEN 0x090
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#define SDMMCIP_REG_DSCADDR 0x094
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#define SDMMCIP_REG_BUFADDR 0x098
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#define SDMMCIP_REG_DATA 0x200
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/* Interrupt Mask register */
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#define SDMMCIP_REG_INTMSK_ALL 0xffffffff
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#define SDMMCIP_REG_INTMSK_CD (1 << 0)
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#define SDMMCIP_REG_INTMSK_RE (1 << 1)
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#define SDMMCIP_REG_INTMSK_CDONE (1 << 2)
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#define SDMMCIP_REG_INTMSK_DTO (1 << 3)
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#define SDMMCIP_REG_INTMSK_TXDR (1 << 4)
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#define SDMMCIP_REG_INTMSK_RXDR (1 << 5)
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#define SDMMCIP_REG_INTMSK_DCRC (1 << 7)
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#define SDMMCIP_REG_INTMSK_RTO (1 << 8)
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#define SDMMCIP_REG_INTMSK_DRTO (1 << 9)
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#define SDMMCIP_REG_INTMSK_HTO (1 << 10)
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#define SDMMCIP_REG_INTMSK_FRUN (1 << 11)
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#define SDMMCIP_REG_INTMSK_HLE (1 << 12)
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#define SDMMCIP_REG_INTMSK_SBE (1 << 13)
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#define SDMMCIP_REG_INTMSK_ACD (1 << 14)
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#define SDMMCIP_REG_INTMSK_EBE (1 << 15)
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/* Raw interrupt Regsiter */
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#define SDMMCIP_REG_DATA_ERR (SDMMCIP_REG_INTMSK_EBE | SDMMCIP_REG_INTMSK_SBE | SDMMCIP_REG_INTMSK_HLE |\
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SDMMCIP_REG_INTMSK_FRUN | SDMMCIP_REG_INTMSK_EBE | SDMMCIP_REG_INTMSK_DCRC)
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#define SDMMCIP_REG_DATA_TOUT (SDMMCIP_REG_INTMSK_HTO | SDMMCIP_REG_INTMSK_DRTO)
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/* CTRL register */
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#define SDMMCIP_REG_CTRL_RESET (1 << 0)
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#define SDMMCIP_REG_CTRL_FIFO_RESET (1 << 1)
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#define SDMMCIP_REG_CTRL_DMA_RESET (1 << 2)
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#define SDMMCIP_REG_INT_EN (1 << 4)
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#define SDMMCIP_REG_DMA_EN (1 << 5)
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#define SDMMCIP_REG_CTRL_SEND_AS_CCSD (1 << 10)
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#define SDMMCIP_REG_IDMAC_EN (1 << 25)
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#define SDMMCIP_REG_RESET_ALL (SDMMCIP_REG_CTRL_RESET | SDMMCIP_REG_CTRL_FIFO_RESET |\
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SDMMCIP_REG_CTRL_DMA_RESET)
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/* CMD register */
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#define SDMMCIP_REG_CMD_RESP_EXP (1 << 6)
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#define SDMMCIP_REG_CMD_RESP_LENGTH (1 << 7)
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#define SDMMCIP_REG_CMD_CHECK_CRC (1 << 8)
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#define SDMMCIP_REG_CMD_DATA_EXP (1 << 9)
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#define SDMMCIP_REG_CMD_RW (1 << 10)
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#define SDMMCIP_REG_CMD_SEND_STOP (1 << 12)
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#define SDMMCIP_REG_CMD_ABORT_STOP (1 << 14)
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#define SDMMCIP_REG_CMD_PRV_DAT_WAIT (1 << 13)
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#define SDMMCIP_REG_CMD_UPD_CLK (1 << 21)
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#define SDMMCIP_REG_CMD_USE_HOLD_REG (1 << 29)
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#define SDMMCIP_REG_CMD_START (1 << 31)
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/* CLKENA register */
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#define SDMMCIP_REG_CLKEN_ENABLE (1 << 0)
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#define SDMMCIP_REG_CLKEN_LOW_PWR (1 << 16)
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/* Card-type registe */
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#define SDMMCIP_REG_CTYPE_1BIT 0
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#define SDMMCIP_REG_CTYPE_4BIT (1 << 0)
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#define SDMMCIP_REG_CTYPE_8BIT (1 << 16)
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/* Status Register */
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#define SDMMCIP_REG_BUSY (1 << 9)
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#define SDMMCIP_REG_FIFO_FULL (1 << 3)
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#define SDMMCIP_REG_FIFO_EMPTY (1 << 2)
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#define SDMMCIP_REG_FIFO_COUNT_SHIFT (17)
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#define SDMMCIP_REG_FIFO_COUNT_MASK (0x1fff << SDMMCIP_REG_FIFO_COUNT_SHIFT)
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/* FIFOTH Register */
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#define MSIZE(x) ((x) << 28)
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#define RX_WMARK(x) ((x) << 16)
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#define TX_WMARK(x) (x)
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#define RX_WMARK_SHIFT 16
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#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
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#define SDMMCIP_REG_IDMAC_OWN (1 << 31)
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#define SDMMCIP_REG_IDMAC_CH (1 << 4)
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#define SDMMCIP_REG_IDMAC_FS (1 << 3)
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#define SDMMCIP_REG_IDMAC_LD (1 << 2)
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/* Bus Mode Register */
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#define SDMMCIP_REG_BMOD_IDMAC_RESET (1 << 0)
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#define SDMMCIP_REG_BMOD_IDMAC_FB (1 << 1)
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#define SDMMCIP_REG_BMOD_IDMAC_EN (1 << 7)
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/* UHS register */
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#define SDMMCIP_REG_DDR_MODE (1 << 16)
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/* quirks */
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#define SDMMCIP_REG_QUIRK_DISABLE_SMU (1 << 0)
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/* FIFO Register */
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#define SDMMCIP_REG_FIFO_OFFSET 0x200
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#endif /* __SDMMCIP_REG_HW_H */
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