432 lines
12 KiB
C
432 lines
12 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#if (CHIP_FLASH_CTRL_VER <= 1)
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#include "plat_types.h"
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#include "plat_addr_map.h"
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#include "reg_norflaship_v1.h"
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#include "hal_norflaship.h"
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#ifdef PROGRAMMER
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#include "task_schedule.h"
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#else
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#define TASK_SCHEDULE true
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#endif
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//====================================================================================
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// Flash IP Operations
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//====================================================================================
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/*
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Supported Command List (Based on GD25Q32C):
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parameter NOP = 8'h00 ;
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parameter WRR = 8'h01 ;
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parameter PP = 8'h02 ;
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parameter READ = 8'h03 ;
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parameter WRDI = 8'h04 ;
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parameter RDSR = 8'h05 ;
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parameter WREN = 8'h06 ;
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parameter FAST_READ = 8'h0B ;
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parameter P4E = 8'h20 ;
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parameter SE2 = 8'h20 ;
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parameter CLSR = 8'h30 ;
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parameter QPP = 8'h32 ;
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parameter RCR = 8'h35 ;
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parameter DOR = 8'h3B ;
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parameter P8E = 8'h40 ;
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parameter OTPP = 8'h42 ;
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parameter PSR = 8'h42 ;
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parameter ESR = 8'h44 ;
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parameter RSR = 8'h48 ;
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parameter OTPR = 8'h4B ;
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parameter BE32 = 8'h52 ;
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parameter CE = 8'h60 ;
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parameter QOR = 8'h6B ;
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parameter PES = 8'h75 ;
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parameter PER = 8'h7A ;
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parameter READ_ID = 8'h90 ;
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parameter RDID = 8'h9F ;
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parameter HPM = 8'hA3 ;
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parameter RES = 8'hAB ;
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parameter DP = 8'hB9 ;
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parameter DIOR = 8'hBB ;
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parameter BE = 8'hC7 ;
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parameter BE64 = 8'hD8 ;
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parameter SE = 8'hD8 ;
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parameter QIOWR = 8'hE7 ;
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parameter QIOR = 8'hEB ;
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parameter CRR = 8'hFF ;
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*/
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/* register memory address */
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#define NORFLASHIP_BASEADDR FLASH_CTRL_BASE
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#define norflaship_readb(a) \
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(*(volatile unsigned char*)(NORFLASHIP_BASEADDR+a))
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#define norflaship_read32(a) \
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(*(volatile unsigned int *)(NORFLASHIP_BASEADDR+a))
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#define norflaship_write32(v,a) \
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((*(volatile unsigned int *)(NORFLASHIP_BASEADDR+a)) = v)
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/* ip ops */
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uint8_t norflaship_continuous_read_mode_bit(uint8_t mode_bit)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(TX_CONFIG2_BASE);
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val &= ~(TX_MODBIT_MASK);
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val |= (mode_bit<<TX_MODBIT_SHIFT)&TX_MODBIT_MASK;
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norflaship_write32(val, TX_CONFIG2_BASE);
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return 0;
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}
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uint8_t norflaship_continuous_read_off(void)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(TX_CONFIG2_BASE);
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val &= ~(TX_CONMOD_MASK);
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norflaship_write32(val, TX_CONFIG2_BASE);
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return 0;
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}
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uint8_t norflaship_continuous_read_on(void)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(TX_CONFIG2_BASE);
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val |= (TX_CONMOD_MASK);
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norflaship_write32(val, TX_CONFIG2_BASE);
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return 0;
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}
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uint32_t norflaship_write_txfifo(const uint8_t *val, uint32_t len)
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{
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uint32_t i = 0;
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for (i = 0; i < len; ++i) {
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norflaship_write32(val[i], TXDATA_BASE);
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}
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return 0;
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}
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uint32_t norflaship_v1_write_txfifo_safe(const uint8_t *val, uint32_t len)
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{
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uint32_t i;
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uint32_t st;
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for (i = 0; i < len; ++i) {
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st = norflaship_read32(INT_STATUS_BASE);
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if (st & TXFIFOFULL_MASK) {
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break;
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}
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norflaship_write32(val[i], TXDATA_BASE);
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}
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return len - i;
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}
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uint32_t norflaship_v1_write_txfifo_all(const uint8_t *val, uint32_t len)
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{
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uint32_t st;
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while (len > 0) {
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st = norflaship_read32(INT_STATUS_BASE);
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if (st & TXFIFOFULL_MASK) {
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continue;
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}
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norflaship_write32(*val, TXDATA_BASE);
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val++;
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len--;
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}
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return 0;
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}
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uint8_t norflaship_read_rxfifo_count(void)
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{
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uint32_t val = 0;
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val = norflaship_readb(INT_STATUS_BASE);
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return ((val&RXFIFOCOUNT_MASK)>>RXFIFOCOUNT_SHIFT);
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}
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uint8_t norflaship_read_rxfifo(void)
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{
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uint32_t val = 0;
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val = norflaship_readb(RXDATA_BASE);
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return val&0xff;
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}
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void norflaship_blksize(uint32_t blksize)
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{
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uint32_t val = 0;
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val = norflaship_read32(TX_CONFIG2_BASE);
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val = ((~(TX_BLKSIZE_MASK))&val) | (blksize<<TX_BLKSIZE_SHIFT);
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norflaship_write32(val, TX_CONFIG2_BASE);
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}
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void norflaship_cmd_addr(uint8_t cmd, uint32_t address)
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{
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norflaship_busy_wait();
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norflaship_write32(address<<TX_ADDR_SHIFT|(cmd<<TX_CMD_SHIFT), TX_CONFIG1_BASE);
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}
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void norflaship_ext_tx_cmd(uint8_t cmd, uint32_t tx_len)
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{
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norflaship_busy_wait();
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norflaship_write32(cmd<<EXT_CMD_SHIFT, TX_CONFIG1_BASE);
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}
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void norflaship_ext_rx_cmd(uint8_t cmd, uint32_t tx_len, uint32_t rx_len)
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{
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norflaship_busy_wait();
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norflaship_blksize(rx_len);
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norflaship_write32(EXT_CMD_RX_MASK|(cmd<<EXT_CMD_SHIFT), TX_CONFIG1_BASE);
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}
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void norflaship_cmd_done(void)
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{
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norflaship_busy_wait();
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}
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void norflaship_rxfifo_count_wait(uint8_t cnt)
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{
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uint32_t st = 0;
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do {
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st = norflaship_read32(INT_STATUS_BASE);
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} while ((((st&RXFIFOCOUNT_MASK)>>RXFIFOCOUNT_SHIFT) < cnt) && TASK_SCHEDULE);
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}
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void norflaship_rxfifo_empty_wait(void)
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{
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uint32_t st = 0;
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do {
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st = norflaship_read32(INT_STATUS_BASE);
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} while ((st&RXFIFOEMPTY_MASK) && TASK_SCHEDULE);
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}
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void norflaship_busy_wait(void)
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{
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uint32_t st = 0;
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do {
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st = norflaship_read32(INT_STATUS_BASE);
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} while ((st&BUSY_MASK) && TASK_SCHEDULE);
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}
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int norflaship_is_busy(void)
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{
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uint32_t st = 0;
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st = norflaship_read32(INT_STATUS_BASE);
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return !!(st&BUSY_MASK);
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}
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void norflaship_clear_fifos(void)
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{
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norflaship_busy_wait();
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norflaship_write32(RXFIFOCLR_MASK|TXFIFOCLR_MASK, FIFO_CONFIG_BASE);
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norflaship_busy_wait();
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}
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void norflaship_clear_rxfifo(void)
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{
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norflaship_busy_wait();
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norflaship_write32(RXFIFOCLR_MASK, FIFO_CONFIG_BASE);
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norflaship_busy_wait();
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}
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void norflaship_clear_txfifo(void)
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{
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norflaship_busy_wait();
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norflaship_write32(TXFIFOCLR_MASK, FIFO_CONFIG_BASE);
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norflaship_busy_wait();
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}
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void norflaship_div(uint32_t div)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(MODE1_CONFIG_BASE);
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val = (~(CLKDIV_MASK) & val) | (div<<CLKDIV_SHIFT);
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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uint32_t norflaship_get_div(void)
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{
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uint32_t val = 0;
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val = norflaship_read32(MODE1_CONFIG_BASE);
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return (val & CLKDIV_MASK) >> CLKDIV_SHIFT;
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}
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void norflaship_cmdquad(uint32_t v)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(MODE1_CONFIG_BASE);
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if (v)
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val |= CMDQUAD_MASK;
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else
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val &= ~CMDQUAD_MASK;
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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uint32_t norflaship_get_pos_neg(void)
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{
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uint32_t val = 0;
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val = norflaship_read32(MODE1_CONFIG_BASE);
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return !!(val & POS_NEG_MASK);
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}
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void norflaship_pos_neg(uint32_t v)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(MODE1_CONFIG_BASE);
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if (v)
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val |= POS_NEG_MASK;
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else
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val &= ~POS_NEG_MASK;
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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uint32_t norflaship_get_neg_phase(void)
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{
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uint32_t val = 0;
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val = norflaship_read32(MODE1_CONFIG_BASE);
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return !!(val & NEG_PHASE_MASK);
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}
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void norflaship_neg_phase(uint32_t v)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(MODE1_CONFIG_BASE);
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if (v)
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val |= NEG_PHASE_MASK;
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else
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val &= ~NEG_PHASE_MASK;
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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uint32_t norflaship_get_samdly(void)
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{
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uint32_t val = 0;
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val = norflaship_read32(MODE1_CONFIG_BASE);
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return (val & SAMDLY_MASK) >> SAMDLY_SHIFT;
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}
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void norflaship_samdly(uint32_t v)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(MODE1_CONFIG_BASE);
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val = (~(SAMDLY_MASK) & val) | (v<<SAMDLY_SHIFT);
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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void norflaship_dual_mode(uint32_t v)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(MODE1_CONFIG_BASE);
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if (v)
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val |= DUALMODE_MASK;
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else
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val &= ~DUALMODE_MASK;
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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void norflaship_hold_pin(uint32_t v)
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{
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uint32_t val = 0;
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val = norflaship_read32(MODE1_CONFIG_BASE);
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if (v)
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val |= HOLDPIN_MASK;
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else
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val &= ~HOLDPIN_MASK;
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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void norflaship_wpr_pin(uint32_t v)
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{
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uint32_t val = 0;
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val = norflaship_read32(MODE1_CONFIG_BASE);
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if (v)
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val |= WPRPIN_MASK;
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else
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val &= ~WPRPIN_MASK;
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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void norflaship_quad_mode(uint32_t v)
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{
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uint32_t val = 0;
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norflaship_busy_wait();
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val = norflaship_read32(MODE1_CONFIG_BASE);
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if (v)
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val |= QUADMODE_MASK;
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else
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val &= ~QUADMODE_MASK;
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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void norflaship_dummyclc(uint32_t v)
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{
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uint32_t val = 0;
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val = norflaship_read32(MODE1_CONFIG_BASE);
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val = (~(DUMMYCLC_MASK) & val) | (v<<DUMMYCLC_SHIFT);
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norflaship_write32(val, MODE1_CONFIG_BASE);
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}
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void norflaship_dummyclcen(uint32_t v)
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||
|
|
{
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||
|
|
uint32_t val = 0;
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||
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|
val = norflaship_read32(MODE1_CONFIG_BASE);
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||
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|
if (v)
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||
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|
val |= DUMMYCLCEN_MASK;
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||
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else
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|
val &= ~DUMMYCLCEN_MASK;
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||
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norflaship_write32(val, MODE1_CONFIG_BASE);
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||
|
|
}
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||
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|
void norflaship_addrbyte4(uint32_t v)
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||
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|
{
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||
|
|
uint32_t val = 0;
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||
|
|
val = norflaship_read32(MODE1_CONFIG_BASE);
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||
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|
if (v)
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||
|
|
val |= ADDRBYTE4_MASK;
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||
|
|
else
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||
|
|
val &= ~ADDRBYTE4_MASK;
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||
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|
norflaship_write32(val, MODE1_CONFIG_BASE);
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||
|
|
}
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||
|
|
void norflaship_ruen(uint32_t v)
|
||
|
|
{
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||
|
|
uint32_t val = 0;
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||
|
|
val = norflaship_read32(PULL_UP_DOWN_CONFIG_BASE);
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||
|
|
val = (~(SPIRUEN_MASK) & val) | (v<<SPIRUEN_SHIFT);
|
||
|
|
norflaship_write32(val, PULL_UP_DOWN_CONFIG_BASE);
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||
|
|
}
|
||
|
|
void norflaship_rden(uint32_t v)
|
||
|
|
{
|
||
|
|
uint32_t val = 0;
|
||
|
|
val = norflaship_read32(PULL_UP_DOWN_CONFIG_BASE);
|
||
|
|
val = (~(SPIRDEN_MASK) & val) | (v<<SPIRDEN_SHIFT);
|
||
|
|
norflaship_write32(val, PULL_UP_DOWN_CONFIG_BASE);
|
||
|
|
}
|
||
|
|
void norflaship_dualiocmd(uint32_t v)
|
||
|
|
{
|
||
|
|
uint32_t val = 0;
|
||
|
|
val = norflaship_read32(MODE2_CONFIG_BASE);
|
||
|
|
val = (~(DUALIOCMD_MASK) & val) | (v<<DUALIOCMD_SHIFT);
|
||
|
|
norflaship_write32(val, MODE2_CONFIG_BASE);
|
||
|
|
}
|
||
|
|
void norflaship_rdcmd(uint32_t v)
|
||
|
|
{
|
||
|
|
uint32_t val = 0;
|
||
|
|
val = norflaship_read32(MODE2_CONFIG_BASE);
|
||
|
|
val = (~(RDCMD_MASK) & val) | (v<<RDCMD_SHIFT);
|
||
|
|
norflaship_write32(val, MODE2_CONFIG_BASE);
|
||
|
|
}
|
||
|
|
void norflaship_frdcmd(uint32_t v)
|
||
|
|
{
|
||
|
|
uint32_t val = 0;
|
||
|
|
val = norflaship_read32(MODE2_CONFIG_BASE);
|
||
|
|
val = (~(FRDCMD_MASK) & val) | (v<<FRDCMD_SHIFT);
|
||
|
|
norflaship_write32(val, MODE2_CONFIG_BASE);
|
||
|
|
}
|
||
|
|
void norflaship_qrdcmd(uint32_t v)
|
||
|
|
{
|
||
|
|
uint32_t val = 0;
|
||
|
|
val = norflaship_read32(MODE2_CONFIG_BASE);
|
||
|
|
val = (~(QRDCMDBIT_MASK) & val) | (v<<QRDCMDBIT_SHIFT);
|
||
|
|
norflaship_write32(val, MODE2_CONFIG_BASE);
|
||
|
|
}
|
||
|
|
uint32_t norflaship_get_rdcmd(void)
|
||
|
|
{
|
||
|
|
uint32_t val;
|
||
|
|
val = norflaship_read32(MODE2_CONFIG_BASE);
|
||
|
|
return ((RDCMD_MASK & val) >> RDCMD_SHIFT);
|
||
|
|
}
|
||
|
|
void norflaship_sleep(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
void norflaship_wakeup(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|