556 lines
16 KiB
C
556 lines
16 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_addr_map.h"
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#ifdef BT_CMU_BASE
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#include "hal_intersys.h"
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#include "hal_trace.h"
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#include "hal_sleep.h"
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#include CHIP_SPECIFIC_HDR(reg_cmu)
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#include CHIP_SPECIFIC_HDR(reg_btcmu)
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#include "cmsis_nvic.h"
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#include "hal_timer.h"
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#ifdef TX_RX_PCM_MASK
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#include "hal_chipid.h"
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#endif
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#ifdef CHIP_BEST1400
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#define PEER_IRQ_AUTO_CLEAR
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#endif
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#define MAX_SEND_RECORD_COUNT 3
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// MCU-CMU ISIRQ_SET
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#define CMU_BT2MCU_DATA_DONE_SET (1 << 0)
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#define CMU_BT2MCU_DATA1_DONE_SET (1 << 1)
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#define CMU_MCU2BT_DATA_IND_SET (1 << 2)
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#define CMU_MCU2BT_DATA1_IND_SET (1 << 3)
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// MCU-CMU ISIRQ_CLR
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#define CMU_BT2MCU_DATA_DONE_CLR (1 << 0)
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#define CMU_BT2MCU_DATA1_DONE_CLR (1 << 1)
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#define CMU_MCU2BT_DATA_IND_CLR (1 << 2)
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#define CMU_MCU2BT_DATA1_IND_CLR (1 << 3)
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// BT-CMU ISIRQ_SET
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#define BTCMU_MCU2BT_DATA_DONE_SET (1 << 0)
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#define BTCMU_MCU2BT_DATA1_DONE_SET (1 << 1)
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#define BTCMU_BT2MCU_DATA_IND_SET (1 << 2)
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#define BTCMU_BT2MCU_DATA1_IND_SET (1 << 3)
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// BT-CMU ISIRQ_CLR
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#define BTCMU_MCU2BT_DATA_DONE_CLR (1 << 0)
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#define BTCMU_MCU2BT_DATA1_DONE_CLR (1 << 1)
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#define BTCMU_BT2MCU_DATA_IND_CLR (1 << 2)
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#define BTCMU_BT2MCU_DATA1_IND_CLR (1 << 3)
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enum HAL_INTERSYS_IRQ_TYPE_T {
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HAL_INTERSYS_IRQ_SEND_IND,
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HAL_INTERSYS_IRQ_RECV_DONE,
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HAL_INTERSYS_IRQ_TYPE_QTY
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};
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struct HAL_INTERSYS_MSG_T {
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struct HAL_INTERSYS_MSG_T *next; // pointer to next element in the list
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enum HAL_INTERSYS_MSG_TYPE_T type; // message type
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unsigned int len; // message data length in bytes
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const unsigned char *data; // pointer to the message data
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};
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struct HAL_INTERSYS_SEND_RECORD_T {
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struct HAL_INTERSYS_MSG_T msg;
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bool in_use;
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};
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static const IRQn_Type rx_irq_id[HAL_INTERSYS_ID_QTY] = {
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ISDATA_IRQn,
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ISDATA1_IRQn,
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};
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static const IRQn_Type tx_irq_id[HAL_INTERSYS_ID_QTY] = {
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ISDONE_IRQn,
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ISDONE1_IRQn,
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};
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static struct HAL_INTERSYS_MSG_T *** const bt_recv_msg_list_ppp[HAL_INTERSYS_ID_QTY] = {
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(struct HAL_INTERSYS_MSG_T ***)(BT_RAM_BASE + BT_INTESYS_MEM_OFFSET + 0x4),
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(struct HAL_INTERSYS_MSG_T ***)(BT_RAM_BASE+ BT_INTESYS_MEM_OFFSET + 0xC),
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};
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static struct HAL_INTERSYS_MSG_T ** const recv_msg_list_p[HAL_INTERSYS_ID_QTY] = {
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(struct HAL_INTERSYS_MSG_T **)(BT_RAM_BASE + BT_INTESYS_MEM_OFFSET),
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(struct HAL_INTERSYS_MSG_T **)(BT_RAM_BASE + BT_INTESYS_MEM_OFFSET + 0x8),
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};
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static struct HAL_INTERSYS_MSG_T * send_msg_list_p[HAL_INTERSYS_ID_QTY];
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static struct HAL_INTERSYS_MSG_T * send_pending_list_p[HAL_INTERSYS_ID_QTY];
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static struct HAL_INTERSYS_MSG_T recv_pending_head[HAL_INTERSYS_ID_QTY];
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static struct HAL_INTERSYS_SEND_RECORD_T send_msgs[HAL_INTERSYS_ID_QTY][MAX_SEND_RECORD_COUNT];
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static HAL_INTERSYS_RX_IRQ_HANDLER rx_irq_handler[HAL_INTERSYS_ID_QTY][HAL_INTERSYS_MSG_TYPE_QTY];
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static HAL_INTERSYS_TX_IRQ_HANDLER tx_irq_handler[HAL_INTERSYS_ID_QTY][HAL_INTERSYS_MSG_TYPE_QTY];
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static uint8_t chan_opened[HAL_INTERSYS_ID_QTY] = { 0, 0, };
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STATIC_ASSERT(sizeof(chan_opened[0]) * 8 >= HAL_INTERSYS_MSG_TYPE_QTY, "chan_opened size too small");
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static bool need_flow_ctrl[HAL_INTERSYS_ID_QTY] = { false, false, };
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static bool chan_busy[HAL_INTERSYS_ID_QTY] = { false, false, };
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static bool busy_now = false;
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#ifdef PEER_IRQ_AUTO_CLEAR
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static bool peer_irq_auto_clear;
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#endif
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static struct CMU_T * const cmu = (struct CMU_T *)CMU_BASE;
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static struct BTCMU_T * const btcmu = (struct BTCMU_T *)BT_CMU_BASE;
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static void hal_intersys_busy(enum HAL_INTERSYS_ID_T id, bool busy)
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{
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int i;
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bool new_state;
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if (chan_busy[id] == busy) {
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return;
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}
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chan_busy[id] = busy;
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if (busy_now == busy) {
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return;
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}
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if (busy) {
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hal_sys_wake_lock(HAL_SYS_WAKE_LOCK_USER_INTERSYS);
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busy_now = true;
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} else {
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new_state = false;
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for (i = 0; i < HAL_INTERSYS_ID_QTY; i++) {
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if (chan_busy[i]) {
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new_state = true;
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break;
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}
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}
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if (!new_state) {
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hal_sys_wake_unlock(HAL_SYS_WAKE_LOCK_USER_INTERSYS);
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busy_now = false;
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}
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}
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}
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#ifdef PEER_IRQ_AUTO_CLEAR
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void hal_intersys_peer_irq_auto_clear(bool enable)
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{
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peer_irq_auto_clear = enable;
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}
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#endif
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static int hal_intersys_peer_irq_set(enum HAL_INTERSYS_ID_T id, enum HAL_INTERSYS_IRQ_TYPE_T type)
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{
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uint32_t value;
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if (id == HAL_INTERSYS_ID_0) {
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if (type == HAL_INTERSYS_IRQ_SEND_IND) {
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value = CMU_MCU2BT_DATA_IND_SET;
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} else {
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value = CMU_BT2MCU_DATA_DONE_SET;
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}
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} else {
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if (type == HAL_INTERSYS_IRQ_SEND_IND) {
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value = CMU_MCU2BT_DATA1_IND_SET;
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} else {
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value = CMU_BT2MCU_DATA1_DONE_SET;
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}
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}
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#ifdef PEER_IRQ_AUTO_CLEAR
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uint32_t ret;
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ret = int_lock();
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cmu->ISIRQ_SET = value;
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if (peer_irq_auto_clear) {
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if (CMU_MCU2BT_DATA_IND_SET == value) {
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cmu->ISIRQ_CLR |= CMU_MCU2BT_DATA_IND_CLR;
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} else {
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cmu->ISIRQ_CLR |= CMU_BT2MCU_DATA_DONE_CLR;
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}
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hal_sys_timer_delay(MS_TO_TICKS(2));
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}
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int_unlock(ret);
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#else
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cmu->ISIRQ_SET = value;
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#endif
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return 0;
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}
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static inline void btcmu_reg_update_wait(void)
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{
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// Make sure BTCMU (26M clock domain) write opertions finish before return
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btcmu->ISIRQ_CLR;
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}
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static int hal_intersys_local_irq_clear(enum HAL_INTERSYS_ID_T id, enum HAL_INTERSYS_IRQ_TYPE_T type)
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{
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uint32_t value;
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if (id == HAL_INTERSYS_ID_0) {
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if (type == HAL_INTERSYS_IRQ_SEND_IND) {
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value = BTCMU_BT2MCU_DATA_IND_CLR;
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} else {
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value = BTCMU_MCU2BT_DATA_DONE_CLR;
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}
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} else {
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if (type == HAL_INTERSYS_IRQ_SEND_IND) {
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value = BTCMU_BT2MCU_DATA1_IND_CLR;
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} else {
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value = BTCMU_MCU2BT_DATA1_DONE_CLR;
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}
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}
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btcmu->ISIRQ_CLR = value;
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btcmu_reg_update_wait();
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return 0;
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}
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static int hal_intersys_local_irq_set(enum HAL_INTERSYS_ID_T id, enum HAL_INTERSYS_IRQ_TYPE_T type)
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{
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uint32_t value;
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if (id == HAL_INTERSYS_ID_0) {
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if (type == HAL_INTERSYS_IRQ_SEND_IND) {
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value = BTCMU_BT2MCU_DATA_IND_SET;
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} else {
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value = BTCMU_MCU2BT_DATA_DONE_SET;
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}
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} else {
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if (type == HAL_INTERSYS_IRQ_SEND_IND) {
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value = BTCMU_BT2MCU_DATA1_IND_SET;
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} else {
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value = BTCMU_MCU2BT_DATA1_DONE_SET;
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}
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}
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btcmu->ISIRQ_SET = value;
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btcmu_reg_update_wait();
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return 0;
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}
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//static void hal_intersys_wait_done_idle(void)
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//{
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// while(hal_cmu_get_address()->ISIRQ_SET & (CMU_BT2MCU_DATA_DONE_SET |CMU_BT2MCU_DATA1_DONE_SET));
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//}
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//static void hal_intersys_wait_data_idle(void)
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//{
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// while(hal_cmu_get_address()->ISIRQ_SET & (CMU_MCU2BT_DATA_IND_SET |CMU_MCU2BT_DATA1_IND_SET));
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//}
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debug_intersys_type g_debug_intersys;
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static void hal_intersys_rx_irq(void)
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{
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int id;
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struct HAL_INTERSYS_MSG_T *msg_ptr;
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enum HAL_INTERSYS_MSG_TYPE_T type;
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unsigned int processed;
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if (g_debug_intersys.cmd_opcode != 0xFFFF){
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g_debug_intersys.irq_happen += 1;
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}
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for (id = HAL_INTERSYS_ID_0; id < HAL_INTERSYS_ID_QTY; id++) {
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if (NVIC_GetActive(rx_irq_id[id])) {
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hal_intersys_local_irq_clear(id, HAL_INTERSYS_IRQ_SEND_IND);
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if (recv_pending_head[id].data) {
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// Previous unprocessed message
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msg_ptr = &recv_pending_head[id];
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} else {
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// New message
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msg_ptr = *recv_msg_list_p[id];
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}
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while (msg_ptr) {
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type = msg_ptr->type;
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if (type >= HAL_INTERSYS_MSG_TYPE_QTY) {
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// Error
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ASSERT(false, "INTERSYS-RX: Invalid msg type: %d", type);
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break;
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}
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if (rx_irq_handler[id][type]) {
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processed = rx_irq_handler[id][type](msg_ptr->data, msg_ptr->len);
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// Check if flow control needed
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if (processed < msg_ptr->len) {
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recv_pending_head[id].next = msg_ptr->next;
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recv_pending_head[id].type = msg_ptr->type;
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recv_pending_head[id].len = msg_ptr->len - processed;
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recv_pending_head[id].data = msg_ptr->data + processed;
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break;
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}
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} else {
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// Error
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ASSERT(false, "INTERSYS-RX: Handler missing");
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break;
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}
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msg_ptr = msg_ptr->next;
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}
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if (msg_ptr == NULL) {
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if (!need_flow_ctrl[id]){
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hal_intersys_peer_irq_set(id, HAL_INTERSYS_IRQ_RECV_DONE);
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}
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recv_pending_head[id].data = NULL;
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}
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}
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}
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}
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static void hal_intersys_tx_irq(void)
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{
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int id;
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struct HAL_INTERSYS_MSG_T *msg_ptr;
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enum HAL_INTERSYS_MSG_TYPE_T type;
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for (id = HAL_INTERSYS_ID_0; id < HAL_INTERSYS_ID_QTY; id++) {
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if (NVIC_GetActive(tx_irq_id[id])) {
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hal_intersys_local_irq_clear(id, HAL_INTERSYS_IRQ_RECV_DONE);
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msg_ptr = send_msg_list_p[id];
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while (msg_ptr) {
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type = msg_ptr->type;
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if (type >= HAL_INTERSYS_MSG_TYPE_QTY) {
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// Error
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ASSERT(false, "INTERSYS-TX: Invalid msg type: %d", type);
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break;
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}
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if (tx_irq_handler[id][type]) {
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tx_irq_handler[id][type](msg_ptr->data, msg_ptr->len);
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};
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CONTAINER_OF(msg_ptr, struct HAL_INTERSYS_SEND_RECORD_T, msg)->in_use = false;
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msg_ptr = msg_ptr->next;
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}
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|
|
||
|
|
if (send_pending_list_p[id]) {
|
||
|
|
send_msg_list_p[id] = send_pending_list_p[id];
|
||
|
|
send_pending_list_p[id] = NULL;
|
||
|
|
hal_intersys_peer_irq_set(id, HAL_INTERSYS_IRQ_SEND_IND);
|
||
|
|
} else {
|
||
|
|
send_msg_list_p[id] = NULL;
|
||
|
|
// Allow sleep
|
||
|
|
hal_intersys_busy(id, false);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_intersys_open(enum HAL_INTERSYS_ID_T id, enum HAL_INTERSYS_MSG_TYPE_T type,
|
||
|
|
HAL_INTERSYS_RX_IRQ_HANDLER rxhandler, HAL_INTERSYS_TX_IRQ_HANDLER txhandler, bool rx_flowctrl)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (id >= HAL_INTERSYS_ID_QTY) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
if (type >= HAL_INTERSYS_MSG_TYPE_QTY) {
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (chan_opened[id] == 0) {
|
||
|
|
if (id == HAL_INTERSYS_ID_0) {
|
||
|
|
cmu->ISIRQ_CLR = CMU_BT2MCU_DATA_DONE_CLR | CMU_MCU2BT_DATA_IND_CLR;
|
||
|
|
} else {
|
||
|
|
cmu->ISIRQ_CLR = CMU_BT2MCU_DATA1_DONE_CLR | CMU_MCU2BT_DATA1_IND_CLR;
|
||
|
|
}
|
||
|
|
*bt_recv_msg_list_ppp[id] = &send_msg_list_p[id];
|
||
|
|
|
||
|
|
NVIC_SetVector(rx_irq_id[id], (uint32_t)hal_intersys_rx_irq);
|
||
|
|
NVIC_SetPriority(rx_irq_id[id], IRQ_PRIORITY_NORMAL);
|
||
|
|
|
||
|
|
NVIC_SetVector(tx_irq_id[id], (uint32_t)hal_intersys_tx_irq);
|
||
|
|
NVIC_SetPriority(tx_irq_id[id], IRQ_PRIORITY_NORMAL);
|
||
|
|
|
||
|
|
// Stop IRQs by default
|
||
|
|
NVIC_DisableIRQ(rx_irq_id[id]);
|
||
|
|
NVIC_DisableIRQ(tx_irq_id[id]);
|
||
|
|
|
||
|
|
send_msg_list_p[id] = NULL;
|
||
|
|
send_pending_list_p[id] = NULL;
|
||
|
|
recv_pending_head[id].data = NULL;
|
||
|
|
for (i = 0; i < MAX_SEND_RECORD_COUNT; i++) {
|
||
|
|
send_msgs[id][i].in_use = false;
|
||
|
|
}
|
||
|
|
need_flow_ctrl[id] = rx_flowctrl;
|
||
|
|
} else {
|
||
|
|
ASSERT(need_flow_ctrl[id] == rx_flowctrl, "INTERSYS-OPEN: rx_flowctrl=%d (should be %d)", rx_flowctrl, need_flow_ctrl[id]);
|
||
|
|
return 3;
|
||
|
|
}
|
||
|
|
chan_opened[id] |= (1 << type);
|
||
|
|
|
||
|
|
rx_irq_handler[id][type] = rxhandler;
|
||
|
|
tx_irq_handler[id][type] = txhandler;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_intersys_close(enum HAL_INTERSYS_ID_T id,enum HAL_INTERSYS_MSG_TYPE_T type)
|
||
|
|
{
|
||
|
|
if (id >= HAL_INTERSYS_ID_QTY) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
chan_opened[id] &= ~(1 << type);
|
||
|
|
rx_irq_handler[id][type] = NULL;
|
||
|
|
tx_irq_handler[id][type] = NULL;
|
||
|
|
|
||
|
|
if (chan_opened[id] == 0) {
|
||
|
|
// Stop IRQs by default
|
||
|
|
NVIC_DisableIRQ(rx_irq_id[id]);
|
||
|
|
NVIC_DisableIRQ(tx_irq_id[id]);
|
||
|
|
|
||
|
|
send_msg_list_p[id] = NULL;
|
||
|
|
send_pending_list_p[id] = NULL;
|
||
|
|
recv_pending_head[id].data = NULL;
|
||
|
|
need_flow_ctrl[id] = false;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_intersys_start_recv(enum HAL_INTERSYS_ID_T id)
|
||
|
|
{
|
||
|
|
if (id >= HAL_INTERSYS_ID_QTY) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
NVIC_EnableIRQ(rx_irq_id[id]);
|
||
|
|
// Check if there is any previous unprocessed message
|
||
|
|
if (recv_pending_head[id].data) {
|
||
|
|
hal_intersys_local_irq_set(id, HAL_INTERSYS_IRQ_SEND_IND);
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_intersys_stop_recv(enum HAL_INTERSYS_ID_T id)
|
||
|
|
{
|
||
|
|
if (id >= HAL_INTERSYS_ID_QTY) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
NVIC_DisableIRQ(rx_irq_id[id]);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_intersys_send(enum HAL_INTERSYS_ID_T id, enum HAL_INTERSYS_MSG_TYPE_T type,
|
||
|
|
const unsigned char *data, unsigned int len)
|
||
|
|
{
|
||
|
|
uint32_t lock;
|
||
|
|
int ret;
|
||
|
|
struct HAL_INTERSYS_SEND_RECORD_T *record;
|
||
|
|
struct HAL_INTERSYS_MSG_T *next;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (id >= HAL_INTERSYS_ID_QTY) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
if (type >= HAL_INTERSYS_MSG_TYPE_QTY) {
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
if ((chan_opened[id] & (1 << type)) == 0) {
|
||
|
|
return 3;
|
||
|
|
}
|
||
|
|
|
||
|
|
NVIC_EnableIRQ(tx_irq_id[id]);
|
||
|
|
|
||
|
|
ret = -1;
|
||
|
|
record = &send_msgs[id][0];
|
||
|
|
|
||
|
|
lock = int_lock();
|
||
|
|
for (i = 0; i < MAX_SEND_RECORD_COUNT; i++) {
|
||
|
|
if (record->in_use) {
|
||
|
|
record++;
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
record->in_use = true;
|
||
|
|
record->msg.next = NULL;
|
||
|
|
record->msg.type = type;
|
||
|
|
record->msg.len = len;
|
||
|
|
record->msg.data = data;
|
||
|
|
if (send_msg_list_p[id] == NULL) {
|
||
|
|
send_msg_list_p[id] = &record->msg;
|
||
|
|
hal_intersys_peer_irq_set(id, HAL_INTERSYS_IRQ_SEND_IND);
|
||
|
|
} else if (send_pending_list_p[id] == NULL) {
|
||
|
|
send_pending_list_p[id] = &record->msg;
|
||
|
|
} else {
|
||
|
|
next = send_pending_list_p[id];
|
||
|
|
while (next->next) {
|
||
|
|
next = next->next;
|
||
|
|
}
|
||
|
|
next->next = &record->msg;
|
||
|
|
}
|
||
|
|
ret = 0;
|
||
|
|
// Prohibit sleep here
|
||
|
|
hal_intersys_busy(id, true);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
int_unlock(lock);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void hal_intersys_rx_done(enum HAL_INTERSYS_ID_T id)
|
||
|
|
{
|
||
|
|
hal_intersys_peer_irq_set(id, HAL_INTERSYS_IRQ_RECV_DONE);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef TX_RX_PCM_MASK
|
||
|
|
static FRAME2BUFF_HANDLER DecQ;
|
||
|
|
|
||
|
|
void hal_intersys_mic_rx_irq()
|
||
|
|
{
|
||
|
|
int id;
|
||
|
|
id = HAL_INTERSYS_ID_1;
|
||
|
|
if(NVIC_GetActive(rx_irq_id[id]))
|
||
|
|
{
|
||
|
|
hal_intersys_local_irq_clear(id, HAL_INTERSYS_IRQ_SEND_IND);
|
||
|
|
//TRACE(0,"HAL_INTERSYS_ID_1 CLEAR");
|
||
|
|
//output data to buff
|
||
|
|
DecQ();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_intersys_mic_open(enum HAL_INTERSYS_ID_T id, FRAME2BUFF_HANDLER dch)
|
||
|
|
{
|
||
|
|
// if(btdrv_is_pcm_mask_enable()==1)
|
||
|
|
{
|
||
|
|
DecQ= dch;
|
||
|
|
NVIC_EnableIRQ(rx_irq_id[id]);
|
||
|
|
if(id == HAL_INTERSYS_ID_1)
|
||
|
|
{
|
||
|
|
cmu->ISIRQ_CLR = CMU_BT2MCU_DATA1_DONE_CLR | CMU_MCU2BT_DATA1_IND_CLR;
|
||
|
|
NVIC_SetVector(rx_irq_id[id], (uint32_t)hal_intersys_mic_rx_irq);
|
||
|
|
NVIC_SetPriority(rx_irq_id[id], IRQ_PRIORITY_NORMAL);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|