316 lines
11 KiB
C
316 lines
11 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "hal_i2s.h"
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#include "hal_trace.h"
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#include "hal_dma.h"
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#include "hal_i2s_tdm.h"
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#if 0
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#define I2S_TDM_TRACE TRACE
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#define I2S_TDM_DUMP8 DUMP8
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#else
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#define I2S_TDM_TRACE(n, str, ...)
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#define I2S_TDM_DUMP8(str, ...)
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#endif
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#define I2S_TDM_FRAME_SIZE_MAX 512
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#define I2S_TDM_TX_FRAME_NUM 2
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#define I2S_TDM_TX_FRAME_SIZE I2S_TDM_FRAME_SIZE_MAX/16
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static struct HAL_DMA_DESC_T i2s_tdm_tx_dma_desc[HAL_I2S_ID_QTY][I2S_TDM_TX_FRAME_NUM];
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static uint16_t I2S_TDM_BUF_ALIGN i2s_tdm_tx_buf[HAL_I2S_ID_QTY][I2S_TDM_TX_FRAME_NUM][I2S_TDM_TX_FRAME_SIZE];
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static struct HAL_DMA_CH_CFG_T tx_dma_cfg[HAL_I2S_ID_QTY];
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static struct HAL_I2S_TDM_CONFIG_T i2s_tdm_cfg[HAL_I2S_ID_QTY];
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static inline bool i2s_tdm_cycles_in_arrays(uint16_t cycles)
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{
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if(cycles == (uint16_t)HAL_I2S_TDM_CYCLES_16
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|| cycles == (uint16_t)HAL_I2S_TDM_CYCLES_32
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|| cycles == (uint16_t)HAL_I2S_TDM_CYCLES_64
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|| cycles == (uint16_t)HAL_I2S_TDM_CYCLES_128
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|| cycles == (uint16_t)HAL_I2S_TDM_CYCLES_256
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|| cycles == (uint16_t)HAL_I2S_TDM_CYCLES_512
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)
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return true;
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else
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return false;
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}
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static inline bool i2s_tdm_fs_cycles_in_arrays(uint16_t fs_cycles)
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{
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if(fs_cycles == (uint16_t)HAL_I2S_TDM_FS_CYCLES_1
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|| fs_cycles == (uint16_t)HAL_TDM_FS_CYCLES_8
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|| fs_cycles == (uint16_t)HAL_I2S_TDM_FS_CYCLES_16
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|| fs_cycles == (uint16_t)HAL_I2S_TDM_FS_CYCLES_32
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|| fs_cycles == (uint16_t)HAL_I2S_TDM_FS_CYCLES_64
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|| fs_cycles == (uint16_t)HAL_I2S_TDM_FS_CYCLES_128
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|| fs_cycles == (uint16_t)HAL_I2S_TDM_FS_CYCLES_256
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|| fs_cycles == (uint16_t)HAL_I2S_TDM_FS_CYCLES_ONE_LESS)
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return true;
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else
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return false;
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}
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static inline bool i2s_tdm_slot_cycles_in_arrays(uint8_t slot_cycles)
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{
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if(slot_cycles == (uint8_t)HAL_I2S_TDM_SLOT_CYCLES_16
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|| slot_cycles == (uint8_t)HAL_I2S_TDM_SLOT_CYCLES_32)
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return true;
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else
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return false;
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}
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static void i2s_tdm0_tx_handler(uint8_t chan, uint32_t remains, uint32_t error, struct HAL_DMA_DESC_T *lli)
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{
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#if 0
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static int cnt = 0;
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cnt++;
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if (cnt % 600 == 0)
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{
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I2S_TDM_TRACE(4,"I2S_TDM0-TX: remains=%ld, error=%ld, cnt=%d,tx_buff_len = %d.", remains, error, cnt,sizeof(i2s_tdm_tx_buf[HAL_I2S_ID_0]));
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I2S_TDM_DUMP8("0x%x,",i2s_tdm_tx_buf[HAL_I2S_ID_0],sizeof(i2s_tdm_tx_buf[HAL_I2S_ID_0]) <= 32 ? sizeof(i2s_tdm_tx_buf[HAL_I2S_ID_0]) : 32 );
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}
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#endif
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}
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static void i2s_tdm1_tx_handler(uint8_t chan, uint32_t remains, uint32_t error, struct HAL_DMA_DESC_T *lli)
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{
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#if 0
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static int cnt = 0;
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cnt++;
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if (cnt % 600 == 0) {
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I2S_TDM_TRACE(4,"I2S_TDM1-TX: remains=%ld, error=%ld, cnt=%d,tx_buff_len = %d.", remains, error, cnt,sizeof(i2s_tdm_tx_buf[HAL_I2S_ID_1]));
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I2S_TDM_DUMP8("0x%x,",i2s_tdm_tx_buf[HAL_I2S_ID_1],sizeof(i2s_tdm_tx_buf[HAL_I2S_ID_1]) <= 32 ? sizeof(i2s_tdm_tx_buf[HAL_I2S_ID_1]) : 32 );
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}
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#endif
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}
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int32_t hal_i2s_tdm_open(enum HAL_I2S_ID_T i2s_id,enum HAL_I2S_MODE_T mode)
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{
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int ret;
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I2S_TDM_TRACE(3,"%s: i2s_id = %d,mode = %d.", __func__, i2s_id, mode);
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ASSERT(i2s_id < HAL_I2S_ID_QTY,"%s: i2s_id = %d!", __func__, i2s_id);
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// i2s open playback and capture.
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ret = hal_i2s_open(i2s_id, AUD_STREAM_PLAYBACK, mode);
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if(ret)
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{
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I2S_TDM_TRACE(2,"%s: hal_i2s_open playback failed.ret = %d.", __func__, ret);
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goto __func_fail;
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}
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ret = hal_i2s_open(i2s_id, AUD_STREAM_CAPTURE, mode);
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if(ret)
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{
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I2S_TDM_TRACE(2,"%s: hal_i2s_open capture failed.ret = %d.", __func__, ret);
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goto __func_fail;
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}
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I2S_TDM_TRACE(1,"%s done.", __func__);
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return 0;
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__func_fail:
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I2S_TDM_TRACE(2,"%s failed. ret = %d.", __func__, ret);
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return ret;
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}
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int32_t hal_i2s_tdm_setup(enum HAL_I2S_ID_T i2s_id,
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uint32_t sample_rate,
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struct HAL_I2S_TDM_CONFIG_T *i2s_tdm_cfg)
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{
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int i,j,m,n;
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int ret;
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struct HAL_I2S_CONFIG_T i2s_cfg;
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uint16_t *buf;
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uint32_t cycles;
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uint32_t fs_cycles;
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uint32_t slot_cycles;
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uint32_t fs_remain;
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I2S_TDM_TRACE(3,"%s: i2s_id = %d,sample_rate = %d.", __func__, i2s_id, sample_rate);
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ASSERT(i2s_id < HAL_I2S_ID_QTY,"%s: i2s_id = %d!", __func__, i2s_id);
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ASSERT(i2s_tdm_cycles_in_arrays(i2s_tdm_cfg->cycles),
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"%s: cycles(%d) error!", __func__, i2s_tdm_cfg->cycles);
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ASSERT(i2s_tdm_fs_cycles_in_arrays(i2s_tdm_cfg->fs_cycles),
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"%s: fs_cycles(%d) error!", __func__, i2s_tdm_cfg->fs_cycles);
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ASSERT(i2s_tdm_slot_cycles_in_arrays(i2s_tdm_cfg->slot_cycles),
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"%s: slot_cycles(%d) error!", __func__, i2s_tdm_cfg->slot_cycles);
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i2s_tdm_cfg[i2s_id] = *i2s_tdm_cfg;
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cycles = i2s_tdm_cfg->cycles;
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fs_cycles = i2s_tdm_cfg->fs_cycles == HAL_I2S_TDM_FS_CYCLES_ONE_LESS ?\
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cycles - 1: i2s_tdm_cfg->fs_cycles;
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slot_cycles = i2s_tdm_cfg->slot_cycles;
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memset(&i2s_cfg, 0, sizeof(i2s_cfg));
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i2s_cfg.use_dma = true;
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i2s_cfg.sync_start = true;
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i2s_cfg.chan_sep_buf = false;
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i2s_cfg.bits = slot_cycles;
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i2s_cfg.channel_num = 2;
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i2s_cfg.channel_map = AUD_CHANNEL_MAP_CH0 | AUD_CHANNEL_MAP_CH1;
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i2s_cfg.sample_rate = (sample_rate*(cycles/i2s_cfg.bits))/2;
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ret = hal_i2s_setup_stream(i2s_id, AUD_STREAM_PLAYBACK, &i2s_cfg);
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if(ret)
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{
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I2S_TDM_TRACE(2,"%s: playback failed.ret = %d.", __func__, ret);
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goto __func_fail;
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}
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i2s_cfg.sync_start = false;
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ret = hal_i2s_setup_stream(i2s_id, AUD_STREAM_CAPTURE, &i2s_cfg);
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if(ret)
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{
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I2S_TDM_TRACE(1,"hal_i2s_setup_stream capture failed.ret = %d.", ret);
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goto __func_fail;
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}
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// Set tx buffer, output signal as slave device ws.
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I2S_TDM_TRACE(3,"%s: cycles = %d, fs_cycles = %d", __func__, cycles, fs_cycles);
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for (i = 0; i < I2S_TDM_TX_FRAME_NUM ; i++) {
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buf = (uint16_t*)(&i2s_tdm_tx_buf[i2s_id][i][0]);
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for(j = 0; j < I2S_TDM_TX_FRAME_SIZE/(cycles/16); j ++){
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fs_remain = fs_cycles;
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for(m = 0; m < (cycles/16); m++) {
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buf[j*(cycles/16) + m] = 0;
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for(n = 0; n < 16; n++) {
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if (fs_remain > 0) {
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buf[j*(cycles/16) + m] |= (1<< n);
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fs_remain --;
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} else {
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break;
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}
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}
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}
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}
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}
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I2S_TDM_TRACE(1,"%s done.", __func__);
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return 0;
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__func_fail:
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I2S_TDM_TRACE(2,"%s failed. ret = %d.", __func__, ret);
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return ret;
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}
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int32_t hal_i2s_tdm_start_stream(enum HAL_I2S_ID_T i2s_id)
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{
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uint32_t i;
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int ret;
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I2S_TDM_TRACE(2,"%s: i2s_id = %d.", __func__, i2s_id);
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ASSERT(i2s_id < HAL_I2S_ID_QTY,"%s: i2s_id = %d!", __func__, i2s_id);
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memset(&tx_dma_cfg[i2s_id], 0, sizeof(tx_dma_cfg[i2s_id]));
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tx_dma_cfg[i2s_id].dst = 0; //useless
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tx_dma_cfg[i2s_id].dst_bsize = HAL_DMA_BSIZE_4;
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tx_dma_cfg[i2s_id].dst_periph = i2s_id == HAL_I2S_ID_0 ? HAL_AUDMA_I2S0_TX : HAL_AUDMA_I2S1_TX;
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tx_dma_cfg[i2s_id].dst_width = HAL_DMA_WIDTH_HALFWORD;
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tx_dma_cfg[i2s_id].handler = i2s_id == HAL_I2S_ID_0 ? i2s_tdm0_tx_handler : i2s_tdm1_tx_handler;
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tx_dma_cfg[i2s_id].src_bsize = HAL_DMA_BSIZE_4;
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tx_dma_cfg[i2s_id].src_tsize = (sizeof(i2s_tdm_tx_buf[i2s_id][0])/2);
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tx_dma_cfg[i2s_id].src_width = HAL_DMA_WIDTH_HALFWORD;
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tx_dma_cfg[i2s_id].try_burst = 1;
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tx_dma_cfg[i2s_id].type = HAL_DMA_FLOW_M2P_DMA;
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tx_dma_cfg[i2s_id].ch = hal_audma_get_chan(tx_dma_cfg[i2s_id].dst_periph, HAL_DMA_HIGH_PRIO);
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for (i = 0; i < I2S_TDM_TX_FRAME_NUM; i++) {
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tx_dma_cfg[i2s_id].src = (uint32_t)&i2s_tdm_tx_buf[i2s_id][i][0];
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ret = hal_audma_init_desc(&i2s_tdm_tx_dma_desc[i2s_id][i],
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&tx_dma_cfg[i2s_id],
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&i2s_tdm_tx_dma_desc[i2s_id][(i + 1) % I2S_TDM_TX_FRAME_NUM],
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1);
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if(ret)
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{
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I2S_TDM_TRACE(2,"%s: hal_audma_init_desc tx failed.ret = %d.", __func__, ret);
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goto __func_fail;
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}
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}
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ret = hal_audma_sg_start(&i2s_tdm_tx_dma_desc[i2s_id][0], &tx_dma_cfg[i2s_id]);
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if(ret)
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{
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I2S_TDM_TRACE(2,"%s: hal_audma_sg_start tx failed.ret = %d.", __func__, ret);
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goto __func_fail;
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}
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// i2s start stream playback and capture.
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ret = hal_i2s_start_stream(i2s_id, AUD_STREAM_PLAYBACK);
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if(ret)
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{
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I2S_TDM_TRACE(2,"%s: hal_i2s_start_stream failed.ret = %d.", __func__, ret);
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}
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ret = hal_i2s_start_stream(i2s_id, AUD_STREAM_CAPTURE);
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if(ret)
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{
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I2S_TDM_TRACE(1,"hal_i2s_start_stream tx failed.ret = %d.", ret);
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goto __func_fail;
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}
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I2S_TDM_TRACE(1,"%s done.", __func__);
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return ret;
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__func_fail:
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I2S_TDM_TRACE(2,"%s failed.ret = %d.", __func__, ret);
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return ret;
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}
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int32_t hal_i2s_tdm_stop_stream(enum HAL_I2S_ID_T i2s_id)
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{
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I2S_TDM_TRACE(2,"%s: i2s_id = %d.", __func__, i2s_id);
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ASSERT(i2s_id < HAL_I2S_ID_QTY,"%s: i2s_id = %d!", __func__, i2s_id);
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hal_dma_stop(tx_dma_cfg[i2s_id].ch);
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hal_i2s_stop_stream(i2s_id,AUD_STREAM_PLAYBACK);
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hal_i2s_stop_stream(i2s_id,AUD_STREAM_CAPTURE);
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I2S_TDM_TRACE(1,"%s done.", __func__);
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return 0;
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}
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int32_t hal_i2s_tdm_close(enum HAL_I2S_ID_T i2s_id)
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{
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I2S_TDM_TRACE(2,"%s: i2s_id = %d.", __func__, i2s_id);
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ASSERT(i2s_id < HAL_I2S_ID_QTY,"%s: i2s_id = %d!", __func__, i2s_id);
|
||
|
|
|
||
|
|
hal_i2s_close(i2s_id,AUD_STREAM_PLAYBACK);
|
||
|
|
hal_i2s_close(i2s_id,AUD_STREAM_CAPTURE);
|
||
|
|
|
||
|
|
I2S_TDM_TRACE(1,"%s done.", __func__);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void hal_i2s_tdm_get_config(enum HAL_I2S_ID_T i2s_id,struct HAL_I2S_TDM_CONFIG_T *tdm_cfg)
|
||
|
|
{
|
||
|
|
I2S_TDM_TRACE(2,"%s: i2s_id = %d.", __func__, i2s_id);
|
||
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY,"%s: i2s_id = %d!", __func__, i2s_id);
|
||
|
|
|
||
|
|
*tdm_cfg = i2s_tdm_cfg[i2s_id];
|
||
|
|
}
|
||
|
|
|
||
|
|
void hal_i2s_tdm_set_config(enum HAL_I2S_ID_T i2s_id,struct HAL_I2S_TDM_CONFIG_T *tdm_cfg)
|
||
|
|
{
|
||
|
|
I2S_TDM_TRACE(2,"%s: i2s_id = %d.", __func__, i2s_id);
|
||
|
|
ASSERT(i2s_id < HAL_I2S_ID_QTY,"%s: i2s_id = %d!", __func__, i2s_id);
|
||
|
|
|
||
|
|
i2s_tdm_cfg[i2s_id] = *tdm_cfg;
|
||
|
|
}
|
||
|
|
|