413 lines
12 KiB
C
413 lines
12 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifdef CHIP_HAS_SPDIF
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#include "plat_types.h"
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#include "plat_addr_map.h"
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#include "reg_spdifip.h"
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#include "hal_spdifip.h"
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#include "hal_spdif.h"
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#include "hal_iomux.h"
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#include "hal_timer.h"
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#include "hal_trace.h"
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#include "analog.h"
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#include "cmsis.h"
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//#define SPDIF_CLOCK_SOURCE 240000000
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//#define SPDIF_CLOCK_SOURCE 22579200
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//#define SPDIF_CLOCK_SOURCE 48000000
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#define SPDIF_CLOCK_SOURCE 3072000
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//#define SPDIF_CLOCK_SOURCE 76800000
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//#define SPDIF_CLOCK_SOURCE 84672000
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// Trigger DMA request when TX-FIFO count <= threshold
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#define HAL_SPDIF_TX_FIFO_TRIGGER_LEVEL (SPDIFIP_FIFO_DEPTH/2)
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// Trigger DMA request when RX-FIFO count >= threshold
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#define HAL_SPDIF_RX_FIFO_TRIGGER_LEVEL (SPDIFIP_FIFO_DEPTH/2)
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#define HAL_SPDIF_YES 1
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#define HAL_SPDIF_NO 0
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#ifdef CHIP_BEST2000
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#define SPDIF_CMU_DIV CODEC_CMU_DIV
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#else
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#define SPDIF_CMU_DIV CODEC_PLL_DIV
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#endif
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enum HAL_SPDIF_STATUS_T {
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HAL_SPDIF_STATUS_NULL,
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HAL_SPDIF_STATUS_OPENED,
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HAL_SPDIF_STATUS_STARTED,
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};
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struct HAL_SPDIF_MOD_NAME_T {
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enum HAL_CMU_MOD_ID_T mod;
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enum HAL_CMU_MOD_ID_T apb;
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};
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struct HAL_SPDIF_MOD_NAME_T spdif_mod[HAL_SPDIF_ID_QTY] = {
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{
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.mod = HAL_CMU_MOD_O_SPDIF0,
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.apb = HAL_CMU_MOD_P_SPDIF0,
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},
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#if (CHIP_HAS_SPDIF > 1)
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{
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.mod = HAL_CMU_MOD_O_SPDIF1,
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.apb = HAL_CMU_MOD_P_SPDIF1,
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},
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#endif
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};
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static const char * const invalid_id = "Invalid SPDIF ID: %d\n";
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//static const char * const invalid_ch = "Invalid SPDIF CH: %d\n";
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struct SPDIF_SAMPLE_RATE_T {
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enum AUD_SAMPRATE_T sample_rate;
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uint32_t codec_freq;
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uint8_t codec_div;
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uint8_t pcm_div;
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uint8_t tx_ratio;
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};
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// SAMPLE_RATE * 128 = PLL_nominal / PCM_DIV / TX_RATIO
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static const struct SPDIF_SAMPLE_RATE_T spdif_sample_rate[]={
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#if defined(CHIP_BEST1000) && defined(AUD_PLL_DOUBLE)
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{AUD_SAMPRATE_96000, CODEC_FREQ_48K_SERIES*2, CODEC_PLL_DIV, SPDIF_CMU_DIV, 4},
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{AUD_SAMPRATE_192000, CODEC_FREQ_48K_SERIES*2, CODEC_PLL_DIV, SPDIF_CMU_DIV, 2},
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{AUD_SAMPRATE_384000, CODEC_FREQ_48K_SERIES*2, CODEC_PLL_DIV, SPDIF_CMU_DIV, 1},
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#else
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{AUD_SAMPRATE_8000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 24},
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{AUD_SAMPRATE_16000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 12},
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{AUD_SAMPRATE_22050, CODEC_FREQ_44_1K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 8},
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{AUD_SAMPRATE_24000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 8},
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{AUD_SAMPRATE_44100, CODEC_FREQ_44_1K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 4},
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{AUD_SAMPRATE_48000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 4},
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{AUD_SAMPRATE_96000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 2},
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{AUD_SAMPRATE_192000, CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV, SPDIF_CMU_DIV, 1},
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#endif
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};
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#if (CHIP_HAS_SPDIF > 1)
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static uint8_t spdif_map;
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STATIC_ASSERT(HAL_SPDIF_ID_QTY <= sizeof(spdif_map) * 8, "Too many SPDIF IDs");
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#endif
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static enum HAL_SPDIF_STATUS_T spdif_status[HAL_SPDIF_ID_QTY][AUD_STREAM_NUM];
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static bool spdif_dma[HAL_SPDIF_ID_QTY][AUD_STREAM_NUM];
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static inline uint32_t _spdif_get_reg_base(enum HAL_SPDIF_ID_T id)
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{
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ASSERT(id < HAL_SPDIF_ID_QTY, invalid_id, id);
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switch(id) {
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case HAL_SPDIF_ID_0:
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default:
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return SPDIF0_BASE;
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break;
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#if (CHIP_HAS_SPDIF > 1)
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case HAL_SPDIF_ID_1:
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return SPDIF1_BASE;
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break;
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#endif
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}
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return 0;
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}
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int hal_spdif_open(enum HAL_SPDIF_ID_T id, enum AUD_STREAM_T stream)
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{
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uint32_t reg_base;
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reg_base = _spdif_get_reg_base(id);
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if (spdif_status[id][stream] != HAL_SPDIF_STATUS_NULL) {
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TRACE(2,"Invalid SPDIF opening status for stream %d: %d", stream, spdif_status[id][stream]);
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return 1;
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}
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if (spdif_status[id][AUD_STREAM_PLAYBACK] == HAL_SPDIF_STATUS_NULL &&
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spdif_status[id][AUD_STREAM_CAPTURE] == HAL_SPDIF_STATUS_NULL) {
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#ifndef SIMU
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bool cfg_pll = true;
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int i;
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for (i = HAL_SPDIF_ID_0; i < HAL_SPDIF_ID_QTY; i++) {
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if (spdif_status[i][AUD_STREAM_PLAYBACK] != HAL_SPDIF_STATUS_NULL ||
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spdif_status[i][AUD_STREAM_CAPTURE] != HAL_SPDIF_STATUS_NULL) {
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cfg_pll = false;
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break;
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}
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}
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if (cfg_pll) {
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analog_aud_pll_open(ANA_AUD_PLL_USER_SPDIF);
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}
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#endif
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#if (CHIP_HAS_SPDIF > 1)
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if (id == HAL_SPDIF_ID_1) {
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hal_iomux_set_spdif1();
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} else
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#endif
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{
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hal_iomux_set_spdif0();
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}
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hal_cmu_spdif_clock_enable(id);
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hal_cmu_clock_enable(spdif_mod[id].mod);
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hal_cmu_clock_enable(spdif_mod[id].apb);
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hal_cmu_reset_clear(spdif_mod[id].mod);
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hal_cmu_reset_clear(spdif_mod[id].apb);
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spdifip_w_enable_spdifip(reg_base, HAL_SPDIF_YES);
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}
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spdif_dma[id][stream] = false;
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spdif_status[id][stream] = HAL_SPDIF_STATUS_OPENED;
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return 0;
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}
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int hal_spdif_close(enum HAL_SPDIF_ID_T id, enum AUD_STREAM_T stream)
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{
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uint32_t reg_base;
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if (id >= HAL_SPDIF_ID_QTY) {
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return 1;
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}
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if (spdif_status[id][stream] != HAL_SPDIF_STATUS_OPENED) {
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TRACE(2,"Invalid SPDIF closing status for stream %d: %d", stream, spdif_status[id][stream]);
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return 1;
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}
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spdif_status[id][stream] = HAL_SPDIF_STATUS_NULL;
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if (spdif_status[id][AUD_STREAM_PLAYBACK] == HAL_SPDIF_STATUS_NULL &&
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spdif_status[id][AUD_STREAM_CAPTURE] == HAL_SPDIF_STATUS_NULL) {
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reg_base = _spdif_get_reg_base(id);
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spdifip_w_enable_spdifip(reg_base, HAL_SPDIF_NO);
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hal_cmu_spdif_set_div(id, 0x1FFF + 2);
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hal_cmu_reset_set(spdif_mod[id].apb);
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hal_cmu_reset_set(spdif_mod[id].mod);
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hal_cmu_clock_disable(spdif_mod[id].apb);
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hal_cmu_clock_disable(spdif_mod[id].mod);
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hal_cmu_spdif_clock_disable(id);
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#ifndef SIMU
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bool cfg_pll = true;
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int i;
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for (i = HAL_SPDIF_ID_0; i < HAL_SPDIF_ID_QTY; i++) {
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if (spdif_status[i][AUD_STREAM_PLAYBACK] != HAL_SPDIF_STATUS_NULL ||
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spdif_status[i][AUD_STREAM_CAPTURE] != HAL_SPDIF_STATUS_NULL) {
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cfg_pll = false;
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break;
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}
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}
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if (cfg_pll) {
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analog_aud_pll_close(ANA_AUD_PLL_USER_SPDIF);
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}
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#endif
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}
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return 0;
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}
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int hal_spdif_start_stream(enum HAL_SPDIF_ID_T id, enum AUD_STREAM_T stream)
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{
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uint32_t reg_base;
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uint32_t lock;
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reg_base = _spdif_get_reg_base(id);
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if (spdif_status[id][stream] != HAL_SPDIF_STATUS_OPENED) {
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TRACE(2,"Invalid SPDIF starting status for stream %d: %d", stream, spdif_status[id][stream]);
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return 1;
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}
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if (stream == AUD_STREAM_PLAYBACK) {
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lock = int_lock();
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spdifip_w_enable_tx_channel0(reg_base, HAL_SPDIF_YES);
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spdifip_w_enable_tx(reg_base, HAL_SPDIF_YES);
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spdifip_w_tx_valid(reg_base, HAL_SPDIF_YES);
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if (spdif_dma[id][stream]) {
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spdifip_w_enable_tx_dma(reg_base, HAL_SPDIF_YES);
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}
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int_unlock(lock);
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} else {
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if (spdif_dma[id][stream]) {
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spdifip_w_enable_rx_dma(reg_base, HAL_SPDIF_YES);
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}
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spdifip_w_enable_rx_channel0(reg_base, HAL_SPDIF_YES);
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spdifip_w_enable_rx(reg_base, HAL_SPDIF_YES);
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spdifip_w_sample_en(reg_base, HAL_SPDIF_YES);
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}
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spdif_status[id][stream] = HAL_SPDIF_STATUS_STARTED;
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return 0;
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}
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int hal_spdif_stop_stream(enum HAL_SPDIF_ID_T id, enum AUD_STREAM_T stream)
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{
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uint32_t reg_base;
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reg_base = _spdif_get_reg_base(id);
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if (spdif_status[id][stream] != HAL_SPDIF_STATUS_STARTED) {
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TRACE(2,"Invalid SPDIF stopping status for stream %d: %d", stream, spdif_status[id][stream]);
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return 1;
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}
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spdif_status[id][stream] = HAL_SPDIF_STATUS_OPENED;
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if (stream == AUD_STREAM_PLAYBACK) {
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spdifip_w_enable_tx(reg_base, HAL_SPDIF_NO);
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spdifip_w_enable_tx_channel0(reg_base, HAL_SPDIF_NO);
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spdifip_w_enable_tx_dma(reg_base, HAL_SPDIF_NO);
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spdifip_w_tx_fifo_reset(reg_base);
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} else {
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spdifip_w_enable_rx(reg_base, HAL_SPDIF_NO);
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spdifip_w_enable_rx_channel0(reg_base, HAL_SPDIF_NO);
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spdifip_w_enable_rx_dma(reg_base, HAL_SPDIF_NO);
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spdifip_w_rx_fifo_reset(reg_base);
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}
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return 0;
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}
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int hal_spdif_setup_stream(enum HAL_SPDIF_ID_T id, enum AUD_STREAM_T stream, struct HAL_SPDIF_CONFIG_T *cfg)
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{
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uint8_t i;
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uint32_t reg_base;
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uint8_t fmt;
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reg_base = _spdif_get_reg_base(id);
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if (spdif_status[id][stream] != HAL_SPDIF_STATUS_OPENED) {
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TRACE(2,"Invalid SPDIF setup status for stream %d: %d", stream, spdif_status[id][stream]);
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return 1;
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}
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for (i = 0; i < ARRAY_SIZE(spdif_sample_rate); i++)
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{
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if (spdif_sample_rate[i].sample_rate == cfg->sample_rate)
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{
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break;
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}
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}
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ASSERT(i < ARRAY_SIZE(spdif_sample_rate), "%s: Invalid spdif sample rate: %d", __func__, cfg->sample_rate);
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TRACE(3,"[%s] stream=%d sample_rate=%d", __func__, stream, cfg->sample_rate);
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#ifdef FPGA
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hal_cmu_spdif_set_div(id, 2);
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#else
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#ifndef SIMU
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analog_aud_freq_pll_config(spdif_sample_rate[i].codec_freq, spdif_sample_rate[i].codec_div);
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#ifdef CHIP_BEST2000
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analog_aud_pll_set_dig_div(spdif_sample_rate[i].codec_div / spdif_sample_rate[i].pcm_div);
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#endif
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#endif
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// SPDIF module is working on 24.576M or 22.5792M
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hal_cmu_spdif_set_div(id, spdif_sample_rate[i].pcm_div);
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|
|
#endif
|
||
|
|
|
||
|
|
if ((stream == AUD_STREAM_PLAYBACK && spdif_status[id][AUD_STREAM_CAPTURE] == HAL_SPDIF_STATUS_NULL) ||
|
||
|
|
(stream == AUD_STREAM_CAPTURE && spdif_status[id][AUD_STREAM_PLAYBACK] == HAL_SPDIF_STATUS_NULL)) {
|
||
|
|
hal_cmu_reset_pulse(spdif_mod[id].mod);
|
||
|
|
}
|
||
|
|
|
||
|
|
spdif_dma[id][stream] = cfg->use_dma;
|
||
|
|
|
||
|
|
fmt = 0;
|
||
|
|
switch (cfg->bits) {
|
||
|
|
case AUD_BITS_16:
|
||
|
|
fmt = 0;
|
||
|
|
break;
|
||
|
|
// here, 32-bit is treated as 24-bit
|
||
|
|
case AUD_BITS_32:
|
||
|
|
case AUD_BITS_24:
|
||
|
|
fmt = 8;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
ASSERT(0, "%s: invalid bits[%d]", __func__, cfg->bits);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (stream == AUD_STREAM_PLAYBACK) {
|
||
|
|
spdifip_w_tx_ratio(reg_base, spdif_sample_rate[i].tx_ratio - 1);
|
||
|
|
spdifip_w_tx_format_cfg_reg(reg_base, fmt);
|
||
|
|
spdifip_w_tx_fifo_threshold(reg_base, HAL_SPDIF_TX_FIFO_TRIGGER_LEVEL);
|
||
|
|
} else {
|
||
|
|
spdifip_w_rx_format_cfg_reg(reg_base, fmt);
|
||
|
|
spdifip_w_rx_fifo_threshold(reg_base, HAL_SPDIF_RX_FIFO_TRIGGER_LEVEL);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_spdif_send(enum HAL_SPDIF_ID_T id, uint8_t *value, uint32_t value_len)
|
||
|
|
{
|
||
|
|
uint32_t i = 0;
|
||
|
|
uint32_t reg_base;
|
||
|
|
|
||
|
|
reg_base = _spdif_get_reg_base(id);
|
||
|
|
|
||
|
|
for (i = 0; i < value_len; i += 4) {
|
||
|
|
while (!(spdifip_r_int_status(reg_base) & SPDIFIP_INT_STATUS_TX_FIFO_EMPTY_MASK));
|
||
|
|
|
||
|
|
spdifip_w_tx_left_fifo(reg_base, value[i+1]<<8 | value[i]);
|
||
|
|
spdifip_w_tx_right_fifo(reg_base, value[i+3]<<8 | value[i+2]);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint8_t hal_spdif_recv(enum HAL_SPDIF_ID_T id, uint8_t *value, uint32_t value_len)
|
||
|
|
{
|
||
|
|
//uint32_t reg_base;
|
||
|
|
|
||
|
|
//reg_base = _spdif_get_reg_base(id);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_spdif_clock_out_enable(enum HAL_SPDIF_ID_T id, uint32_t div)
|
||
|
|
{
|
||
|
|
if (id >= HAL_SPDIF_ID_QTY) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
hal_cmu_spdif_clock_enable(id);
|
||
|
|
hal_cmu_spdif_set_div(id, div);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int hal_spdif_clock_out_disable(enum HAL_SPDIF_ID_T id)
|
||
|
|
{
|
||
|
|
if (id >= HAL_SPDIF_ID_QTY) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
hal_cmu_spdif_set_div(id, 0x1FFF + 2);
|
||
|
|
hal_cmu_spdif_clock_disable(id);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|