282 lines
6.6 KiB
C
282 lines
6.6 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __ARM_ARCH_ISA_ARM
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#include "mpu.h"
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#include "cmsis.h"
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#include "hal_trace.h"
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#define NORM_MEM_WT_RA_ATTR ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0)
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#define NORM_MEM_WB_WA_ATTR ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1)
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#define DEV_MEM_ATTR_OUTER ARM_MPU_ATTR_MEMORY_(0, 0, 0, 0)
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static void init_mair_attr(void)
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{
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ARM_MPU_SetMemAttr(MAIR_ATTR_FLASH, ARM_MPU_ATTR(NORM_MEM_WT_RA_ATTR, NORM_MEM_WT_RA_ATTR));
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ARM_MPU_SetMemAttr(MAIR_ATTR_INT_SRAM, ARM_MPU_ATTR(NORM_MEM_WT_RA_ATTR, NORM_MEM_WT_RA_ATTR));
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ARM_MPU_SetMemAttr(MAIR_ATTR_EXT_SRAM, ARM_MPU_ATTR(NORM_MEM_WB_WA_ATTR, NORM_MEM_WB_WA_ATTR));
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ARM_MPU_SetMemAttr(MAIR_ATTR_DEVICE, ARM_MPU_ATTR(DEV_MEM_ATTR_OUTER, ARM_MPU_ATTR_DEVICE_nGnRnE));
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}
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static int mpu_enable(void)
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{
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int flags = 0;
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if (get_cpu_id()) {
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/*
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* if cpu is CP, we will use different mpu maps, that is, every map needed by CP will
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* be mapped, and the memory is not mapped will issue abort when access
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*/
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flags = MPU_CTRL_HFNMIENA_Msk;
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} else {
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/*
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* mpu maps use default map designed by arm, that is, if the memory is not mapped,
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* the mpu attibutes will use the default setting by ARM.
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*/
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flags = MPU_CTRL_PRIVDEFENA_Msk;
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}
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ARM_MPU_Enable(flags);
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__DSB();
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__ISB();
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return 0;
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}
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static int mpu_disable(void)
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{
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__DMB();
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ARM_MPU_Disable();
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return 0;
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}
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int mpu_open(void)
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{
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int i;
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if ((MPU->TYPE & MPU_TYPE_DREGION_Msk) == 0) {
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return 1;
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}
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for (i = 0; i < MPU_ID_QTY; i++) {
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ARM_MPU_ClrRegion(i);
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}
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init_mair_attr();
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return 0;
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}
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int mpu_close(void)
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{
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ARM_MPU_Disable();
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return 0;
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}
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static int mpu_set_armv8(enum MPU_ID_T id, uint32_t addr, uint32_t len,
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enum MPU_ATTR_T ap_attr, enum MAIR_ATTR_TYPE_T mem_attr)
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{
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uint32_t rbar;
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uint32_t rlar;
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uint8_t xn;
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uint8_t ro;
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uint32_t lock;
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if (id >= MPU_ID_QTY) {
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return 2;
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}
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if (len < 32) {
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return 3;
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}
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if (addr & 0x1F) {
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return 4;
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}
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if (ap_attr >= MPU_ATTR_QTY) {
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return 5;
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}
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if (ap_attr == MPU_ATTR_READ_WRITE_EXEC || ap_attr == MPU_ATTR_READ_EXEC ||
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ap_attr == MPU_ATTR_EXEC) {
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xn = 0;
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} else {
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xn = 1;
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}
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if (ap_attr == MPU_ATTR_READ_WRITE_EXEC || ap_attr == MPU_ATTR_READ_WRITE) {
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ro = 0;
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} else if (ap_attr == MPU_ATTR_READ_EXEC || ap_attr == MPU_ATTR_READ || ap_attr == MPU_ATTR_EXEC) {
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ro = 1;
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} else {
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// Cannot support no access
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return 6;
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}
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// Sharebility: Outer Shareable
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// Non-privilege Access: Enabled
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rbar = ARM_MPU_RBAR(addr, 2, ro, 1, xn);
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/* rlar = ARM_MPU_RLAR((addr + len - 1), MAIR_ATTR_INT_SRAM); */
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rlar = ARM_MPU_RLAR((addr + len - 1), mem_attr);
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lock = int_lock();
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ARM_MPU_SetRegion(id, rbar, rlar);
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int_unlock(lock);
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return 0;
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}
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static inline int mpu_fram_protect_armv8(uint32_t fr_start, uint32_t fr_end)
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{
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uint32_t len = fr_end - fr_start;
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int ret;
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if ((fr_start % 32 != 0) || (len % 32 != 0))
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ASSERT(0, "fr_start %x and len %d must be aligned to 32", fr_start, len);
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mpu_disable();
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ret = mpu_set_armv8(MPU_ID_FRAM_TEXT1, fr_start, len, MPU_ATTR_EXEC, MAIR_ATTR_INT_SRAM);
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mpu_enable();
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return ret;
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}
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static int mpu_code_region_protect(void)
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{
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uint32_t code_start = RAMX_BASE;
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uint32_t len = RAM_SIZE;
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return mpu_set(MPU_ID_CODE, code_start, len, 0, MPU_ATTR_EXEC);
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}
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extern uint32_t __sram_text_data_start__[];
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extern uint32_t __sram_text_end__[];
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static int mpu_sram_text_protect(void)
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{
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int ret;
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uint32_t start = (uint32_t)__sram_text_data_start__;
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uint32_t end = RAMX_TO_RAM((uint32_t)__sram_text_end__);
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uint32_t len = end - start;
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TRACE(1,"sram start %x size %x", start, len);
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if ((start % 32 != 0) || (len % 32 != 0))
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ASSERT(0, "sram start %x and len %d must be aligned to 32", start, len);
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ret = mpu_set(MPU_ID_SRAM_TEXT, start, len, 0, MPU_ATTR_READ_EXEC);
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return ret;
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}
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int mpu_set(enum MPU_ID_T id, uint32_t addr, uint32_t len, int srd_bits,
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enum MPU_ATTR_T attr)
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{
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int ret = -1;
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uint32_t lock;
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lock = int_lock();
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mpu_disable();
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ret = mpu_set_armv8(id, addr, len, attr, MAIR_ATTR_INT_SRAM);
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mpu_enable();
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int_unlock(lock);
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return ret;
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}
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int mpu_clear(enum MPU_ID_T id)
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{
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uint32_t lock;
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if (id >= MPU_ID_QTY) {
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return 2;
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}
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lock = int_lock();
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mpu_disable();
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ARM_MPU_ClrRegion(id);
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__DSB();
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__ISB();
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mpu_enable();
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int_unlock(lock);
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return 0;
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}
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static int mpu_null_check_enable(void)
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{
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return mpu_set(MPU_ID_NULL_POINTER, 0, 0x800, 0, MPU_ATTR_EXEC);
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}
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extern uint32_t __fast_sram_text_exec_start__[];
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extern uint32_t __fast_sram_text_exec_end__[];
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static int mpu_fast_ram_protect(void)
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{
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uint32_t ramx_start = (uint32_t)__fast_sram_text_exec_start__;
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uint32_t ramx_end = (uint32_t)__fast_sram_text_exec_end__;
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uint32_t ram_start = RAMX_TO_RAM(ramx_start);
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uint32_t ram_end = RAMX_TO_RAM(ramx_end);
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int ret = -1;
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ret = mpu_fram_protect_armv8(ram_start, ram_end);
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return ret;
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}
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int mpu_setup(void)
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{
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mpu_null_check_enable();
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mpu_code_region_protect();
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mpu_sram_text_protect();
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mpu_fast_ram_protect();
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return 0;
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}
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int mpu_setup_cp(const mpu_regions_t *mpu_table, uint32_t region_num)
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{
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int ret;
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int i;
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uint32_t lock;
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ret = mpu_open();
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if (ret) {
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return ret;
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}
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if (region_num > MPU_ID_QTY) {
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return -1;
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}
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lock = int_lock();
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mpu_disable();
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for (i = 0; i < region_num; i++) {
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const mpu_regions_t *region;
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region = &mpu_table[i];
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ret = mpu_set_armv8(i, region->addr, region->len, region->ap_attr, region->mem_attr);
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if (ret)
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break;
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}
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mpu_enable();
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int_unlock(lock);
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return ret;
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}
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#endif
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