2023-02-01 14:52:54 -06:00
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#include "app_ai_if_config.h"
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#include "cmsis_nvic.h"
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#include "cmsis_os.h"
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#include "stdbool.h"
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#include "stdint.h"
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#include "string.h"
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#include "tool_msg.h"
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//#include "hal_timer_raw.h"
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#include "app_thread.h"
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#include "communication_sysapi.h"
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#include "hal_bootmode.h"
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#include "hal_cmu.h"
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#include "hal_iomux.h"
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#include "hal_uart.h"
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#include "pmu.h"
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#include "tgt_hardware.h"
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//#define FLASH_BASE 0x6C000000
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//#define FLASH_TO_FLASHX(d) ((uint32_t)(d) & 0x0FFFFFFF)
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#define WAIT_TRACE_TIMEOUT MS_TO_TICKS(200)
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static uint32_t send_timeout = MS_TO_TICKS(500);
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static const struct HAL_UART_CFG_T uart_cfg = {
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HAL_UART_PARITY_NONE,
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#ifdef __KNOWLES
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HAL_UART_STOP_BITS_2,
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#else
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HAL_UART_STOP_BITS_1,
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#endif
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HAL_UART_DATA_BITS_8,
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HAL_UART_FLOW_CONTROL_NONE, // RTC/CTS pins might be unavailable for some
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// chip packages
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HAL_UART_FIFO_LEVEL_1_2,
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HAL_UART_FIFO_LEVEL_1_2,
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#ifdef __PC_CMD_UART__
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115200,
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#else
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921600,
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#endif
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true,
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false,
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false,
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};
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#ifdef __PC_CMD_UART__
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static const enum HAL_UART_ID_T comm_uart = HAL_UART_ID_0;
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#else
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#ifdef CHIP_BEST2300P
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static const enum HAL_UART_ID_T comm_uart = HAL_UART_ID_2;
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#else
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static const enum HAL_UART_ID_T comm_uart = HAL_UART_ID_1;
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#endif
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#endif
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static volatile enum UART_DMA_STATE uart_dma_rx_state = UART_DMA_IDLE;
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static volatile uint32_t uart_dma_rx_size = 0;
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static bool uart_opened = false;
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static volatile bool cancel_xfer = false;
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static uint32_t xfer_err_time = 0;
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static uint32_t xfer_err_cnt = 0;
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#ifdef __KNOWLES
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#include "Knowles_mic_demo.h"
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#include "audio_dump.h"
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#include "cqueue.h"
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uint32_t kw_start_index = 0;
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uint32_t kw_end_index = 0;
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bool is_markers_read_done = false;
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#ifdef KNOWLES_UART_DATA
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uint8_t out_buf[FRAME_SIZE];
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uint8_t found = 0;
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static osMutexId uart_audio_pcmbuff_mutex_id = NULL;
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osMutexDef(uart_audio_pcmbuff_mutex);
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typedef enum { PP_PING = 0, PP_PANG = 1 } FIR_PP_T;
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#define PP_PINGPANG(v) (v == PP_PING ? PP_PANG : PP_PING)
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static FIR_PP_T pp_index = PP_PING;
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static uint32_t uart_dma_interval;
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#define knowles_uart_packet_len FRAME_SIZE // 640//20MS
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static uint8_t
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audio_data_receive_buf[knowles_uart_packet_len * 2]; // ping_pong_buffer
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#ifdef SYSTEM_USE_PSRAM
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#include "hal_location.h"
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#define AMA_STREAM_UART_FIFO_SIZE (1024 * 32)
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PSRAM_BSS_LOC static unsigned char ama_uart_buff[AMA_STREAM_UART_FIFO_SIZE];
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#else
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#define AMA_STREAM_UART_FIFO_SIZE (1024 * 16)
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static unsigned char ama_uart_buff[AMA_STREAM_UART_FIFO_SIZE];
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#endif
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static CQueue ama_uart_queue = {0};
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extern osThreadId knowles_uart_audio_tid;
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#define APP_UART_FLOW_CONTROL_TIMEOUT_INTERVEL (12)
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static void app_uart_flow_control_timeout_timer_cb(void const *n);
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osTimerDef(APP_UART_FLOW_CONTROL_TIMEOUT,
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app_uart_flow_control_timeout_timer_cb);
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osTimerId app_uart_flow_control_timeout_timer_id = NULL;
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static void app_uart_flow_control_timeout_timer_cb(void const *n) {
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uint32_t available_buffer;
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unsigned char get_next_chunk_cmd[4];
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smart_mic_get_nextchunk_cmd(get_next_chunk_cmd);
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available_buffer = avil_len_of_the_fifo();
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available_buffer = AMA_STREAM_UART_FIFO_SIZE - available_buffer;
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TRACE(1, "UART_FLOW_CONTROL: Available UART Buffer %d\n", available_buffer);
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if (available_buffer > 1024) {
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// TRACE(0,"More than 1024 bytes availble hence sending next chunk command
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// \n");
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send_data(get_next_chunk_cmd, 4);
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osTimerStop(app_uart_flow_control_timeout_timer_id);
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osTimerStart(app_uart_flow_control_timeout_timer_id,
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APP_UART_FLOW_CONTROL_TIMEOUT_INTERVEL);
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} else {
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// TRACE(0,"no buffer available hence triggering timer for 10ms\n");
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osTimerStop(app_uart_flow_control_timeout_timer_id);
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osTimerStart(app_uart_flow_control_timeout_timer_id,
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APP_UART_FLOW_CONTROL_TIMEOUT_INTERVEL);
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}
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}
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void ama_uart_stream_fifo_init() {
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if (uart_audio_pcmbuff_mutex_id == NULL) {
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uart_audio_pcmbuff_mutex_id =
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osMutexCreate((osMutex(uart_audio_pcmbuff_mutex)));
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}
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pp_index = PP_PING;
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if (knowles_uart_audio_tid) {
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osSignalClear(knowles_uart_audio_tid, UART_OUT_SIGNAL_ID);
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}
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memset(audio_data_receive_buf, 0, sizeof(audio_data_receive_buf));
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InitCQueue(&ama_uart_queue, AMA_STREAM_UART_FIFO_SIZE,
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(CQItemType *)ama_uart_buff);
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}
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uint32_t ama_uart_get_fifo_data(uint8_t *buf) {
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uint32_t avail = 0;
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avail = LengthOfCQueue(&ama_uart_queue);
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if (avail > 0) {
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if (avail < knowles_uart_packet_len) {
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TRACE(2, "%s: Invalid UART STREAM SIZE: %d", __FUNCTION__, avail);
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return 0;
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} else {
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// TRACE(1,"UART_GET_len %d",knowles_uart_packet_len);
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if (!DeCQueue(&ama_uart_queue, buf, knowles_uart_packet_len))
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return knowles_uart_packet_len;
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TRACE(2, "%s: queue get data error len %d", __func__,
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knowles_uart_packet_len);
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return 0;
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}
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} else {
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TRACE(0, "uart no stream to get");
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return 0;
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}
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}
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uint32_t avil_len_of_the_fifo() { return LengthOfCQueue(&ama_uart_queue); }
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extern "C" void OS_NotifyEvm(void);
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void send_message() { OS_NotifyEvm(); }
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#endif
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#endif
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static void uart_break_handler(void) {
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TRACE(0, "****** Handle break ******");
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cancel_xfer = true;
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hal_uart_stop_dma_recv(comm_uart);
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hal_uart_stop_dma_send(comm_uart);
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uart_dma_rx_state = UART_DMA_ERROR;
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}
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extern "C" uint8_t app_ai_is_stream_running(void);
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static void uart_rx_dma_handler(uint32_t xfer_size, int dma_error,
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union HAL_UART_IRQ_T status) {
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if (status.BE) {
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uart_break_handler();
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return;
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}
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// The DMA transfer has been cancelled
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#ifndef KNOWLES_UART_DATA
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if (uart_dma_rx_state != UART_DMA_START) {
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return;
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}
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#endif
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uart_dma_rx_size = xfer_size;
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if (dma_error || status.FE || status.OE || status.PE || status.BE) {
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TRACE(2, "UART-RX Error: dma_error=%d, status=0x%08x", dma_error,
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status.reg);
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uart_dma_rx_state = UART_DMA_ERROR;
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} else {
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// TRACE(1,"UART-RX OK: rx_size=%d", uart_dma_rx_size);
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uart_dma_rx_state = UART_DMA_DONE;
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int ret = 0;
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// TRACE(1,"UART DMA INTERUPT
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// TIME=%d",hal_sys_timer_get()-uart_dma_interval);
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uart_dma_interval = hal_sys_timer_get();
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if (app_ai_is_stream_running()) {
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if (!EnCQueue(&ama_uart_queue,
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(uint8_t *)&audio_data_receive_buf[pp_index *
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knowles_uart_packet_len],
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FRAME_SIZE))
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ret = FRAME_SIZE;
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if (ret < FRAME_SIZE) {
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TRACE(2, "%s:WARNING !!! UART STREAM OVERFLOW Dropping %d Bytes",
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__FUNCTION__, (FRAME_SIZE - ret));
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}
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osSignalSet(knowles_uart_audio_tid, UART_OUT_SIGNAL_ID);
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}
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pp_index = PP_PINGPANG(pp_index);
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}
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}
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void recv_data_state_get(enum UART_DMA_STATE *state) {
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*state = uart_dma_rx_state;
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}
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void recv_data_reset(void) {
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union HAL_UART_IRQ_T mask;
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mask.reg = 0;
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mask.BE = 1;
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hal_uart_irq_set_mask(comm_uart, mask);
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uart_dma_rx_state = UART_DMA_IDLE;
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}
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void init_transport(void) {
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union HAL_UART_IRQ_T mask;
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struct HAL_UART_CFG_T comm_uart_cfg;
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#ifdef KNOWLES_UART_DATA
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// audio_dump_init(320, 1);
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ama_uart_stream_fifo_init();
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#endif
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if (!uart_opened) {
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#ifdef __PC_CMD_UART__
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hal_iomux_set_uart0();
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#else
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#ifdef CHIP_BEST2300P
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hal_iomux_init(cfg_pinmux_uart, ARRAY_SIZE(cfg_pinmux_uart));
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#else
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hal_iomux_set_uart1();
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#endif
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#endif
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memcpy(&comm_uart_cfg, &uart_cfg, sizeof(comm_uart_cfg));
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hal_uart_open(comm_uart, &comm_uart_cfg);
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mask.reg = 0;
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mask.BE = 1;
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mask.FE = 1;
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mask.OE = 1;
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mask.PE = 1;
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hal_uart_irq_set_dma_handler(comm_uart, uart_rx_dma_handler, NULL);
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hal_uart_irq_set_mask(comm_uart, mask);
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uart_opened = true;
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}
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cancel_xfer = false;
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hal_uart_flush(comm_uart, 0);
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#ifdef KNOWLES_UART_DATA
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if (recv_data(&audio_data_receive_buf[0], knowles_uart_packet_len * 2) < 0)
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TRACE(1, "%s error", __func__);
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smart_mic_stream_header_parser_init(FRAME_SIZE);
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#endif
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app_uart_flow_control_timeout_timer_id =
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osTimerCreate(osTimer(APP_UART_FLOW_CONTROL_TIMEOUT), osTimerOnce, NULL);
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}
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void deinit_transport(void) {
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union HAL_UART_IRQ_T mask;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
mask.reg = 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
// audio_dump_clear_up(); //added by punith
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
hal_uart_stop_dma_recv(comm_uart); // punith
|
|
|
|
uart_dma_rx_state = UART_DMA_IDLE;
|
|
|
|
hal_uart_irq_set_mask(comm_uart, mask);
|
|
|
|
hal_uart_irq_set_dma_handler(comm_uart, NULL, NULL);
|
|
|
|
hal_uart_close(comm_uart);
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
hal_uart_flush(comm_uart, 0);
|
|
|
|
uart_opened = false;
|
|
|
|
cancel_xfer = true;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
osTimerStop(app_uart_flow_control_timeout_timer_id);
|
|
|
|
if (osTimerDelete(app_uart_flow_control_timeout_timer_id) != osOK) {
|
|
|
|
TRACE(0, "app_uart_flow_control_timeout_timer_id Failed !!!!");
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
void reinit_transport(void) {
|
|
|
|
union HAL_UART_IRQ_T mask;
|
|
|
|
struct HAL_UART_CFG_T comm_uart_cfg;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
uart_opened = false;
|
|
|
|
memcpy(&comm_uart_cfg, &uart_cfg, sizeof(comm_uart_cfg));
|
|
|
|
hal_uart_open(comm_uart, &comm_uart_cfg);
|
|
|
|
mask.reg = 0;
|
|
|
|
mask.BE = 1;
|
|
|
|
mask.FE = 1;
|
|
|
|
mask.OE = 1;
|
|
|
|
mask.PE = 1;
|
|
|
|
hal_uart_irq_set_dma_handler(comm_uart, uart_rx_dma_handler, NULL);
|
|
|
|
hal_uart_irq_set_mask(comm_uart, mask);
|
|
|
|
uart_opened = true;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
cancel_xfer = false;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
hal_uart_flush(comm_uart, 0);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
void set_send_timeout(uint32_t timeout) { send_timeout = MS_TO_TICKS(timeout); }
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
int debug_read_enabled(void) {
|
|
|
|
return !!(hal_sw_bootmode_get() & HAL_SW_BOOTMODE_READ_ENABLED);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
int debug_write_enabled(void) {
|
|
|
|
return !!(hal_sw_bootmode_get() & HAL_SW_BOOTMODE_WRITE_ENABLED);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
static int uart_send_data(const unsigned char *buf, unsigned int len) {
|
|
|
|
uint32_t start;
|
|
|
|
uint32_t sent = 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
start = hal_sys_timer_get();
|
|
|
|
while (sent < len) {
|
|
|
|
while (!cancel_xfer && !hal_uart_writable(comm_uart) &&
|
|
|
|
hal_sys_timer_get() - start < send_timeout)
|
|
|
|
;
|
|
|
|
if (cancel_xfer) {
|
|
|
|
break;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
2023-02-01 14:52:54 -06:00
|
|
|
if (hal_uart_writable(comm_uart)) {
|
|
|
|
hal_uart_putc(comm_uart, buf[sent++]);
|
|
|
|
} else {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
if (sent != len) {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
int send_data(const unsigned char *buf, unsigned int len) {
|
|
|
|
if (cancel_xfer) {
|
|
|
|
return -1;
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
return uart_send_data(buf, len);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct HAL_DMA_DESC_T dma_desc[17] = {0};
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
static int uart_recv_data_dma(unsigned char *buf, unsigned int len,
|
|
|
|
unsigned int expect) {
|
|
|
|
int ret;
|
|
|
|
union HAL_UART_IRQ_T mask;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
uint32_t desc_cnt = ARRAY_SIZE(dma_desc);
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
if (uart_dma_rx_state != UART_DMA_IDLE) {
|
|
|
|
ret = -3;
|
|
|
|
goto _no_state_exit;
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
uart_dma_rx_state = UART_DMA_START;
|
|
|
|
uart_dma_rx_size = 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
|
|
|
#ifdef KNOWLES_UART_DATA
|
2023-02-01 14:52:54 -06:00
|
|
|
ret = hal_uart_dma_recv_pingpang(comm_uart, buf, expect, &dma_desc[0],
|
|
|
|
&desc_cnt);
|
2022-08-15 04:20:27 -05:00
|
|
|
#else
|
2023-02-01 14:52:54 -06:00
|
|
|
ret = hal_uart_dma_recv(comm_uart, buf, expect, &dma_desc[0], &desc_cnt);
|
2022-08-15 04:20:27 -05:00
|
|
|
#endif
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
if (ret) {
|
|
|
|
uart_dma_rx_state = UART_DMA_ERROR;
|
|
|
|
goto err_exit;
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
mask.reg = 0;
|
|
|
|
mask.BE = 1;
|
|
|
|
mask.FE = 1;
|
|
|
|
mask.OE = 1;
|
|
|
|
mask.PE = 1;
|
|
|
|
// mask.RT = 1;
|
|
|
|
hal_uart_irq_set_mask(comm_uart, mask);
|
2022-08-15 04:20:27 -05:00
|
|
|
|
|
|
|
_no_state_exit:
|
2023-02-01 14:52:54 -06:00
|
|
|
TRACE(2, "%s ret %d", __func__, ret);
|
|
|
|
return ret;
|
2022-08-15 04:20:27 -05:00
|
|
|
err_exit:
|
2023-02-01 14:52:54 -06:00
|
|
|
TRACE(2, "%s err_exit ret %d", __func__, ret);
|
|
|
|
return -1;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
int recv_data(unsigned char *buf, unsigned int len) {
|
|
|
|
TRACE(3, "%s %d %d", __func__, cancel_xfer, len);
|
|
|
|
if (cancel_xfer) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return uart_recv_data_dma(buf, len, len);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
int recv_data_dma(unsigned char *buf, unsigned int len, unsigned int expect) {
|
|
|
|
if (cancel_xfer) {
|
|
|
|
return -1;
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
return uart_recv_data_dma(buf, len, expect);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
static int uart_handle_error(void) {
|
|
|
|
TRACE(0, "****** Send break ******");
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
// Send break signal, to tell the peer to reset the connection
|
|
|
|
hal_uart_break_set(comm_uart);
|
|
|
|
osDelay(100);
|
|
|
|
hal_uart_break_clear(comm_uart);
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
return 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
int handle_error(void) {
|
|
|
|
int ret = 0;
|
|
|
|
uint32_t err_time;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
osDelay(200);
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
if (!cancel_xfer) {
|
|
|
|
ret = uart_handle_error();
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
xfer_err_cnt++;
|
|
|
|
err_time = hal_sys_timer_get();
|
|
|
|
if (err_time - xfer_err_time > MS_TO_TICKS(5000)) {
|
|
|
|
xfer_err_cnt = 0;
|
|
|
|
}
|
|
|
|
xfer_err_time = err_time;
|
|
|
|
if (xfer_err_cnt < 2) {
|
|
|
|
osDelay(500);
|
|
|
|
} else if (xfer_err_cnt < 5) {
|
|
|
|
osDelay(1000);
|
|
|
|
} else {
|
|
|
|
osDelay(2000);
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
return ret;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
static int uart_cancel_input(void) {
|
|
|
|
hal_uart_flush(comm_uart, 0);
|
|
|
|
return 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
int cancel_input(void) { return uart_cancel_input(); }
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
void system_reboot(void) { hal_cmu_sys_reboot(); }
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
void system_shutdown(void) { pmu_shutdown(); }
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
void system_set_bootmode(unsigned int bootmode) {
|
|
|
|
bootmode &= ~(HAL_SW_BOOTMODE_READ_ENABLED | HAL_SW_BOOTMODE_WRITE_ENABLED);
|
|
|
|
hal_sw_bootmode_set(bootmode);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
void system_clear_bootmode(unsigned int bootmode) {
|
|
|
|
bootmode &= ~(HAL_SW_BOOTMODE_READ_ENABLED | HAL_SW_BOOTMODE_WRITE_ENABLED);
|
|
|
|
hal_sw_bootmode_clear(bootmode);
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
unsigned int system_get_bootmode(void) { return hal_sw_bootmode_get(); }
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
void wait_trace_finished(void) {
|
|
|
|
uint32_t time;
|
|
|
|
int idle_cnt = 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
time = hal_sys_timer_get();
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
while (idle_cnt < 2 && hal_sys_timer_get() - time < WAIT_TRACE_TIMEOUT) {
|
|
|
|
osDelay(10);
|
|
|
|
idle_cnt = hal_trace_busy() ? 0 : (idle_cnt + 1);
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
unsigned int get_current_time(void) { return hal_sys_timer_get(); }
|
2022-08-15 04:20:27 -05:00
|
|
|
|
|
|
|
#ifdef KNOWLES_UART_DATA
|
|
|
|
uint8_t *uart_stream_buf;
|
|
|
|
bool send_start_speech = false;
|
|
|
|
extern bool is_markers_read_done;
|
|
|
|
#endif
|
|
|
|
#ifdef KNOWLES_UART_DATA
|
2023-02-01 14:52:54 -06:00
|
|
|
osThreadId knowles_uart_audio_tid = NULL;
|
2022-08-15 04:20:27 -05:00
|
|
|
static void uart_data_process_thread(const void *arg);
|
2023-02-01 14:52:54 -06:00
|
|
|
osThreadDef(uart_data_process_thread, (osPriorityAboveNormal), 1, (1024 * 12),
|
|
|
|
"UART_DATA");
|
|
|
|
|
|
|
|
int app_ai_voice_uart_audio_init() {
|
|
|
|
ama_uart_stream_fifo_init();
|
|
|
|
if (knowles_uart_audio_tid == NULL)
|
|
|
|
knowles_uart_audio_tid =
|
|
|
|
osThreadCreate(osThread(uart_data_process_thread), NULL);
|
|
|
|
if (knowles_uart_audio_tid == NULL) {
|
|
|
|
TRACE(0, "[UART AUDIO]Create thread error\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
return 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
2023-02-01 14:52:54 -06:00
|
|
|
void uart_data_process_thread(const void *arg) {
|
|
|
|
uint32_t ret = 0;
|
|
|
|
uint32_t frame_len = 0;
|
|
|
|
// uint32_t stime,etime;
|
|
|
|
// stime=hal_sys_timer_get();
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
// TRACE(0,"---in uart_process_thread\n");
|
|
|
|
osEvent evt;
|
|
|
|
|
|
|
|
if (avil_len_of_the_fifo() <= 640) {
|
|
|
|
evt = osSignalWait(0x0, osWaitForever);
|
|
|
|
}
|
|
|
|
|
|
|
|
// TRACE(1,"#####Available len of fifo %d####",avil_len_of_the_fifo());
|
|
|
|
// get role from signal value
|
|
|
|
if (evt.status == osEventSignal) {
|
|
|
|
if (evt.value.signals & UART_OUT_SIGNAL_ID) {
|
|
|
|
if (app_ai_is_stream_running()) {
|
|
|
|
frame_len = ama_uart_get_fifo_data(uart_stream_buf);
|
|
|
|
} else {
|
|
|
|
frame_len = 0;
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
if (frame_len != 0) {
|
|
|
|
TRACE(1, "--data start encode %d", frame_len);
|
|
|
|
// DUMP8("%02x ",uart_stream_buf,10);
|
|
|
|
|
|
|
|
// stime=hal_sys_timer_get();
|
|
|
|
|
|
|
|
ret = voice_compression_handle(app_ai_get_encode_type(),
|
|
|
|
uart_stream_buf,
|
|
|
|
VOB_PCM_SIZE_TO_SAMPLE_CNT(640),
|
|
|
|
app_ai_is_algorithm_engine_reset());
|
|
|
|
app_ai_set_algorithm_engine_reset(false);
|
|
|
|
|
|
|
|
ai_function_handle(API_DATA_SEND, NULL, 0);
|
|
|
|
|
|
|
|
// etime=hal_sys_timer_get();
|
|
|
|
// TRACE(1,"OPUS COST TIME %d", TICKS_TO_MS(etime-stime));
|
|
|
|
// TRACE(2,"%s ====>sys freq calc : %d\n", __func__,
|
|
|
|
// hal_sys_timer_calc_cpu_freq(50, 0));
|
|
|
|
audio_dump_add_channel_data(0, (short *)uart_stream_buf,
|
|
|
|
frame_len / 2);
|
|
|
|
audio_dump_run();
|
|
|
|
send_message();
|
|
|
|
if (ret < 0) {
|
|
|
|
goto __EXCEPTION;
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
2023-02-01 14:52:54 -06:00
|
|
|
}
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
continue;
|
2022-08-15 04:20:27 -05:00
|
|
|
|
2023-02-01 14:52:54 -06:00
|
|
|
__EXCEPTION:
|
|
|
|
app_ai_voice_stop_stream();
|
|
|
|
}
|
2022-08-15 04:20:27 -05:00
|
|
|
}
|
|
|
|
#endif
|