586 lines
19 KiB
C
586 lines
19 KiB
C
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/**************************************************************************//**
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* @file cmsis_armclang.h
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* @brief CMSIS compiler specific macros, functions, instructions
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* @version V1.1.1
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* @date 15. May 2019
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __CMSIS_ARMCLANG_CA_H
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#define __CMSIS_ARMCLANG_CA_H
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#pragma clang system_header /* treat file as system include file */
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#ifndef __ARM_COMPAT_CA_H
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#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
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#endif
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE __inline
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#endif
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#ifndef __FORCEINLINE
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#define __FORCEINLINE __attribute__((always_inline))
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static __inline
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#endif
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((__noreturn__))
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#endif
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#ifndef CMSIS_DEPRECATED
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#define CMSIS_DEPRECATED __attribute__((deprecated))
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed, aligned(1)))
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
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#endif
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/* ########################## Core Instruction Access ######################### */
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/**
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\brief No Operation
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*/
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#define __NOP __builtin_arm_nop
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/**
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\brief Wait For Interrupt
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*/
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#define __WFI __builtin_arm_wfi
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/**
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\brief Wait For Event
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*/
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#define __WFE __builtin_arm_wfe
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/**
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\brief Send Event
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*/
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#define __SEV __builtin_arm_sev
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/**
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\brief Instruction Synchronization Barrier
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*/
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#define __ISB() do {\
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__schedule_barrier();\
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__builtin_arm_isb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Synchronization Barrier
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*/
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#define __DSB() do {\
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__schedule_barrier();\
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__builtin_arm_dsb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Memory Barrier
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*/
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#define __DMB() do {\
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__schedule_barrier();\
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__builtin_arm_dmb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV(value) __builtin_bswap32(value)
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV16(value) __ROR(__REV(value), 16)
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REVSH(value) (int16_t)__builtin_bswap16(value)
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/**
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\brief Rotate Right in unsigned value (32 bit)
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\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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\param [in] op1 Value to rotate
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\param [in] op2 Number of Bits to rotate
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\return Rotated value
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*/
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__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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{
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op2 %= 32U;
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if (op2 == 0U)
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{
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return op1;
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}
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return (op1 >> op2) | (op1 << (32U - op2));
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}
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/**
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\brief Breakpoint
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __ASM volatile ("bkpt "#value)
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/**
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\brief Reverse bit order of value
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __RBIT __builtin_arm_rbit
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/**
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\brief Count leading zeros
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
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{
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/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
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__builtin_clz(0) is undefined behaviour, so handle this case specially.
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This guarantees ARM-compatible results if happening to compile on a non-ARM
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target, and ensures the compiler doesn't decide to activate any
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optimisations using the logic "value was passed to __builtin_clz, so it
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is non-zero".
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ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
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single CLZ instruction.
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*/
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if (value == 0U)
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{
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return 32U;
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}
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return __builtin_clz(value);
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}
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/**
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\brief LDR Exclusive (8 bit)
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\details Executes a exclusive LDR instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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#define __LDREXB (uint8_t)__builtin_arm_ldrex
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/**
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\brief LDR Exclusive (16 bit)
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\details Executes a exclusive LDR instruction for 16 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
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*/
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#define __LDREXH (uint16_t)__builtin_arm_ldrex
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/**
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\brief LDR Exclusive (32 bit)
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\details Executes a exclusive LDR instruction for 32 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint32_t at (*ptr)
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*/
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#define __LDREXW (uint32_t)__builtin_arm_ldrex
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/**
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\brief STR Exclusive (8 bit)
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\details Executes a exclusive STR instruction for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXB (uint32_t)__builtin_arm_strex
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/**
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\brief STR Exclusive (16 bit)
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\details Executes a exclusive STR instruction for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXH (uint32_t)__builtin_arm_strex
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/**
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\brief STR Exclusive (32 bit)
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\details Executes a exclusive STR instruction for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXW (uint32_t)__builtin_arm_strex
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/**
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\brief Remove the exclusive lock
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\details Removes the exclusive lock which is created by LDREX.
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*/
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#define __CLREX __builtin_arm_clrex
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/**
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\brief Signed Saturate
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\details Saturates a signed value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (1..32)
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\return Saturated value
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*/
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#define __SSAT __builtin_arm_ssat
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/**
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\brief Unsigned Saturate
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\details Saturates an unsigned value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (0..31)
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\return Saturated value
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*/
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#define __USAT __builtin_arm_usat
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/* ################### Compiler specific Intrinsics ########################### */
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/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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Access to dedicated SIMD instructions
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@{
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*/
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#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
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#define __QADD8 __builtin_arm_qadd8
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#define __QSUB8 __builtin_arm_qsub8
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#define __QADD16 __builtin_arm_qadd16
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#define __SHADD16 __builtin_arm_shadd16
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#define __QSUB16 __builtin_arm_qsub16
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#define __SHSUB16 __builtin_arm_shsub16
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#define __QASX __builtin_arm_qasx
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#define __SHASX __builtin_arm_shasx
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#define __QSAX __builtin_arm_qsax
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#define __SHSAX __builtin_arm_shsax
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#define __SXTB16 __builtin_arm_sxtb16
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#define __SMUAD __builtin_arm_smuad
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#define __SMUADX __builtin_arm_smuadx
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#define __SMLAD __builtin_arm_smlad
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#define __SMLADX __builtin_arm_smladx
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#define __SMLALD __builtin_arm_smlald
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#define __SMLALDX __builtin_arm_smlaldx
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#define __SMUSD __builtin_arm_smusd
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#define __SMUSDX __builtin_arm_smusdx
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#define __SMLSDX __builtin_arm_smlsdx
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__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
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{
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int32_t result;
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__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
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{
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int32_t result;
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__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||
|
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||
|
|
|
||
|
|
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||
|
|
{
|
||
|
|
int32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* (__ARM_FEATURE_DSP == 1) */
|
||
|
|
|
||
|
|
/* ########################### Core Function Access ########################### */
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get FPSCR
|
||
|
|
\details Returns the current value of the Floating Point Status/Control register.
|
||
|
|
\return Floating Point Status/Control register value
|
||
|
|
*/
|
||
|
|
#define __get_FPSCR __builtin_arm_get_fpscr
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Set FPSCR
|
||
|
|
\details Assigns the given value to the Floating Point Status/Control register.
|
||
|
|
\param [in] fpscr Floating Point Status/Control value to set
|
||
|
|
*/
|
||
|
|
#define __set_FPSCR __builtin_arm_set_fpscr
|
||
|
|
|
||
|
|
/** \brief Get CPSR Register
|
||
|
|
\return CPSR Register value
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Set CPSR Register
|
||
|
|
\param [in] cpsr CPSR value to set
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
|
||
|
|
{
|
||
|
|
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Get Mode
|
||
|
|
\return Processor Mode
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE uint32_t __get_mode(void)
|
||
|
|
{
|
||
|
|
return (__get_CPSR() & 0x1FU);
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Set Mode
|
||
|
|
\param [in] mode Mode value to set
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
|
||
|
|
{
|
||
|
|
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Get Stack Pointer
|
||
|
|
\return Stack Pointer value
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE uint32_t __get_SP()
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Set Stack Pointer
|
||
|
|
\param [in] stack Stack Pointer value to set
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
|
||
|
|
{
|
||
|
|
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Get USR/SYS Stack Pointer
|
||
|
|
\return USR/SYS Stack Pointer value
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE uint32_t __get_SP_usr()
|
||
|
|
{
|
||
|
|
uint32_t cpsr;
|
||
|
|
uint32_t result;
|
||
|
|
__ASM volatile(
|
||
|
|
"MRS %0, cpsr \n"
|
||
|
|
"CPS #0x1F \n" // no effect in USR mode
|
||
|
|
"MOV %1, sp \n"
|
||
|
|
"MSR cpsr_c, %0 \n" // no effect in USR mode
|
||
|
|
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
|
||
|
|
);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Set USR/SYS Stack Pointer
|
||
|
|
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
|
||
|
|
{
|
||
|
|
uint32_t cpsr;
|
||
|
|
__ASM volatile(
|
||
|
|
"MRS %0, cpsr \n"
|
||
|
|
"CPS #0x1F \n" // no effect in USR mode
|
||
|
|
"MOV sp, %1 \n"
|
||
|
|
"MSR cpsr_c, %0 \n" // no effect in USR mode
|
||
|
|
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Get FPEXC
|
||
|
|
\return Floating Point Exception Control register value
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
|
||
|
|
{
|
||
|
|
#if (__FPU_PRESENT == 1)
|
||
|
|
uint32_t result;
|
||
|
|
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
|
||
|
|
return(result);
|
||
|
|
#else
|
||
|
|
return(0);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/** \brief Set FPEXC
|
||
|
|
\param [in] fpexc Floating Point Exception Control value to set
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
|
||
|
|
{
|
||
|
|
#if (__FPU_PRESENT == 1)
|
||
|
|
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Include common core functions to access Coprocessor 15 registers
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||
|
|
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||
|
|
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||
|
|
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||
|
|
|
||
|
|
#include "ca/cmsis_cp15_ca.h"
|
||
|
|
|
||
|
|
/** \brief Enable Floating Point Unit
|
||
|
|
|
||
|
|
Critical section, called from undef handler, so systick is disabled
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void __FPU_Enable(void)
|
||
|
|
{
|
||
|
|
__ASM volatile(
|
||
|
|
//Permit access to VFP/NEON, registers by modifying CPACR
|
||
|
|
" MRC p15,0,R1,c1,c0,2 \n"
|
||
|
|
" ORR R1,R1,#0x00F00000 \n"
|
||
|
|
" MCR p15,0,R1,c1,c0,2 \n"
|
||
|
|
|
||
|
|
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
|
||
|
|
" ISB \n"
|
||
|
|
|
||
|
|
//Enable VFP/NEON
|
||
|
|
" VMRS R1,FPEXC \n"
|
||
|
|
" ORR R1,R1,#0x40000000 \n"
|
||
|
|
" VMSR FPEXC,R1 \n"
|
||
|
|
|
||
|
|
//Initialise VFP/NEON registers to 0
|
||
|
|
" MOV R2,#0 \n"
|
||
|
|
|
||
|
|
//Initialise D16 registers to 0
|
||
|
|
" VMOV D0, R2,R2 \n"
|
||
|
|
" VMOV D1, R2,R2 \n"
|
||
|
|
" VMOV D2, R2,R2 \n"
|
||
|
|
" VMOV D3, R2,R2 \n"
|
||
|
|
" VMOV D4, R2,R2 \n"
|
||
|
|
" VMOV D5, R2,R2 \n"
|
||
|
|
" VMOV D6, R2,R2 \n"
|
||
|
|
" VMOV D7, R2,R2 \n"
|
||
|
|
" VMOV D8, R2,R2 \n"
|
||
|
|
" VMOV D9, R2,R2 \n"
|
||
|
|
" VMOV D10,R2,R2 \n"
|
||
|
|
" VMOV D11,R2,R2 \n"
|
||
|
|
" VMOV D12,R2,R2 \n"
|
||
|
|
" VMOV D13,R2,R2 \n"
|
||
|
|
" VMOV D14,R2,R2 \n"
|
||
|
|
" VMOV D15,R2,R2 \n"
|
||
|
|
|
||
|
|
#if __ARM_NEON == 1
|
||
|
|
//Initialise D32 registers to 0
|
||
|
|
" VMOV D16,R2,R2 \n"
|
||
|
|
" VMOV D17,R2,R2 \n"
|
||
|
|
" VMOV D18,R2,R2 \n"
|
||
|
|
" VMOV D19,R2,R2 \n"
|
||
|
|
" VMOV D20,R2,R2 \n"
|
||
|
|
" VMOV D21,R2,R2 \n"
|
||
|
|
" VMOV D22,R2,R2 \n"
|
||
|
|
" VMOV D23,R2,R2 \n"
|
||
|
|
" VMOV D24,R2,R2 \n"
|
||
|
|
" VMOV D25,R2,R2 \n"
|
||
|
|
" VMOV D26,R2,R2 \n"
|
||
|
|
" VMOV D27,R2,R2 \n"
|
||
|
|
" VMOV D28,R2,R2 \n"
|
||
|
|
" VMOV D29,R2,R2 \n"
|
||
|
|
" VMOV D30,R2,R2 \n"
|
||
|
|
" VMOV D31,R2,R2 \n"
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//Initialise FPSCR to a known state
|
||
|
|
" VMRS R1,FPSCR \n"
|
||
|
|
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||
|
|
" AND R1,R1,R2 \n"
|
||
|
|
" VMSR FPSCR,R1 "
|
||
|
|
: : : "cc", "r1", "r2"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __CMSIS_ARMCLANG_CA_H */
|